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| features ? high performance, low power avr ? 8-bit microcontroller ? advanced risc architecture ? 135 powerful instructions ? mo st single clock cycle execution ? 32 8 general purpose working registers ? fully static operation ? up to 16mips throughput at 16mhz ? on-chip 2-cycle multiplier ? non-volatile program and data memories ? 64/128kbytes of in-system self-programmable flash ? endurance: 100,000 write/erase cycles ? optional boot code section with independent lock bits ? usb boot loader programmed by default in the factory ? in-system programming by on-chip boot program hardware activated after reset ? true read-while-write operation ? all supplied parts are pre-programed with a default usb bootloader ? 2k/4k (64k/128k flash version) bytes eeprom ? endurance: 100,000 write/erase cycles ? 4k/8k (64k/128k flash version) bytes internal sram ? up to 64kbytes optional external memory space ? programming lock for software security ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities acc ording to the jtag standard ? extensive on-chip debug support ? programming of flash, eeprom , fuses, and lock bits th rough the jtag interface ? usb 2.0 full-speed/l ow-speed device and on-the-go module ? complies fully with: ? universal serial bus specification rev 2.0 ? on-the-go supplement to the usb 2.0 specification rev 1.0 ? supports data transfer rates up to 12mbit/s and 1.5mbit/s ? usb full-speed/low speed device module with interrupt on transfer completion ? endpoint 0 for control tr ansfers: up to 64-bytes ? six programmable endpoints with in or out directions and with bulk, interrupt or isochronous transfers ? configurable endpoints size up to 256bytes in double bank mode ? fully independent 832bytes usb dpram for endpoint me mory allocation ? suspend/resume interrupts ? power-on reset and usb bus reset ? 48mhz pll for full-speed bus operation ? usb bus disconnection on microcontroller request ? usb otg reduced host: ? supports host negotiation protocol (hnp) and session request protocol (srp) for otg dual-role devices ? provide status and control signals for software implementation of hnp and srp ? provides programmable times required for hnp and srp ? peripheral features ? two 8-bit timer/counters with separate prescaler and compare mode ? two16-bit timer/counter with separate prescaler, compare- and capture mode 8-bit atmel microcontroller with 64/128kbytes of isp flash and usb controller at90usb646 at90usb647 at90usb1286 at90usb1287 7593l?avr?09/12
2 7593l?avr?09/12 at90usb64/128 ? real time counter with separate oscillator ? four 8-bit pwm channels ? six pwm channels with programmab le resolution from 2 to 16 bits ? output compare modulator ? 8-channels, 10-bit adc ? programmable serial usart ? master/slave spi serial interface ? byte oriented 2-wi re serial interface ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal calibra ted oscillator ? external and internal interrupt sources ? six sleep modes: idle, adc noise reduction, powe r-save, power-down, standby, and extended standby ? i/o and packages ? 48 programmable i/o lines ? 64-lead tqfp and 64-lead qfn ? operating voltages ? 2.7 - 5.5v ? operating temperature ? industrial (- 40c to +85c) ? maximum frequency ? 8mhz at 2.7v - industrial range ? 16mhz at 4.5v - industrial range 3 7593l?avr?09/12 at90usb64/128 1. pin configurations figure 1-1. pinout atmel at90 usb64/128-tqfp. at90usb90128/64 tqfp64 (int.7/ain.1/uvcon) pe7 uvcc d- d+ ugnd ucap vbus (iuid) pe3 (ss/pcint0) pb0 (int.6/ain.0) pe6 (pcint1/sclk) pb1 (pdi/pcint2/mosi) pb2 (pdo/pcint3/miso) pb3 (pcint4/oc.2a) pb4 (pcint5/oc.1a) pb5 (pcint6/oc.1b) pb6 (pcint7/oc.0a/oc.1c) pb7 (int4/tosc1) pe4 (int.5/tosc2) pe5 reset vcc gnd xtal2 xtal1 (oc0b/scl/int0) pd0 (oc2b/sda/int1) pd1 (rxd1/int2) pd2 (txd1/int3) pd3 (icp1) pd4 (xck1) pd5 pa3 (ad3) pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pe2 (ale/hwb) pc7 (a15/ic.3/clko) pc6 (a14/oc.3a) pc5 (a13/oc.3b) pc4 (a12/oc.3c) pc3 (a11/t.3) pc2 (a10) pc1 (a9) pc0 (a8) pe1 (rd) pe0 (wr) avcc gnd aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) pf7 (adc7/tdi) gnd vcc pa0 (ad0) pa1 (ad1) pa2 (ad2) (t1) pd6 (t0) pd7 index corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4 7593l?avr?09/12 at90usb64/128 figure 1-2. pinout atmel at 90usb64/128-qfn. note: the large center pad underneath the mlf packages is made of metal and internally connected to gnd. it should be soldered or glued to the boar d to ensure good mechanical stability. if the center pad is left unconnected, the packa ge might loosen from the board. 2 3 1 4 5 6 7 8 9 10 11 12 13 14 16 33 15 47 46 48 45 44 43 42 41 40 39 38 37 36 35 34 17 18 20 19 21 22 23 24 25 26 27 29 28 32 31 30 52 51 50 49 64 63 62 53 61 60 59 58 57 56 55 54 at90usb12 8 /64 (64-lead qf n top view) i n dex cor n er a v cc g n d aref pf0 (adc0) pf1 (adc1) pf2 (adc2) pf3 (adc3) pf4 (adc4/tck) pf5 (adc5/tms) pf6 (adc6/tdo) pf7 (adc7/tdi) g n d v cc pa0 (ad0) pa1 (ad1) pa2 (ad2) (i n t.7/ai n .1/u v con) pe7 u v cc d- d+ ugnd ucap v b u s (iuid) pe3 (ss/pci n t0) pb0 (i n t.6/ai n .0) pe6 (pci n t1/sclk) pb1 (pdi/pci n t2/mosi) pb2 (pdo/pci n t3/miso) pb3 (pci n t4/oc.2a) pb4 (pci n t5/oc.1a) pb5 (pci n t6/oc.1b) pb6 (pci n t7/oc.0a/oc.1c) pb7 (i n t4/tosc1) pe4 (i n t.5/tosc2) pe5 v cc g n d xtal2 xtal1 (oc0b/scl/i n t0) pd0 (oc2b/sda/i n t1) pd1 (rxd1/i n t2) pd2 (txd1/i n t3) pd3 (icp1) pd4 (xck1) pd5 (t1) pd6 (t0) pd7 reset pa3 (ad3) pa4 (ad4) pa5 (ad5) pa6 (ad6) pa7 (ad7) pe2 (ale/h w b) pc7 (a15/ic.3/clko) pc6 (a14/oc.3a) pc5 (a13/oc.3b) pc4 (a12/oc.3c) pc3 (a11/t.3) pc2 (a10) pc1 (a9) pc0 (a 8 ) pe1 (rd) pe0 ( w r) 5 7593l?avr?09/12 at90usb64/128 2. overview the atmel ? avr ? at90usb64/128 is a lo w -po w er cmos 8-bit microcontroller based on the atmel ? avr ? enhanced risc architecture. by executing po w erful instructions in a single clock cycle, the at90usb64/128 achie v es throughputs approaching 1mips per mhz allo w ing the sys- tem designer to optimize po w er consumption v ersus processing speed. 6 7593l?avr?09/12 at90usb64/128 2.1 block diagram figure 2-1. block diagram. the avr core combines a rich instruction set w ith 32 general purpose w orking registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allo w ing t w o independent registers to be accessed in one single instruction executed in one clock cycle. the resulting program counter st ack pointer program flash mcu control register sram general purpose registers instruction register timer/ counters instruction decoder data dir. reg. port b data dir. reg. port e data dir. reg. port a data dir. reg. port d data register port b data register port e data register port a data register port d interrupt unit eeprom spi usart1 st atus register z y x alu por t b drivers por t e drivers por t a drivers por t f drivers por t d drivers por t c drivers pb7 - pb0 pe7 - pe0 pa7 - p a0 pf7 - pf0 reset vcc agnd gnd aref xt al1 xt al2 control lines + - analog comp arator pc7 - pc0 internal oscilla tor watchdog timer 8-bit da ta bus avcc usb timing and control oscilla tor calib. osc data dir. reg. port c data register port c on-chip debug jtag tap programming logic boundary- scan data dir. reg. port f data register port f adc por - bod reset pd7 - pd0 two-wire serial interface pll 7 7593l?avr?09/12 at90usb64/128 architecture is more code efficient w hile achie v ing throughputs up to ten times faster than con- v entional cisc microcontrollers. the atmel at90usb64/128 pro v ides the follo w ing features: 64/128kbytes of in-system pro- grammable flash w ith read-while-write capabilities, 2k/4kbytes eeprom, 4k/8k bytes sram, 48 general purpose i/o lines, 32 general purpose w orking registers, real time counter (rtc), four flexible timer/counters w ith compare modes and pwm, one usart, a byte ori- ented 2- w ire serial interface, a 8-channels, 10-bit adc w ith optional differential input stage w ith programmable gain, programmable watchdog timer w ith internal oscillator, an spi serial port, ieee std. 1149.1 compliant jtag test interface, also used for accessing the on-chip debug sys- tem and programming and six soft w are selectable po w er sa v ing modes. the idle mode stops the cpu w hile allo w ing the sram, timer/counters, spi port, and interrupt system to continue functioning. the po w er-do w n mode sa v es the register contents but freezes the oscillator, dis- abling all other chip functions until the next interrupt or hard w are reset. in po w er-sa v e mode, the asynchronous timer continues to run, allo w ing the user to maintain a timer base w hile the rest of the de v ice is sleeping. the adc noise reduction mode stops the cpu and all i/o mod- ules except asynchronous timer and adc, to minimize s w itching noise during adc con v ersions. in standby mode, the crystal/resonator oscillator is running w hile the rest of the de v ice is sleeping. this allo w s v ery fast start-up combined w ith lo w po w er consumption. in extended standby mode, bo th the main oscillator and the asynchronous ti mer continue to run. the de v ice is manufactured using the atmel high-density non v olatile memory technology. the on-chip isp flash allo w s the program memory to be repr ogrammed in-system through an spi serial interface, by a con v entional non v olatile memory programmer, or by an on-chip boot pro- gram running on the avr core. the boot program can use any interface to do w nload the application program in the application flash memory. soft w are in the boot flash section w ill continue to run w hile the application flash section is updated, pro v iding true read-while-write operation. by combining an 8-bit risc cpu w ith in-system self-programmable flash on a monolithic chip, the at90usb64/128 is a po w erful microcontroller that pro v ides a highly flexible and cost effecti v e solution to many embedded control applications. the at90usb64/128 avr is supported w ith a full suite of program and system de v elopment tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emula- tors, and e v aluation kits. 8 7593l?avr?09/12 at90usb64/128 2.2 pin descriptions 2.2.1 vcc digital supply v oltage. 2.2.2 gnd ground. 2.2.3 avcc analog supply v oltage. 2.2.4 port a (pa7..pa0) port a is an 8-bit bidirectional i/o port w ith internal pull-up resistors (selected for each bit). the port a output buffers ha v e symmetrical dri v e characteristics w ith both high sink and source capability. as inputs, port a pi ns that are exte rnally pulled lo w w ill source current if the pull-up resistors are acti v ated. the port a pins are tri-stated w hen a reset condition becomes acti v e, e v en if the clock is not running. port a also ser v es the functions of v arious special features of the atmel at90usb64/128 as listed on page 78 . 2.2.5 port b (pb7..pb0) port b is an 8-bit bidirectional i/o port w ith internal pull-up resistors (selected for each bit). the port b output buffers ha v e symmetrical dri v e characteristics w ith both high sink and source capability. as inputs, port b pi ns that are exte rnally pulled lo w w ill source current if the pull-up resistors are acti v ated. the port b pins are tri-stated w hen a reset condition becomes acti v e, e v en if the clock is not running. port b has better dri v ing capabilities th an the other ports. port b also ser v es the functions of v arious special features of the at90usb64/128 as listed on page 79 . 2.2.6 port c (pc7..pc0) port c is an 8-bit bidirectional i/o port w ith internal pull-up resistors (selected for each bit). the port c output buffers ha v e symmetrical dri v e characteristics w ith both high sink and source capability. as inputs, port c pi ns that are externally pulled lo w w ill source current if the pull-up resistors are acti v ated. the port c pins are tri-stated w hen a reset condition becomes acti v e, e v en if the clock is not running. port c also ser v es the functions of special features of the at90usb64/128 as listed on page 82 . 2.2.7 port d (pd7..pd0) port d is an 8-bit bi-directional i/o port w ith internal pull-up resistors (selected for each bit). the port d output buffers ha v e symmetrical dri v e characteristics w ith both high sink and source capability. as inputs, port d pi ns that are externally pulled lo w w ill source current if the pull-up resistors are acti v ated. the port d pins are tri-stated w hen a reset condition becomes acti v e, e v en if the clock is not running. port d also ser v es the functions of v arious special features of the at90usb64/128 as listed on page 83 . 9 7593l?avr?09/12 at90usb64/128 2.2.8 port e (pe7..pe0) port e is an 8-bit bidirectional i/o port w ith internal pull-up resistors (selected for each bit). the port e output buffers ha v e symmetrical dri v e characteristics w ith both high sink and source capability. as inputs, port e pi ns that are exte rnally pulled lo w w ill source current if the pull-up resistors are acti v ated. the port e pins are tri-stated w hen a reset condition becomes acti v e, e v en if the clock is not running. port e also ser v es the functions of v arious special features of the at90usb64/128 as listed on page 86 . 2.2.9 port f (pf7..pf0) port f ser v es as analog inputs to the a/d con v erter. port f also ser v es as an 8-bit bidirectional i/o port, if the a/d con v erter is not used. port pins can pro v ide internal pull-up resistors (selected for each bit). the port f output buffers ha v e sym- metrical dri v e characteristics w ith both high sink an d source capability. as inputs, port f pins that are externally pulled lo w w ill source current if the pull-up resistors are acti v ated. the port f pins are tri-stated w hen a reset condition becomes acti v e, e v en if the clock is not running. if the jtag interface is enabled, the pull-up resistors on pins pf7(tdi), pf5(tms), and pf4(tck) w ill be acti v ated e v en if a reset occurs. port f also ser v es the functions of the jtag interface. 2.2.10 d- usb full speed / lo w speed negati v e data upstream port. should be connected to the usb d- connector pin w ith a serial 22 resistor. 2.2.11 d+ usb full speed / lo w speed positi v e data upstream port. should be connected to the usb d+ connector pin w ith a serial 22 resistor. 2.2.12 ugnd usb pads ground. 2.2.13 uvcc usb pads internal regulator input supply v oltage. 2.2.14 ucap usb pads internal regulator output supply v oltage. should be connected to an external capac- itor (1f). 2.2.15 vbus usb vbus monitor and otg negociations. 2.2.16 reset reset input. a lo w le v el on this pin for longer than the minimum pulse length w ill generate a reset, e v en if the clock is not running. the minimum pulse length is gi v en in table 9-1 on page 58 . shorter pulses are not guaranteed to generate a reset. 2.2.17 xtal1 input to the in v erting oscillator amplifier and input to the internal clock operating circuit. 10 7593l?avr?09/12 at90usb64/128 2.2.18 xtal2 output from the in v erting oscillator amplifier. 2.2.19 avcc avcc is the supply v oltage pin for port f and the a/d con v erter. it should be externally con- nected to v cc , e v en if the adc is not used. if the adc is used, it should be connected to v cc through a lo w -pass filter. 2.2.20 aref this is the analog reference pin for the a/d con v erter. 3. resources a comprehensi v e set of de v elopment tools, application notes and datasheets are a v ailable for do w nload on http:// www .atmel.com/a v r . 4. about code examples this documentation contains simple code examples that briefly sho w ho w to use v arious parts of the de v ice. be a w are that not all c compiler v endors include bit definitions in the header files and interrupt handling in c is compiler dependent. please confirm w ith the c compiler documen- tation for more details. these code examples assume that the part specific header file is included before compilation. for i/o registers located in extended i/o map, "i n", "out", "sbis", "sbic", "cbi", and "sbi" instructions must be replaced w ith instructions that allo w access to extended i/o. typically "lds" and "sts" combined w ith "sbrs", "sbrc", "sbr", and "cbr". 11 7593l?avr?09/12 at90usb64/128 5. avr cpu core 5.1 introduction this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 architectural overview figure 5-1. block diagram of the avr architecture. in order to maximize performance and parallelism, the avr uses a har v ard architecture ? w ith separate memories and buses for program and data. instructions in the program memory are executed w ith a single le v el pipelining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in e v ery clock cycle. the program memory is in-system re-programmable flash memory. flash program memory instruction register instruction decoder program counter control lines 32 x 8 general purpose registrers alu status and control i/o lines eeprom data bus 8-bit data sram direct addressing indirect addressing interrupt unit spi unit watchdog timer analog comparator i/o module 2 i/o module1 i/o module n 12 7593l?avr?09/12 at90usb64/128 the fast-access register file contains 32 8-bit general purpose w orking registers w ith a single clock cycle access time. this allo w s single-cycle arithmetic logic unit (alu) operation. in a typ- ical alu operation, t w o operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-b it indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations bet w een registers or bet w een a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is updated to reflect information about the result of the operation. program flo w is pro v ided by conditional and unconditional jump and call instructions, able to directly address the w hole address space. most avr instructions ha v e a single 16-bit w ord for- mat. e v ery program memory address contains a 16- or 32-bit instruction. program flash memory space is di v ided in t w o sections, the boot program section and the application program section. both sections ha v e dedicated lock bits for w rite and read/ w rite protection. the spm instruction that w rites into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effecti v ely allocated in the general data sram, and consequently the stack size is only limited by the to tal sram size and the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/ w rite accessible in the i/o space. the data sram can easily be accessed through the fi v e different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control registers in the i/o space w ith an additional global interrupt enable bit in the stat us register. all interrupts ha v e a separate interrupt vector in the interrupt vector table. the interrupts ha v e priority in accordance w ith their interrupt vector posi- tion. the lo w er the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functi ons as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations follo w ing those of the register file, 0x20 - 0x5f. in addition, the atmel at90usb64/128 has extended i/o space from 0x60 - 0xff in sram w here only the st/sts/std and ld/lds/ldd instructions can be used. 5.3 alu ? arithm etic logic unit the high-performance avr alu operates in direct connection w ith all the 32 general purpose w orking registers. within a single clock cycle, arithmetic operations bet w een general purpose registers or bet w een a register and an immediate are executed. the alu operations are di v ided into three main categories ? arithmetic, logical, and bit-functions. some implementations of the architecture also pro v ide a po w erful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set summary? on page 423 for a detailed description. 13 7593l?avr?09/12 at90usb64/128 5.4 status register the status register contains information about the result of the most recently executed arithmetic instruction. this information can be used for altering program flo w in order to perform conditional operations. note that the status register is updat ed after all alu operations, as specified in the instruction set reference. this w ill in many cases remo v e the need for using the dedicated com- pare instructions, resulting in faster and more compact code. the status register is not automatically stored w hen entering an interrupt routine and restored w hen returning from an interrupt. this must be handled by soft w are. the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for the interrupts to be enabled. the indi v idual inter- rupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the indi v idual interrupt enable settings. the i-bit is cleared by hard w are after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application w ith the sei and cli instructions, as de scribed in the instru ction set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (b it store) use the t-bit as source or desti- nation for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in so me arithmetic operations. half carry is useful in bcd arithmetic. see the ?instruction set summary? on page 423 for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is al w ays an exclusi v e or bet w een the negati v e flag n and the t w o?s complement o v erflo w flag v. see the ?instruction set summary? on page 423 for detailed information. ? bit 3 ? v: two?s complement overflow flag the t w o?s complement o v erflo w flag v supports t w o?s complement arithmetics. see the ?instruction set summary? on page 423 for detailed information. ? bit 2 ? n: negative flag the negati v e flag n indicates a negati v e result in an arithmetic or logic operation. see the ?instruction set summary? on page 423 for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruction set summary? on page 423 for detailed information. bit 76543210 i thsvnzcsreg read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 14 7593l?avr?09/12 at90usb64/128 ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithmetic or logic operation. see the ?instruction set summary? on page 423 for detailed information. 5.5 general purpose register file the register file is optimized for the avr enhan ced risc instruction set. in order to achie v e the required performance an d flexibility, the follo w ing input/output schemes are supported by the register file: ? one 8-bit output operand and one 8-bit result input ?t w o 8-bit output operands and one 8-bit result input ?t w o 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 5-2 sho w s the structure of the 32 general purpose w orking registers in the cpu. figure 5-2. avr cpu general purpose w orking registers. most of the instructions operating on the register file ha v e direct access to all registers, and most of them are single cycle instructions. as sho w n in figure 5-2 , each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user data space. although not being physically imple- mented as sram locations, this memory organization pro v ides great flexibility in access of the registers, as the x-, y-, and z-pointer registers can be set to index any register in the file. 5.5.1 the x-register, y-register, and z-register the registers r26..r31 ha v e some added functions to their general purpose usage. these reg- isters are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 5-3 . 70addr. r0 0x00 r1 0x01 r2 0x02 ? r13 0x0d general r14 0x0e purpose r15 0x0f w orking r16 0x10 registers r17 0x11 ? r26 0x1a x-register lo w byte r27 0x1b x-register high byte r28 0x1c y-register lo w byte r29 0x1d y-register high byte r30 0x1e z-register lo w byte r31 0x1f z-register high byte 15 7593l?avr?09/12 at90usb64/128 figure 5-3. the x-, y-, and z-registers. in the different addressing modes these address registers ha v e functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.6 stack pointer the stack is mainly used for storing temporary data, for storing local v ariables and for storing return addresses after interrupts and subroutine calls. the stack pointer register al w ays points to the top of the stack. note that the stack is implemented as gro w ing from higher memory loca- tions to lo w er memory locations. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack area w here the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point abo v e 0x0100. the initial v alue of the stack pointer is the last address of the internal sram. the stack pointer is decremented by one w hen data is pushed onto the stack w ith the push instruction, and it is decremented by three w hen the return address is pushed onto the stack w ith subroutine call or interrupt. the stack pointer is incremented by one w hen data is popped from the stack w ith the pop instruction, and it is incremented by three w hen data is popped from the stack w ith return from subroutine ret or return from interrupt reti. the avr stack pointer is implemented as t w o 8-bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in some implementa- tions of the avr architecture is so small that only spl is needed. in this case, the sph register w ill not be present. 15 xh xl 0 x-register 707 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 707 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7070 r31 (0x1f) r30 (0x1e) bit 1514131211109 8 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00100000 11111111 16 7593l?avr?09/12 at90usb64/128 5.6.1 rampz - extended z-poin ter register for elpm/spm for elpm/spm instructions, the z-pointer is a concatenation of rampz, zh, and zl, as sho w n in figure 5-4. note that lpm is not affected by the rampz setting. figure 5-4. the z-pointer used by elpm and spm. the actual number of bits is implementation dependent. unused bits in an implementation w ill al w ays read as zero. for compatibility w ith future de v ices, be sure to w rite these bits to zero. 5.7 instruction execution timing this section describes the general access timi ng concepts for instruction execution. the avr cpu is dri v en by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clock di v ision is used. figure 5-5 sho w s the parallel instruction fetches and instruction executions enabled by the har- v ard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz w ith the corresponding unique results for functions per cost, functions per clocks, and functions per po w er-unit. figure 5-5. the parallel instruction fetches and instruction executions. figure 5-6 sho w s the internal timing concept for the register file. in a single clock cycle an alu operation using t w o register operands is executed, and t he result is stored back to the destina- tion register. bit 7654321 0 rampz7 rampz6 rampz5 rampz4 rampz3 rampz2 rampz1 rampz0 rampz read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue0000000 0 bit (indi v idually) 7 0 7 0 7 0 rampz zh zl bit (z-pointer) 23 16 15 8 7 0 clk 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 cpu 17 7593l?avr?09/12 at90usb64/128 figure 5-6. single cycle alu operation. 5.8 reset and inte rrupt handling the avr pro v ides se v eral different interrupt sources. these interrupts and the separate reset vector each ha v e a separate program v ector in the program memory space. all interrupts are assigned indi v idual enable bits w hich must be w ritten logic one together w ith the global interrupt enable bit in the status register in orde r to enable the interrupt. depending on the program counter v alue, interrupts may be automatically disabled w hen boot lock bits blb02 or blb12 are programmed. this feature impro v es soft w are security. see the section ?memory program- ming? on page 359 for details. the lo w est addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of v ectors is sho w n in ?interrupts? on page 68 . the list also determines the priority le v els of the different interrupts. the lo w er the address the higher is the priority le v el. reset has the highest priority, and next is int0 ? the external interrupt request 0. the interrupt vectors can be mo v ed to the start of the boot flash section by setting the ivsel bit in the mcu control r egister (mcucr). refer to ?interrupts? on page 68 for more information. the reset vector can also be mo v ed to the start of the boot flash section by programming the bootrst fuse, see ?memory programming? on page 359 . when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user soft w are can w rite logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set w hen a return from interrupt instruction ? reti ? is executed. there are basically t w o types of interrupts. the first type is triggered by an e v ent that sets the interrupt flag. for these interrupts, the program counter is v ectored to the actual interrupt vec- tor in order to execute the interrupt handling routine, and hard w are clears the corresponding interrupt flag. interrupt flags can also be cleared by w riting a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs w hile the corresponding interrupt enable bit is cleared, the interrupt flag w ill be set and remembered until the in terrupt is enabled, or the flag is cleared by soft w are. similarly, if one or more interrupt conditions occur w hile the global interrupt enable bit is cleared, the corresponding interrupt flag(s) w ill be set and remembered until the global interrupt enable bit is set, and w ill then be executed by order of priority. the second type of interrupts w ill trigger as long as the interrupt condition is present. these interrupts do not necessarily ha v e interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the interrupt w ill not be triggered. when the avr exits from an interrupt, it w ill al w ays return to the main program and execute one more instruction before an y pending interrupt is ser v ed. total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 18 7593l?avr?09/12 at90usb64/128 note that the status register is not automatically stored w hen entering an interrupt routine, nor restored w hen returning from an interrupt routine. this must be handled by soft w are. when using the cli instruction to disable interrupts, the interrupts w ill be immediately disabled. no interrupt w ill be executed after the cli instruction, e v en if it occurs simultaneously w ith the cli instruction. the follo w ing example sho w s ho w this can be used to a v oid interrupts during the timed eeprom w rite sequence. when using the sei instruction to enable interrupts, the instruction follo w ing sei w ill be exe- cuted before any pending interrupts, as sho w n in this example. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ __disable_interrupt(); eecr |= (1< 20 7593l?avr?09/12 at90usb64/128 6. atmel avr at90usb64/128 memories this section describes the different memories in the at90usb64/128. the avr architecture has t w o main memory spaces, the data memory and the program memory space. in addition, the at90usb64/128 features an eeprom memory for data storage. all three memory spaces are linear and regular. notes: 1. byte address. 2. word (16-bit) address. 6.1 in-system re-programmabl e flash program memory the at90usb64/128 contains 128kbytes on-c hip in-system re-programmable flash memory for program storage. since all avr instructions are 16 or 32 bits w ide, the flash is organized as 64k 16. for soft w are security, the flash program memory space is di v ided into t w o sections, boot program section and application program section. the flash memory has an endurance of at least 100,000 w rite/erase cycles. the at90usb64/128 program counter (pc) is 16 bits w ide, thus addressing the 128k program memory locations. the operation of boot program section and associated boot lock bits for table 6-1. memory mapping. memory mnemonic at90usb64 at90usb128 flash size flash size 64kbytes 128k bytes start address - 0x00000 end address flash end 0x0ffff (1) 0x7fff (2) 0x1ffff (1) 0xffff (2) 32 registers size - 32bytes start address - 0x0000 end address - 0x001f i/o registers size - 64 bytes start address - 0x0020 end address - 0x005f ext i/o registers size - 160bytes start address - 0x0060 end address - 0x00ff internal sram size isram size 4kbytes 8kbytes start address isram start 0x0100 end address isram end 0x10ff 0x20ff external memory size xmem size 0-64kbytes start address xmem start 0x1100 0x2100 end address xmem end 0xffff eeprom size e2 size 2kbytes 4kbytes start address - 0x0000 end address e2 end 0x07ff 0x0fff 21 7593l?avr?09/12 at90usb64/128 soft w are protection are described in detail in ?memory programming? on page 359 . ?memory pro- gramming? on page 359 contains a detailed description on flash data serial do w nloading using the spi pins or the jtag interface. constant tables can be allocated w ithin the entire program memory address space (see the lpm ? load program memory instruction description and elpm - extended load program memory instruction description). timing diagrams for instruction fetch and execution are presented in ?instruction execution tim- ing? on page 16 . figure 6-1. program memory map. 6.2 sram data memory figure 6-2 sho w s ho w the atmel at90usb64/128 sram memory is organized. the at90usb64/128 is a complex microcontroller w ith more peripheral units than can be sup- ported w ithin the 64 location reser v ed in the opcode for the in and out instructions. for the extended i/o space from $060 - $0ff in sram, only the st/sts/std and ld/lds/ldd instruc- tions can be used. the first 4,352/8,448 data memory locations address both the register file, the i/o memory, extended i/o memory, and the internal data sr am. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory and the next 4,096/8,192 locations address the internal data sram. 0x00000 progr a m memory applic a tion fl as h s ection boot fl as h s ection fl as h end 22 7593l?avr?09/12 at90usb64/128 an optional external data sram can be used w ith the atmel at90usb64/128. this sram w ill occupy an area in the remaining address locations in the 64k address space. this area starts at the address follo w ing the internal sram. the register file, i/o, extended i/o and internal sram occupies the lo w est 4,352/8,448 bytes, so w hen using 64kb (65,536 bytes) of external memory, 61,184/57,088 bytes of external memory are a v ailable. see ?external memory interface? on page 31 for details on ho w to take ad v antage of the external memory map. when the addresses accessing the sram memory space exceeds the internal data memory locations, the external data sram is accessed using the same instructions as for the internal data memory access. when the internal data memories are accessed, the read and w rite strobe pins (pe0 and pe1 ) are inacti v e during the w hole access cycle. external sram operation is enabled by setting the sre bit in the xmcra register. accessing external sram takes one additional clock cycle per byte compared to access of the internal sram. this means that the commands ld, st, lds, sts, ldd, std, push, and pop take one additional clock cycle. if the stack is placed in external sram, interrupts, subroutine calls and returns take three clock cycles extra because the three-byte program counter is pushed and popped, and external memory access does not take ad v antage of the internal pipe- line memory access. when external sram interface is used w ith w ait-state, one-byte external access takes t w o, three, or four additio nal clock cycles for one, t w o, and three w ait-states respecti v ely. interrupts, subroutine calls and returns w ill need fi v e, se v en, or nine clock cycles more than specified in the instruction set manual for one, t w o, and three w ait-states. the fi v e different addressing modes for the data memory co v er: direct, indirect w ith displace- ment, indirect, indirect w ith pre-decrement, and indirect w ith post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect w ith displacement mode reaches 63 address locations from the base address gi v en by the y- or z-register. when using register indirect addressing modes w ith automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented or incremented. the 32 general purpose w orking registers, 64 i/o registers, and the 8,192 bytes of internal data sram in the at90usb64/128 are all accessible through all these addressing modes. the reg- ister file is described in ?general purpose register file? on page 14 . 23 7593l?avr?09/12 at90usb64/128 figure 6-2. data memory map. 6.2.1 data memory access times this section describes the general access timi ng concepts for internal memory access. the internal data sram access is performed in t w o clk cpu cycles as described in figure 6-3 . 3 2 regi s ter s 64 i/o regi s ter s intern a l sram (8192 x 8) $0000 - $001f $0020 - $005f $ffff $0060 - $00ff data memory extern a l sram (0 - 64k x 8) 160 ext i/o reg. xmem start isram end isram start 24 7593l?avr?09/12 at90usb64/128 figure 6-3. on-chip data sram access cycles. 6.3 eeprom data memory the atmel at90usb64/128 contai ns 2k/4k bytes of data eeprom memory. it is organized as a separate data space, in w hich single bytes can be read and w ritten. the eeprom has an endurance of at least 100,000 w rite/erase cycles. the access bet w een the eeprom and the cpu is described in the follo w ing, specifying the eeprom ad dress registers, the eeprom data register, and the eeprom control register. for a detailed description of spi, jtag and parallel data do w nloading to the eeprom, see page 373 , page 377 , and page 362 respecti v ely. 6.3.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the w rite access time for the eeprom is gi v en in table 6-3 . a self-timing function, ho w e v er, lets the user soft w are detect w hen the next byte can be w ritten. if the user code contains instruc- tions that w rite the eeprom, some precautions must be taken. in hea v ily filtered po w er supplies, v cc is likely to rise or fall slo w ly on po w er-up/do w n. this causes the de v ice for some period of time to run at a v oltage lo w er than specified as minimum for the clock frequency used. see ?pre v enting eeprom corr uption? on page 29. for details on ho w to a v oid problems in these situations. in order to pre v ent unintentional eeprom w rites, a specific w rite procedure must be follo w ed. refer to the description of the eeprom control regist er for details on this. when the eeprom is read, the cpu is halted for fo ur clock cycles before the next in struction is executed. when the eeprom is w ritten, the cpu is halted for t w o clock cycles before the next instruction is executed. clk wr rd data data address address valid t1 t2 t3 compute address read write cpu memory access instruction next instruction 25 7593l?avr?09/12 at90usb64/128 6.3.2 eearh and eearl ? the eeprom address register ? bits 15..12 ? res: reserved bits these bits are reser v ed bits in the atmel at90usb64/128 and w ill al w ays read as zero. ? bits 11..0 ? eear8..0: eeprom address the eeprom address r egisters ? eearh and eearl specify the eeprom address in the 4k bytes eeprom space. the eeprom data bytes are addressed linearly bet w een 0 and 4096. the initial v alue of eear is undefined. a proper v alue must be w ritten before the eeprom may be accessed. 6.3.3 eedr ? the eeprom data register ? bits 7..0 ? eedr7.0: eeprom data for the eeprom w rite operation, the eedr register contains the data to be w ritten to the eeprom in the address gi v en by the eear register. for the eeprom read operation, the eedr contains the data read out from the eeprom at the address gi v en by eear. 6.3.4 eecr ? the eeprom control register ? bits 7..6 ? res: reserved bits these bits are reser v ed bits in the at90usb64/128 and w ill al w ays read as zero. ? bits 5, 4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming mode bit setting defines w hich programming action that w ill be trig- gered w hen w riting eepe. it is possible to program data in one atomic operation (erase the old v alue and program the ne w v alue) or to split the erase and write operations in t w o different operations. the programming times for the different modes are sho w n in table 6-2 on page 26 . while eepe is set, any w rite to eepmn w ill be ignored. during reset, the eepmn bits w ill be reset to 0b00 unless the eeprom is busy programming. bit 1514131211 10 9 8 ????eear11eear10eear9eear8eearh eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 76543 2 10 read/ w riterrrrr/wr/wr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w initial v alue0000x x xx xxxxx x xx bit 76543210 msb lsb eedr read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 765432 10 ? ? eepm1 eepm0 eerie eempe eepe eere eecr read/ w rite r r r/w r/w r/w r/w r/w r/w initial v alue 0 0 x x 0 0 x 0 26 7593l?avr?09/12 at90usb64/128 ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writing eerie to zero disables the interrupt. the eeprom ready interrupt generates a constant inter- rupt w hen eepe is cleared. ? bit 2 ? eempe: eeprom master programming enable the eempe bit determines w hether setting eepe to one causes the eeprom to be w ritten. when eempe is set, setting eepe w ithin four clock cycles w ill w rite data to the eeprom at the selected address if eem pe is zero, setting eepe w ill ha v e no effect. when eempe has been w ritten to one by soft w are, hard w are clears the bit to zero a fter four clock cycles. see the description of the eepe bit for an eeprom w rite procedure. ? bit 1 ? eepe: eeprom programming enable the eeprom write enable signal eepe is the w rite strobe to the eeprom. when address and data are correctly set up, the eepe bit must be w ritten to one to w rite the v alue into the eeprom. the eempe bit must be w ritten to one before a logical one is w ritten to eepe, other- w ise no eeprom w rite takes place. the follo w ing procedure should be follo w ed w hen w riting the eeprom (the order of steps 3 and 4 is not essential): 1. wait until eepe becomes zero. 2. wait until selfprgen in spmcsr becomes zero. 3. write ne w eeprom address to eear (optional). 4. write ne w eeprom data to eedr (optional). 5. write a logical one to the eempe bit w hile w riting a zero to eepe in eecr. 6. within four clock cycles after setting eempe, w rite a logical one to eepe. the eeprom can not be programmed during a cpu w rite to the flash memory. the soft w are must check that the flash programming is completed before initiating a ne w eeprom w rite. step 2 is only rele v ant if the soft w are contains a boot loader allo w ing the cpu to program the flash. if the flash is ne v er being updated by the cpu, step 2 can be omitted. see ?memory pro- gramming? on page 359 for details about boot programming. caution: an interrupt bet w een step 5 and step 6 w ill make the w rite cycle fail, since the eeprom master write enable w ill time-out. if an interrupt routine accessing the eeprom is interrupting another eeprom access , the eear or eedr register w ill be modified, causing the interrupted eeprom access to fa il. it is recommended to ha v e the global interrupt flag cleared during all the steps to a v oid these problems. table 6-2. eeprom mode bits. eepm1 eepm0 programming time operation 0 0 3.4ms erase and write in one operation (atomic operation) 0 1 1.8ms erase only 1 0 1.8ms write only 11 ? reser v ed for future use 27 7593l?avr?09/12 at90usb64/128 when the w rite access time has elapsed, the eepe bit is cleared by hard w are. the user soft- w are can poll this bit and w ait for a zero before w riting the next byte. when eepe has been set, the cpu is halted for t w o cycles before the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the re ad strobe to the eeprom. when the correct address is set up in the eear register, the eere bit must be w ritten to a logic one to trigger the eeprom read. the eeprom read access takes one instruction, and th e requested data is a v ailable immediately. when the eeprom is read, the cpu is ha lted for four cycles before the next instruction is executed. the user should poll the eepe bit before starting the read operation. if a w rite operation is in progress, it is neither possi ble to read the eeprom, nor to change the eear register. the calibrated oscillator is used to time the eeprom accesses. table 6-3 lists the typical pro- gramming time for eeprom access from the cpu. the follo w ing code examples sho w one assembly and one c function for w riting to the eeprom. the examples assume that interrupts are controlled (for example by disabling inter- rupts globally) so that no interrupts w ill occur during execution of these functions . the examples also assume that no flash boot loader is present in the soft w are. if such code is present, the eeprom w rite function must also w ait for any ongoing spm command to finish. table 6-3. eeprom programming time. symbol number of calibrat ed rc oscillator cycles typical programming time eeprom w rite (from cpu) 26,368 3.3ms 28 7593l?avr?09/12 at90usb64/128 note: 1. see ?about code examples? on page 10. assembly code example (1) eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eempe sbi eecr,eempe ; start eeprom write by setting eepe sbi eecr,eepe ret c code example (1) void eeprom_write( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 31 7593l?avr?09/12 at90usb64/128 6.5 external memory interface with all the features the external memory interface pro v ides, it is w ell suited to operate as an interface to memory de v ices such as external sram and flash, and peripherals such as lcd- display, a/d, and d/a. the main features are: ? four different wait-s tate settings (includi ng no wait-state) ? independent wait-state setting for different exte rnal memory sectors (configurable sector size) ? the number of bits dedicated to address high byte is selectable ? bus keepers on data lines to minimi ze current consumption (optional) 6.5.1 overview when the external memory (xmem) is enabl ed, address space outside the internal sram becomes a v ailable using the dedicated external memory pins (see figure 2-1 on page 6 , table 11-3 on page 78 , and table 11-9 on page 82 ). the memory configuration is sho w n in figure 6-4 . figure 6-4. external memory w ith sector select. 6.5.2 using the external memory interface the interface consists of: ? ad7:0: multiplexed lo w -order address bus and data bus ? a15:8: high-order address bus (configurable number of bits) ? ale: address latch enable ?rd : read strobe ?wr : write strobe the control bits for the external memory interface are located in t w o registers, the external memory control register a ? xmcra, and the external memory control register b ? xmcrb. memory confi g uration a 0x0000 extern a l memory (0-60k x 8) 0xffff intern a l memory srl[2..0] srw11 srw10 srw01 srw00 lower s ector upper s ector isram end xmem start 32 7593l?avr?09/12 at90usb64/128 when the xmem interface is enabled, the xmem interface w ill o v erride the setting in the data direction registers that corresponds to the ports dedicated to the xmem interface. for details about the port o v erride, see the alternate functions in section ?i/o-ports? on page 71 . the xmem interface w ill auto-detect w hether an access is internal or external. if the access is external, the xmem interface w ill output address, data, and the contro l signals on the ports according to fig- ure 6-6 on page 33 (this figure sho w s the w a v e forms w ithout w ait-states). when ale goes from high-to-lo w , there is a v alid address on ad7:0. ale is lo w during a data transfer. when the xmem interface is enabled, also an internal access w ill cause acti v ity on address, data and ale ports, but the rd and wr strobes w ill not toggle during internal access. when the external memory interface is disabled, the normal pin and data direction settings are used. note that w hen the xmem interface is disabled, the address space abo v e the internal sram boundary is not mapped into the internal sram. figure 6-5 illustrates ho w to connect an external sram to the avr using an octal latch (typically ?74 573? or equi v alent) w hich is transparent w hen g is high. 6.5.3 address latch requirements due to the high-speed operation of the xram interface, the address latch must be selected w ith care for system frequencies abo v e 8mhz @ 4v and 4mhz @ 2.7v. when operating at condi- tions abo v e these frequencies, the typical old style 74hc series latch becomes inadequate. the external memory interface is designed in compliance to the 74ahc series latch. ho w e v er, most latches can be used as long they comply w ith the main timing parameters. the main parameters for the address latch are: ? d to q propagation delay (t pd ) ? data setup time before g lo w (t su ) ? data (address) hold time after g lo w ( th ) the external memory interface is designed to guaranty minimum address hold time after g is asserted lo w of t h = 5ns. refer to t laxx_ld /t llaxx_st in ?external data memory timing? tables 31-7 through tables 31-13 on pages 399 - 401 . the d-to-q propagation delay (t pd ) must be taken into consideration w hen calculating the access time requirement of the external component. the data setup time before g lo w (t su ) must not exceed address v alid to ale lo w (t avllc ) minus pcb w iring delay (dependent on the capaciti v e load). figure 6-5. external sram connected to the avr. d[7:0] a[7:0] a[15:8] rd wr sram dq g ad7:0 ale a15:8 rd wr avr 33 7593l?avr?09/12 at90usb64/128 6.5.4 pull-up and bus-keeper the pull-ups on the ad7:0 ports may be acti v ated if the corresponding port register is w ritten to one. to reduce po w er consumption in sleep mode, it is recommended to disable the pull-ups by w riting the port register to zero before entering sleep. the xmem interface also pro v ides a bus-keeper on the ad7:0 lines. the bus-keeper can be dis- abled and enabled in soft w are as described in ?xmcrb ? external memo ry control register b? on page 36 . when enabled, the bus-keeper w ill keep the pre v ious v alue on the ad7:0 bus w hile these lines are tri-stated by the xmem interface. 6.5.5 timing external memory de v ices ha v e different timing requirements. to meet these requirements, the xmem interface pro v ides four different w ait-states as sho w n in table 6-5 on page 36 . it is impor- tant to consider the timing specification of the external memory de v ice before selecting the w ait- state. the most important parameters are the access time for the external memory compared to the setup requirement. the access time for the ex ternal memory is defined to be the time from recei v ing the chip select/address until the da ta of this address actually is dri v en on the bus. the access time cannot exceed the time from the ale pulse must be asserted lo w until data is stable during a read sequence (see t llrl + t rlrh - t dvrh in tables 31-6 through tables 31-13 on pages 399 - 401 ). the different w ait-states are set up in soft w are. as an additional feature, it is possible to di v ide the external memory space in t w o sectors w ith indi v idual w ait-state settings. this makes it possible to connect t w o different memory de v ices w ith different timing requirements to the same xmem interface. for xmem interface timing details, please refer to tables 31-6 through tables 31-13 and figure 31-7 to figure 31-10 in the ?external data memory timing? on page 399 . note that the xmem interface is asynchronous and that the w a v eforms in the follo w ing figures are related to the internal system clock. the ske w bet w een the internal and external clock (xtal1) is not guarantied ( v aries bet w een de v ices temperature, and supply v oltage). conse- quently, the xmem interface is not suited for synchronous operation. figure 6-6. external data memory cycles w ithout w ait-state (srwn1=0 and srwn0=0). ale t1 t2 t 3 write re a d wr t4 a15:8 addre ss prev. a ddr. da7:0 addre ss d a t a prev. d a t a xx rd da7:0 (xmbk = 0) d a t a prev. d a t a addre ss d a t a prev. d a t a addre ss da7:0 (xmbk = 1) sy s tem clock (clk cpu ) 34 7593l?avr?09/12 at90usb64/128 note: 1. srwn1 = srw11 (upper sector) or srw01 (lo w er sector), srwn0 = srw10 (upper sector) or srw00 (lo w er sector). the ale pulse in period t4 is only present if the next instruction accesses the ram (internal or external). figure 6-7. external data memory cycles w ith srwn1 = 0 and srwn0 = 1 (1) . note: 1. srwn1 = srw11 (upper sector) or srw01 (lo w er sector), srwn0 = srw10 (upper sector) or srw00 (lo w er sector). the ale pulse in period t5 is only present if the next instruction accesses the ram (internal or external). figure 6-8. external data memory cycles w ith srwn1 = 1 and srwn0 = 0 (1) . note: 1. srwn1 = srw11 (upper sector) or srw01 (lo w er sector), srwn0 = srw10 (upper sector) or srw00 (lo w er sector). the ale pulse in period t6 is only present if the next instruction accesses the ram (internal or external). ale t1 t2 t 3 write re a d wr t5 a15:8 addre ss prev. a ddr. da7:0 addre ss d a t a prev. d a t a xx rd da7:0 (xmbk = 0) d a t a prev. d a t a addre ss d a t a prev. d a t a addre ss da7:0 (xmbk = 1) sy s tem clock (clk cpu ) t4 ale t1 t2 t 3 write re a d wr t6 a15:8 addre ss prev. a ddr. da7:0 addre ss d a t a prev. d a t a xx rd da7:0 (xmbk = 0) d a t a prev. d a t a addre ss d a t a prev. d a t a addre ss da7:0 (xmbk = 1) sy s tem clock (clk cpu ) t4 t5 35 7593l?avr?09/12 at90usb64/128 figure 6-9. external data memory cycles w ith srwn1 = 1 and srwn0 = 1 (1) . note: 1. srwn1 = srw11 (upper sector) or srw01 (lo w er sector), srwn0 = srw10 (upper sector) or srw00 (lo w er sector). the ale pulse in period t7 is only present if the next instruction accesses the ram (internal or external). 6.5.6 xmcra ? external memory control register a ? bit 7 ? sre: external sram/xmem enable writing sre to one enables the external memory interface.the pin functions ad7:0, a15:8, ale, wr , and rd are acti v ated as the alternate pin functions. the sre bit o v errides any pin direction settings in the respecti v e data direction registers. writ ing sre to zero, disables the external memory interface and the normal pin and data direction settings are used. ? bit 6..4 ? srl2:0: wait-state sector limit it is possible to configure different w ait-states for different external memory addresses. the external memory address space can be di v ided in t w o sectors that ha v e separate w ait-state bits. the srl2, srl1, and srl0 bits select the split of the sectors, see table 6-4 on page 36 and figure 6-4 on page 31 . by default, the srl2, srl1, and srl0 bits are set to zero and the entire external memory address space is treated as one sector. when the entire sram address space is configured as one sector, the w ait-states are configured by the srw11 and srw10 bits. ale t1 t2 t 3 write re a d wr t7 a15:8 addre ss prev. a ddr. da7:0 addre ss d a t a prev. d a t a xx rd da7:0 (xmbk = 0) d a t a prev. d a t a addre ss d a t a prev. d a t a addre ss da7:0 (xmbk = 1) sy s tem clock (clk cpu ) t4 t5 t6 bit 76543210 sre srl2 srl1 srl0 srw11 srw10 srw01 srw00 xmcra read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 36 7593l?avr?09/12 at90usb64/128 ? bit 3..2 ? srw11, srw10: wait-state select bits for upper sector the srw11 and srw10 bits control the number of w ait-states for the upper sector of the exter- nal memory address space, see table 6-5 . ? bit 1..0 ? srw01, srw00: wait-state select bits for lower sector the srw01 and srw00 bits control the number of w ait-states for the lo w er sector of the exter- nal memory address space, see table 6-5 . note: 1. n = 0 or 1 (lo w er/upper sector). for further details of the timing and w ait-states of the external memory interface, see figures 6-6 through figures 6-9 on page 33 to page 35 for ho w the setting of the srw bits affects the timing. 6.5.7 xmcrb ? external memory control register b ? bit 7? xmbk: external memory bus-keeper enable writing xmbk to one enables the bus keeper on the ad7:0 lines. when the bus keeper is enabled, ad7:0 w ill keep the last dri v en v alue on the lines e v en if the xmem interface has tri- table 6-4. sector limits w ith different settings of srl2..0. srl2 srl1 srl0 sector limits 00x lo w er sector = n/a upper sector = 0x2100 - 0xffff 010 lo w er sector = 0x2100 - 0x3fff upper sector = 0x4000 - 0xffff 011 lo w er sector = 0x2100 - 0x5fff upper sector = 0x6000 - 0xffff 100 lo w er sector = 0x2100 - 0x7fff upper sector = 0x8000 - 0xffff 101 lo w er sector = 0x2100 - 0x9fff upper sector = 0xa000 - 0xffff 110 lo w er sector = 0x2100 - 0xbfff upper sector = 0xc000 - 0xffff 111 lo w er sector = 0x2100 - 0xdfff upper sector = 0xe000 - 0xffff table 6-5. wait states (1) . srwn1 srwn0 wait states 00no w ait-states 0 1 wait one cycle during read/ w rite strobe 10wait t w o cycles during read/ w rite strobe 11 wait t w o cycles during read/ w rite and w ait one cycle before dri v ing out ne w address bit 7654 3 210 xmbk ? ? ? ? xmm2 xmm1 xmm0 xmcrb read/ w rite r/w r r r r r/w r/w r/w initial v alue0000 0 000 37 7593l?avr?09/12 at90usb64/128 stated the lines. writing xmbk to zero disables the bus keeper. xmbk is not qualified w ith sre, so e v en if the xmem interface is dis abled, the bus keepers are still acti v ated as long as xmbk is one. ? bit 6..3 ? res: reserved bits these bits are reser v ed and w ill al w ays read as zero. when w riting to this address location, w rite these bits to zero for compatibility w ith future de v ices. ? bit 2..0 ? xmm2, xmm1, xmm0: external memory high mask when the external memory is enabled, all port c pins are default used for the high address byte. if the full 60kb address space is not required to access the external memory, some, or all, port c pins can be released for normal port pin function as described in table 6-6 . as described in ?using all 64kb locations of external memory? on page 38 , it is possible to use the xmmn bits to access all 64kb locations of the external memory. 6.5.8 using all locations of external memory smaller than 64kb since the external memory is mapped after the internal memory as sho w n in figure 6-4 on page 31 , the external memory is not addressed w hen addressing the first 8,448/4,352 bytes (128/64kbytes v ersion) of data space. it may appear that the first 8,448/4,352 bytes of the exter- nal memory are inaccessible (external memory addresses 0x0000 to 0x10ff or 0x0000 to 0x20ff). ho w e v er, w hen connecting an external memory smaller than 64kb, for example 32kb, these locations are easily accessed simply by addressing from address 0x8000 to 0xa1ff. since the external memory address bit a15 is not connected to the external memory, addresses 0x8000 to 0xa1ff w ill appear as addresses 0x0000 to 0x21ff for the external memory. addressing abo v e address 0xa1ff is not recommended, since this w ill address an external memory location that is already accessed by another (lo w er) address. to the application soft- w are, the external 32kb memory w ill appear as one linear 32kb ad dress space from 0x2200 to 0xa1ff. this is illustrated in figure 6-10 on page 38 . table 6-6. port c pins released as normal port pins w hen the external memory is enabled. xmm2 xmm1 xmm0 # bits for external memory address released port pins 0 0 0 8 (full 56kb space) none 0017 pc7 0106 pc7 - pc6 0115 pc7 - pc5 1004 pc7 - pc4 1013 pc7 - pc3 1102 pc7 - pc2 1 1 1 no address high bits full port c 38 7593l?avr?09/12 at90usb64/128 figure 6-10. address map w ith 32kb external memory. 6.5.9 using all 64kb locations of external memory since the external memory is mapped after the internal memory as sho w n in figure 6-4 , only 56kb of external memory is a v ailable by default (address s pace 0x0000 to 0x20ff is reser v ed for internal memory). ho w e v er, it is possible to take ad v antage of the entire external memory by masking the higher address bits to zero. this can be done by using the xmmn bits and control by soft w are the most significant bits of the address. by setting port c to output 0x00, and releas- ing the most significant bits for normal port pin operation, the memory interface w ill address 0x0000 - 0x2fff. see the follo w ing code examples. care must be exercised using this option as most of the memory is masked a w ay. 0x0000 0x20ff 0xffff 0x2100 0x7fff 0x8000 0x0000 0x7fff memory config u r a tion a intern a l memory (un us ed) avr memory m a p extern a l 3 2k sram extern a l memory xmem start + 0x8000 isram end + 0x8000 xmem start isram end 39 7593l?avr?09/12 at90usb64/128 note: 1. see ?about code examples? on page 10. assembly code example (1) ; offset is defined to 0x4000 to ensure ; external memory access ; configure port c (address high byte) to ; output 0x00 when the pins are released ; for normal port pin operation ldi r16, 0xff out ddrc, r16 ldi r16, 0x00 out portc, r16 ; release pc7:6 ldi r16, (1< 41 7593l?avr?09/12 at90usb64/128 7.1.4 asynchronous timer clock ? clk asy the asynchronous timer clock allo w s the asynchronous timer/counter to be clocked directly from an external clock or an external 32khz clock crystal. the dedicated clock domain allo w s using this timer/counter as a real-time counter e v en w hen the de v ice is in sleep mode. 7.1.5 adc clock ? clk adc the adc is pro v ided w ith a dedicated clock domain. this allo w s halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gi v es more accurate adc con v ersion results. 7.1.6 usb clock ? clk usb the usb is pro v ided w ith a dedicated clock domain. this clock is generated w ith an on-chip pll running at 48mhz. the pll al w ays multiply its input frequency by 24. thus the pll clock regis- ter should be programmed by soft w are to generate a 2mhz clock on the pll input. 7.2 clock sources the de v ice has the follo w ing clock source options, selectable by flash fuse bits as sho w n belo w . the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed w hile ?0? means programmed. 7.2.1 default clock source the de v ice is shipped w ith lo w po w er crystal oscillator (8.0mhz-max) enabled and w ith the fuse ckdiv8 programmed, result ing in 1.0mhz system clock ( w ith a 8mhz crystal). the default fuse configuration is cksel = "1 110", sut = "01", ckdiv8 = "0". this default setting ensures that all users can make their desired clock source setting using any a v ailable programming interface. 7.2.2 clock startup sequence any clock source needs a sufficient v cc to start oscillating and a minimum number of oscillating cycles before it can be considered stable. to ensure sufficient v cc , the de v ice issues an internal reset w ith a time-out delay (t tout ) after the de v ice reset is released by all other reset sources. ?on-chip debug system? on page 56 describes the start conditions for the internal reset. the delay (t tout ) is timed from the watchdog oscillator and the number of cycles in the delay is set by the sutx and ckselx fuse bits. the selectable delays are sho w n in table 7-2 . the frequency of the watchdog oscillator is v oltage table 7-1. de v ice clocking options select (1) . device clocking option cksel3..0 lo w po w er crystal oscillator 1111 - 1000 reser v ed 0111 - 0110 lo w frequency crystal oscillator 0101 - 0100 reser v ed 0011 calibrated internal rc oscillator 0010 external clock 0000 reser v ed 0001 42 7593l?avr?09/12 at90usb64/128 dependent as sho w n in ?atmel at90usb64/128 typical characteristics? on page 404 . main purpose of the delay is to keep the avr in reset until it is supplied w ith minimum v cc . the delay w ill not monitor the actual v oltage and it w ill be required to select a delay longer than the v cc rise time. if this is not possible, an internal or external bro w n-out detection circuit should be used. a bod circuit w ill ensure sufficient v cc before it releases the reset, and the time-out delay can be disabled. disabling the time-out delay w ithout utilizing a bro w n-out detection circuit is not recommended. the oscillator is required to oscillate for a minimu m number of cycles befo re the clock is consid- ered stable. an inte rnal ripple counter monito rs the oscillator output cl ock, and keep s the internal reset acti v e for a gi v en number of clock cycles. the reset is then released and the de v ice w ill start to execute. the recommend ed oscillator start-up time is dependent on the clock type, and v aries from 6 cycles for an externally applied clock to 32k cycles for a lo w frequency crystal. the start-up sequence for the clock includes both the time-out delay and the start-up time w hen the de v ice starts up from reset. when starting up from po w er-sa v e or po w er-do w n mode, v cc is assumed to be at a sufficient le v el and only the start-up time is included. 7.3 low power crystal oscillator pins xtal1 and xtal2 are input and output, respecti v ely, of an in v erting amplifier w hich can be configured for use as an on-chip oscillator, as sho w n in figure 7-2 on page 43 . either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a lo w po w er oscillator, w ith reduced v oltage s w ing on the xtal2 out- put. it gi v es the lo w est po w er consumption, but is not capable of dri v ing other clock inputs, and may be more susceptible to noise in noisy en v ironments. in these cases, refer to the ?these options are intended for use w ith ceramic resonators and w ill ensure frequency stability at start- up. they can also be used w ith crystals w hen not operating close to the maximum frequency of the de v ice, and if frequency stability at start-up is not important for the ap plication.? on page 44 . c1 and c2 should al w ays be equal for both crystals and resonators. the optimal v alue of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the en v ironment. some initial guidelines for choosing capacitors for use w ith crystals are gi v en in table 7-3 on page 43 . for ceramic resonators, the capacitor v al- ues gi v en by the manufacturer should be used. table 7-2. number of w atchdog oscillator cycles. typical time-out (v cc = 5.0v) typical time-out (v cc = 3.0v) number of cycles 0ms 0ms 0 4.1ms 4.3ms 512 65ms 69ms 8k (8,192) 43 7593l?avr?09/12 at90usb64/128 figure 7-2. crystal oscillator connections. the lo w po w er oscillator can operate in three different modes, each opt imized for a specific fre- quency range. the operating mode is selected by the fuses cksel3..1 as sho w n in table 7-3 . notes: 1. the frequency ranges are preliminary v alues. actual v alues are tbd. 2. this option should not be used w ith crystals, only w ith ceramic resonators. 3. if 8mhz frequency exceeds the specification of the de v ice (depends on v cc ), the ckdiv8 fuse can be programmed in order to di v ide the internal frequency by 8. it must be ensured that the resulting di v ided clock meets the frequen cy specification of the de v ice. the cksel0 fuse together w ith the sut1..0 fuses select the start-up times as sho w n in table 7-4 . table 7-3. lo w po w er crystal oscillator operating modes (3) . frequency range (1) [mhz] cksel3..1 recommended range for capacitors c1 and c2 [pf] 0.4 - 0.9 100 (2) ? 0.9 - 3.0 101 12 - 22 3.0 - 8.0 110 12 - 22 8.0 - 16.0 111 12 - 22 table 7-4. start-up times for the lo w po w er crystal oscillator clock selection. oscillator source / power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 ceramic resonator, fast rising po w er 258ck 14ck + 4.1ms (1) 000 ceramic resonator, slo w ly rising po w er 258ck 14ck + 65ms (1) 001 ceramic resonator, bod enabled 1kck 14ck (2) 010 ceramic resonator, fast rising po w er 1kck 14ck + 4.1ms (2) 011 ceramic resonator, slo w ly rising po w er 1kck 14ck + 65ms (2) 100 xtal2 xtal1 gnd c2 c1 44 7593l?avr?09/12 at90usb64/128 notes: 1. these options should only be used w hen not operating close to the maximum frequency of the de v ice, and only if frequency stability at start- up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use w ith ceramic resonators and w ill ensure fre quency stability at start-up. they can also be used w ith crystals w hen not operating close to the maximum fre- quency of the de v ice, and if frequency stability at start- up is not important for the application. note: 1. the de v ice is shipped w ith this option selected. 7.4 low frequency crystal oscillator the de v ice can utilize a 32.768khz w atch crystal as clock so urce by a dedicated lo w frequency crystal oscillator. t he crystal should be connected as sho w n in figure 7-2 on page 43 . when this oscillator is selected , start-up times are det ermined by the sut fuses and cksel0 as sho w n in table 7-6 . crystal oscillator, bod enabled 16kck 14ck 1 01 crystal oscillator, fast rising po w er 16kck 14ck + 4.1ms 1 10 crystal oscillator, slo w ly rising po w er 16kck 14ck + 65ms 1 11 table 7-5. start-up times for the internal calib rated rc oscillator clock selection. power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6ck 14ck 00 fast rising po w er 6ck 14ck + 4.1ms 01 slo w ly rising po w er 6ck 14ck + 65ms (1) 10 reser v ed 11 table 7-4. start-up times for the lo w po w er crystal oscillator clo ck selection. (continued) oscillator source / power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 table 7-6. start-up times for the lo w frequency crystal osc illator clock selection. power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 bod enabled 1kck 14ck (1) 000 fast rising po w er 1kck 14ck + 4.1ms (1) 001 slo w ly rising po w er 1kck 14ck + 65ms (1) 010 reser v ed 0 11 bod enabled 32kck 14ck 1 00 fast rising po w er 32kck 14ck + 4.1ms 1 01 slo w ly rising po w er 32kck 14ck + 65ms 1 10 reser v ed 1 11 45 7593l?avr?09/12 at90usb64/128 note: 1. these options should only be used if frequen cy stability at start-up is not important for the application. 7.5 calibrated internal rc oscillator the calibrated inte rnal rc oscillator by default pro v ides a 8.0mhz clock. the frequency is nomi- nal v alue at 3v and 25 c. the de v ice is shipped w ith the ckdiv8 fuse programmed. see ?system clock prescaler? on page 47 for more details. this clock may be selected as the system clock by programming the cksel fuses as sho w n in table 7-7 . if selected, it w ill operate w ith no external components. during reset, hard w are loads the calibration byte into the osccal register and thereby automatically calib rates the rc oscillator. at 3v and 25 c, this calibration gi v es a frequency of 8mhz 10%. the oscillator c an be calibrated to any frequency in the range 7.3 - 8.1mhz w ithin 10% accuracy, by changing the osccal register. when this oscillator is used as the chip clock, the watchdog oscillator w ill still be used for the watchdog timer and for the reset time-out. for more information on the pre-programmed calibration v alue, see section ?calibration byte? on page 362 notes: 1. the de v ice is shipped w ith this option selected. 2. the frequency ranges are preliminary v alues. actual v alues are tbd. 3. if 8mhz frequency exceeds the specification of the de v ice (depends on v cc ), the ckdiv8 fuse can be programmed in order to di v ide the internal frequency by 8. when this oscillator is selected, start-up ti mes are determined by the sut fuses as sho w n in table 7-5 on page 44 . note: 1. the de v ice is shipped w ith this option selected. 7.5.1 osccal ? oscillato r calibration register ? bits 7..0 ? cal7..0: oscillator calibration value the oscillator calibration regist er is used to trim the calibrate d internal rc oscillator to remo v e process v ariations from the oscillator fr equency. the factory-calibrated v alue is automatically w ritten to this register during chip reset, gi v ing an oscillator frequency of 8.0mhz at 25c. the application soft w are can w rite this register to change the o scillator frequency. the oscillator can table 7-7. internal calibrated rc o scillator operating modes (1)(3) . frequency range (2) [mhz] cksel3..0 7.3 - 8.1 0010 table 7-8. start-up times for the internal calib rated rc oscillator clock selection. power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6ck 14ck 00 fast rising po w er 6ck 14ck + 4.1ms 01 slo w ly rising po w er 6ck 14ck + 65ms (1) 10 reser v ed 11 bit 76543210 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue de v ice specific calibration v alue 46 7593l?avr?09/12 at90usb64/128 be calibrated to any frequency in the range 7.3 - 8.1mhz w ithin 10% accuracy. calibration out- side that range is not guaranteed. note that this osc illator is used to time eeprom and flash w rite accesses, and these w rite times w ill be affected accordingly. if the eeprom or flash are w ritten, do not calibrate to more than 8.8mhz. other w ise, the eeprom or flash w rite may fail. the cal7 bit determines the range of operation for the oscillator. setting this bit to 0 gi v es the lo w est frequency range, setting this bit to 1 gi v es the highest frequency range. the t w o fre- quency ranges are o v erlapping, in other w ords a setting of osccal = 0x7f gi v es a higher frequency than osccal = 0x80. the cal6..0 bits are used to tune the frequency w ithin the selected range. a setting of 0x00 gi v es the lo w est frequency in that range, and a setting of 0x7f gi v es the highest frequency in the range. incrementing cal6..0 by 1 w ill gi v e a frequency increment of less than 2% in the fre- quency range 7.3 - 8.1mhz. 7.6 external clock the de v ice can utilize a external clock source as sho w n in figure 7-3 . to run the de v ice on an external clock, the cksel fuse s must be programmed as sho w n in table 7-1 on page 41 . figure 7-3. external clock dri v e configuration. when this clock source is selected, start-up times are determined by the sut fuses as sho w n in table 7-9 . when applying an external clock, it is required to a v oid sudden changes in the applied clock fre- quency to ensure stable operation of the mcu. a v ariation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable beha v ior. if changes of more than 2% is required, ensure that the mcu is kept in reset during the changes. table 7-9. start-up times for the external clock selection. power conditions start-up time from power- down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6ck 14ck 00 fast rising po w er 6ck 14ck + 4.1ms 01 slo w ly rising po w er 6ck 14ck + 65ms 10 reser v ed 11 nc external clock signal xtal2 xtal1 gnd 47 7593l?avr?09/12 at90usb64/128 note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency w hile still ensuring stable operation. refer to ?system clock prescaler? on page 47 for details. 7.7 clock output buffer the de v ice can output the system clock on the cl ko pin. to enable the output, the ckout fuse has to be programmed. this mode is suitable w hen the chip clock is used to dri v e other cir- cuits on the system. the clock also w ill be output during reset, and the normal operation of i/o pin w ill be o v erridden w hen the fuse is programmed. any clock source, including the internal rc oscillator, can be selected w hen the clock is output on clko. if the system clock prescaler is used, it is the di v ided system clock that is output. 7.8 timer/counter oscillator the de v ice can operate its timer/counter2 from an external 32.768khz w atch crystal or a exter- nal clock source. see figure 7-2 on page 43 for crystal connection. applying an external clock source to tosc 1 requires exclk in the assr register w ritten to logic one. see ?asynchronous operation of the timer/counter? on page 161 for further descrip- tion on selecting external clock as input instead of a 32khz crystal. 7.9 system clock prescaler the atmel at90usb64/128 has a system clock prescaler, and the syst em clock can be di v ided by setting the ?clkpr ? clock prescale register? on page 48 . this feature can be used to decrease the system clock frequency and the po w er consumption w hen the requirement for pro- cessing po w er is lo w . this can be used w ith all clock source options, and it w ill affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are di v ided by a factor as sho w n in table 7-10 on page 48 . when s w itching bet w een prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system. it also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the pre v ious setting, nor the clock frequency corre- sponding to the ne w setting. the ripple counter that implements the prescaler runs at the frequency of the undi v ided clock, w hich may be faster than the cpu's clock frequency. hence, it is not possible to determine the state of the prescaler - e v en if it w ere readable, and the exact time it takes to s w itch from one clock di v ision to the other cannot be exactly predicted. from the time the clkps v alues are w rit- ten, it takes bet w een t1 + t2 and t1 + 2 t2 before the ne w clock frequency is acti v e. in this inter v al, t w o acti v e clock edges are produced. here, t1 is the pre v ious clock period, and t2 is the period corresponding to the ne w prescaler setting. to a v oid unintentional changes of clock frequency, a special w rite procedure must be follo w ed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, w rite the desired v alue to clkps w hile w riting a zero to clkpce. interrupts must be disabled w hen changing prescaler setting to make sure the w rite procedure is not interrupted. 48 7593l?avr?09/12 at90usb64/128 7.9.1 clkpr ? clock prescale register ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be w ritten to logic one to enable change of th e clkps bits. the clkpce bit is only updated w hen the other bits in clkpr are simultaneously w ritten to zero. clkpce is cleared by hard w are four cycles after it is w ritten or w hen clkps bits are w ritten. re w riting the clkpce bit w ithin this timeout period does neither extend the timeout period, nor clear the clk- pce bit. ? bits 3..0 ? clkps3..0: clock prescaler select bits 3 - 0 these bits define the di v ision factor bet w een the selected clock source and the internal system clock. these bits can be w ritten run-time to v ary the clock frequency to suit the application requirements. as the di v ider di v ides the master clock input to the mcu, the speed of all synchro- nous peripherals is reduced w hen a di v ision factor is used. the di v ision factors are gi v en in table 7-10 . the ckdiv8 fuse determines the initial v alue of the clkps bits. if ckdiv8 is unprogrammed, the clkps bits w ill be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?0011?, gi v ing a di v ision factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the de v ice at the present operat- ing conditions. note that any v alue can be w ritten to the clkps bits regardless of the ckdiv8 fuse setting. the application soft w are must ensure that a sufficient di v ision factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the de v ice at the present operating conditions. the de v ice is shipped w ith the ckdiv8 fuse programmed. table 7-10. clock prescaler select. bit 7 6543210 clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/ w rite r/w r r r r/w r/w r/w r/w initial v alue 0 0 0 0 see bit description clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reser v ed 1010 reser v ed 1011 reser v ed 1100 reser v ed 49 7593l?avr?09/12 at90usb64/128 7.10 pll the pll is used to generate internal high frequency (48mhz) clock for usb interface, the pll input is generated from an external lo w -frequency (the crystal oscill ator or external clock input pin from xtal1). the internal rc oscilla tor can not be used for usb operations. 7.10.1 internal pll for usb interface the internal pll in atmel at90usb64/128 generat es a clock frequency that is 24 multiplied from nominally 2mhz input. the source of the 2m hz pll input clock is the output of the internal pll clock prescaler that generates the 2mhz (see section 7.10.2 for pll interface). figure 7-4. pll clocking system. 7.10.2 pllcsr ? pll control and status register ? bit 7..5 ? res: reserved bits these bits are reser v ed bits in the at90usb64/128 and al w ays read as zero. ? bit 4..2 ? pllp2:0 pll prescaler these bits allo w to configure the pll input prescaler to generate the 2mhz input clock for the pll. 1101 reser v ed 1110 reser v ed 1111 reser v ed clkps3 clkps2 clkps1 clkps0 clock division factor 8mhz rc oscillator xtal1 xtal2 oscillators pll 24x plle lock detector plock clk usb sy s tem clock clk 2mhz pll clock pre s c a ler (48mhz) bit 76543210 $29 ($29) pllp2 pllp1 pllp0 plle plock pllcsr read/ w rite r r r r/w r/w r/w r/w r/w initial v alue0000000/10 50 7593l?avr?09/12 at90usb64/128 note: 1. for atmel at90usb128x only. do not use w ith atmel at90usb64x. 2. for at90usb64x only. do not use w ith at90usb128x. ? bit 1 ? plle: pll enable when the plle is set, the pll is started. ? bit 0 ? plock: pll lock detector when the plock bit is set, the pll is locked to the reference clock. after the pll is enabled, it takes about 100ms for the pll to lock. to clear plock, clear plle and pllpx bits. table 7-11. pll input prescaler configurations. pllp2 pllp1 pllp0 clock division factor external xtal re quired for usb operation [mhz] 000 reser v ed - 001 reser v ed - 010 reser v ed - 011 4 8 100 reser v ed - 101 8 (1) 16 (1) 110 8 (2) 16 (2) 111 reser v ed - 51 7593l?avr?09/12 at90usb64/128 8. power management and sleep modes sleep modes enable the application to shut do w n unused modules in the mcu, thereby sa v ing po w er. the avr pro v ides v arious sleep modes allo w ing the user to tailor the po w er consump- tion to the application?s requirements. to enter any of the fi v e sleep modes, the se bit in smcr must be w ritten to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select w hich sleep mode (idle, adc noise reduction, po w er-do w n, po w er-sa v e, or standby) w ill be acti v ated by the sleep instruction. see table 8-1 for a summary. if an enabled interrupt occurs w hile the mcu is in a sleep mode, the mcu w akes up. the mcu is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction follo w ing sleep. the contents of the register file and sram are unaltered w hen the de v ice w akes up from sleep. if a reset occurs during sleep mode, the mcu w akes up and executes from the reset vector. figure 7-1 on page 40 presents the different clock systems in the atmel at90usb64/128, and their distribution. the figure is helpful in selecting an appropriate sleep mode. 8.0.1 smcr ? sleep mode control register the sleep mode control register contains control bits for po w er management. ? bits 3, 2, 1 ? sm2..0: sleep mode select bits 2, 1, and 0 these bits select bet w een the six a v ailable sleep modes as sho w n in table 8-1 . note: 1. standby modes are only recommended for use w ith external crystals or resonators. ? bit 1 ? se: sleep enable the se bit must be w ritten to logic one to make the mcu enter the sleep mode w hen the sleep instruction is executed. to a v oid the mcu entering the sleep mode unless it is the programmer?s purpose, it is recommended to w rite the sleep enable (se) bit to one just before the execution of the sleep instruction and to clear it immediately after w aking up. bit 76543210 ????sm2sm1sm0sesmcr read/ w riterrrrr/wr/wr/wr/w initial v alue00000000 table 8-1. sleep mode select. sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 010po w er-do w n 011po w er-sa v e 100reser v ed 101reser v ed 110standby (1) 1 1 1 extended standby (1) 52 7593l?avr?09/12 at90usb64/128 8.1 idle mode when the sm2..0 bits are w ritten to 000, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allo w ing the usb, spi, usart, analog comparator, adc, 2- w ire serial interface, timer/counters , watchdog, and the interrupt syst em to continue operating. this sleep mode basically halts clk cpu and clk flash , w hile allo w ing the other clocks to run. idle mode enables the mcu to w ake up from external triggered interrupts as w ell as internal ones like the timer o v erflo w and usart transmit complete interrupts. if w ake-up from the analog comparator interrupt is not required, the analog comparator can be po w ered do w n by setting the acd bit in the analog comparator control and status register ? acsr. this w ill reduce po w er consumption in idle mode. if the adc is enabled, a con v ersion starts automati- cally w hen this mode is entered. 8.2 adc noise reduction mode when the sm2..0 bits are w ritten to 001, the sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allo w ing the adc, the external interrupts, 2- w ire serial interface address match, timer/counter2 and the watchdog to continue operating (if enabled). this sleep mode basically halts clki/o, clkcpu, and clkflash, w hile allo w ing the other clocks to run (including clkusb). this impro v es the noise en v ironment for the adc, enabling higher resolution measurements. if the adc is enabled, a con v ersion starts automatically w hen this mode is entered. apart form the adc con v ersion complete interrupt, only an external reset, a watchdog system reset, a watchdog interrupt, a bro w n-out reset, a 2- w ire serial interface interrupt, a timer/counter2 interrupt, an spm/eeprom ready interrupt, an external le v el interrupt on int7:4 or a pin change interrupt can w akeup the mcu from adc noise reduction mode. 8.3 power-down mode when the sm2..0 bits are w ritten to 010, the sleep instruction makes the mcu enter po w er- do w n mode. in this mo de, the extern al oscillator is stopped, w hile the external interrupts, the 2- w ire serial interface, and the watchdog continue operating (if enabled). only an external reset, a watchdog reset, a bro w n-out reset, 2- w ire serial interface address match, an external le v el interrupt on int7:4, an external interrupt on int3:0, a pin change interrupt or an asynchronous usb interrupt sources (vbusti, wakeupi, idti and hwupi), can w ake up the mcu. this sleep mode basically halts all generated clocks, allo w ing operation of asynchronous modules only. note that if a le v el triggered interrupt is used for w ake-up from po w er-do w n mode, the changed le v el must be held for some time to w ake up the mcu. refer to ?external interrupts? on page 92 for details. when w aking up from po w er-do w n mode, there is a delay from the w ake-up condition occurs until the w ake-up becomes effecti v e. this allo w s the clock to restart and become stable after ha v ing been stopped. the w ake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 41 . 8.4 power-save mode when the sm2..0 bits are w ritten to 011, the sleep instruction makes the mcu enter po w er- sa v e mode. this mode is identical to po w er-do w n, w ith one exception: 53 7593l?avr?09/12 at90usb64/128 if timer/counter2 is enabled, it w ill keep running during sleep. the de v ice can w ake up from either timer o v erflo w or output compare e v ent from timer/counter2 if the corresponding timer/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if timer/counter2 is not running, po w er-do w n mode is recommended instead of po w er-sa v e mode. the timer/counter2 can be clocked both synchronously and asynchronously in po w er-sa v e mode. if the time r/counter2 is not using t he asynchronous clock, the timer/counter oscillator is stopped during sleep. if the timer/counter2 is not using the synchronous clock, the clock source is stopped during sleep. note that e v en if the synchronous clock is running in po w er-sa v e, this clock is only a v ailable for the timer/counter2. 8.5 standby mode when the sm2..0 bits are 110 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to po w er-do w n w ith the exception that the oscillator is kept runnin g. from standb y mode, the de v ice w akes up in six clock cycles. note that in stanby mode the pll is disabled and the usb interface w ill not function. 8.6 extended standby mode when the sm2..0 bits are 111 and an external crystal/resonator clock option is selected, the sleep instruction makes the m cu enter extended standby mode . this mode is identical to po w er-sa v e mode w ith the exception that the oscillator is kept running. from extended standby mode, the de v ice w akes up in six clock cycles. notes: 1. only recommended w ith external crystal or resonat or selected as clock source. 2. if timer/counter2 is running in asynchronous mode. 3. for int7:4, only le v el interrupt. 4. asynchronous usb interrupts ar e vbusti, wakeupi, idti and hwupi. table 8-2. acti v e clock domains and w ake-up sources in the different sleep modes. active clock domains oscillators wake-up sources sleep mode clk cpu clk flash clk io clk adc clk asy main clock source enabled timer oscillator enabled int7:0 and pin change twi address match timer2 spm/ eeprom ready adc wdt interrupt other i/o usb synchronous interrupts usb asynchonous interrupts (4) idle xxxxx (2) xxxxxxxxx adcnrm x x x x (2) x (3) xx (2) xxx xx po w er-do w nx (3) xxx po w er-sa v exx (2) x (3) xxxx standby (1) xx (3) xxx extended standby x (2) xx (2) x (3) xxxx 54 7593l?avr?09/12 at90usb64/128 8.7 power reduction register the po w er reduction register, prr, pro v ides a method to stop the clock to indi v idual peripher- als to reduce po w er consumption. the current state of the peripheral is frozen and the i/o registers can not be read or w ritten. resources used by the peripheral w hen stopping the clock w ill remain occupied, hence the perip heral should in most cases be disabled before stopping the clock. waking up a module, w hich is done by clearing the bit in prr, puts the module in the same state as before shutdo w n. module shutdo w n can be used in idle mode and acti v e mode to significantly reduce the o v erall po w er consumption. in all other sleep modes, the clock is already stopped. 8.7.1 prr0 ? power reduction register 0 ? bit 7 - prtwi: power reduction twi writing a logic one to this bit shuts do w n the twi by stopping the clock to the module. when w aking up the twi again, the twi should be re initialized to ensure proper operation. ? bit 6 - prtim2: power reduction timer/counter2 writing a logic one to this bit shuts do w n the timer/counter2 module in synchronous mode (as2 is 0). when the timer/counter2 is enabled, operation w ill continue like before the shutdo w n. ? bit 5 - prtim0: power reduction timer/counter0 writing a logic one to this bit shuts do w n the timer/counter0 module. when the timer/counter0 is enabled, operation w ill continue like before the shutdo w n. ? bit 4 - res: reserved bit this bit is reser v ed and w ill al w ays read as zero. ? bit 3 - prtim1: power reduction timer/counter1 writing a logic one to this bit shuts do w n the timer/counter1 module. when the timer/counter1 is enabled, operation w ill continue like before the shutdo w n. ? bit 2 - prspi: power reduction serial peripheral interface writing a logic one to this bit shuts do w n the serial peripheral interface by stopping the clock to the module. when w aking up the spi again, the spi should be re initialized to ensure proper operation. ? bit 1 - res: reserved bit these bits are reser v ed and w ill al w ays read as zero. ? bit 0 - pradc: power reduction adc writing a logic one to this bit shuts do w n the adc. the adc must be disabled before shut do w n. the analog comparator cannot use the adc input mux w hen the adc is shut do w n. bit 7654321 0 prtwi prtim2 prtim0 ? prtim1 prspi - pradc prr0 read/ w rite r/w r/w r/w r r/w r/w r r/w initial v alue0000000 0 55 7593l?avr?09/12 at90usb64/128 8.7.2 prr1 ? power reduction register 1 ? bit 7 - prusb: power reduction usb writing a logic one to this bit shuts do w n the usb by stopping the clock to the module. when w aking up the usb again, the usb should be re initialized to ensure proper operation. ? bit 6..4 - res: reserved bits these bits are reser v ed and w ill al w ays read as zero. ? bit 3 - prtim3: power reduction timer/counter3 writing a logic one to this bit shuts do w n the timer/counter3 module. when the timer/counter3 is enabled, operation w ill continue like before the shutdo w n. ? bit 2..1 - res: reserved bits these bits are reser v ed and w ill al w ays read as zero. ? bit 0 - prusart1: power reduction usart1 writing a logic one to this bit shuts do w n the usart1 by stopping the clock to the module. when w aking up the usart1 again, the usart1 should be re-initialized to ensure proper operation. 8.8 minimizing power consumption there are se v eral issues to consider w hen trying to minimize the po w er consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as fe w as possible of the de v ice?s functions are operating. all functions not needed should be disabled. in particular, the follo w ing modules may need special consideration w hen trying to achie v e the lo w est possible po w er consumption. 8.8.1 analog to digital converter if enabled, the adc w ill be enabled in all sleep modes. to sa v e po w er, the adc should be dis- abled before entering any sleep mode. when the adc is turned off and on again, the next con v ersion w ill be an extended con v ersion. refer to ?adc ? analog to digital con v erter? on page 307 for details on adc operation. 8.8.2 analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is automatically disabled. ho w e v er, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. other w ise, the internal voltage reference w ill be enabled, independent of sleep mode. refer to ?analog comparator? on page 304 for details on ho w to configure the analog comparator. bit 7 6543 210 prusb???prtim3??prusart1prr1 read/ w riter/wrrrr/w rrr/w initial v alue0 0000 000 56 7593l?avr?09/12 at90usb64/128 8.8.3 brown-out detector if the bro w n-out detector is not needed by the application, this module should be turned off. if the bro w n-out detector is enabled by the bodlevel fuses, it w ill be enabled in all sleep modes, and hence, al w ays consume po w er. in the deeper sleep modes, this w ill contribute sig- nificantly to the total current consumption. refer to ?bro w n-out detection? on page 60 for details on ho w to configure the bro w n-out detector. 8.8.4 internal voltage reference the internal v oltage reference w ill be enabled w hen needed by the bro w n-out detection, the analog comparator or the adc. if these modules are disabled as described in the sections abo v e, the internal v oltage reference w ill be disabled and it w ill not be consuming po w er. when turned on again, the user must allo w the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal v olt- age reference? on page 62 for details on the start-up time. 8.8.5 watchdog timer if the watchdog timer is not needed in the application, the module should be turned off. if the watchdog timer is enabled, it w ill be enabled in all sleep modes, and hence, al w ays consume po w er. in the deeper sleep modes, this w ill contribute significantly to the total current consump- tion. refer to ?interrupts? on page 68 for details on ho w to configure the watchdog timer. 8.8.6 port pins when entering a sleep mode, all port pins should be configured to use minimum po w er. the most important is then to ensure that no pins dri v e resisti v e loads. in sleep modes w here both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the de v ice w ill be disabled. this ensures that no po w er is consumed by the input logic w hen not needed. in some cases, the input logic is needed for detecting w ake-up conditions, and it w ill then be enabled. refer to the section ?digital input enable and sleep modes? on page 75 for details on w hich pins are enabled. if the input buffer is enabl ed and the input signal is left floating or ha v e an analog signal le v el close to v cc /2, the input buffer w ill use excessi v e po w er. for analog input pins, the digital input buffer should be disabled at all times. an analog signal le v el close to v cc /2 on an input pin can cause significant current e v en in acti v e mode. digital input buffers can be disabled by w riting to the digital input disable registers (didr1 and didr0). refer to ?didr1 ? digital input disable register 1? on page 306 and ?didr0 ? digital input disable register 0? on page 326 for details. 8.8.7 on-chip debug system if the on-chip debug system is enabled by the ocden fuse and the chip enters sleep mode, the main clock source is enabled, and hence, al w ays consumes po w er. in the deeper sleep modes, this w ill contribute significantly to the total curren t consumption. there are three alternati v e w ays to disable the ocd system: ? disable the ocden fuse ? disable the jtagen fuse ? write one to the jtd bit in mcucr 57 7593l?avr?09/12 at90usb64/128 9. system control and reset 9.1 resetting the avr during reset, all i/o regist ers are set to their initial v alues, and the program starts execution from the reset vector. the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. if the program ne v er enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section w hile the interrupt vectors are in the boot section or v ice v ersa. the circuit diagram in figure 9-1 on page 58 sho w s the reset logic. table 9-1 on page 58 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state w hen a reset source goes acti v e. this does not require any clock source to be running. after all reset sources ha v e gone inacti v e, a delay counter is in v oked, stretching the internal reset. this allo w s the po w er to reach a stable le v el before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the dif- ferent selections for the delay period are presented in ?clock sources? on page 41 . 9.2 reset sources the atmel at90usb64/128 has fi v e sources of reset: ?po w er-on reset. the mcu is reset w hen the supply v oltage is belo w the po w er-on reset threshold (v pot ) ? external reset. the mcu is reset w hen a lo w le v el is present on the reset pin for longer than the minimum pulse length ? watchdog reset. the mcu is reset w hen the watchdog timer period expires and the watchdog is enabled ?bro w n-out reset. the mcu is reset w hen the supply v oltage v cc is belo w the bro w n-out reset threshold (v bot ) and the bro w n-out detector is enabled ? jtag avr reset. the mcu is reset as long as there is a logic one in the reset register, one of the scan chains of the jtag system. refer to section ?ieee 1149.1 (jta g) boundary- scan? on page 333 for details 58 7593l?avr?09/12 at90usb64/128 figure 9-1. reset logic. notes: 1. the por w ill not w ork unless the supply v oltage has been belo w v pot (falling). 9.3 power-on reset a po w er-on reset (por) pulse is generated by an on-chip detection circuit. the detection le v el is defined in table 9-1 . the por is acti v ated w hene v er v cc is belo w the detection le v el. the por circuit can be used to trigger the start-up reset, as w ell as to detect a failure in supply v oltage. a po w er-on reset (por) circuit ensures that the de v ice is properly reset from po w er-on if vcc started from v por w ith a rise rate upper than v ccrr . reaching the po w er-on reset threshold table 9-1. reset characteristics. symbol parameter condition min. typ. max. units v pot po w er-on reset threshold v oltage (rising) 1.4 2.3 v po w er-on reset threshold v oltage (falling) (1) 1.3 2.3 v por v cc start v oltage to ensure internal po w er- on reset signal -0.1 0.1 v ccrr v cc rise rate to ensure internal po w er_on reset signal 0.3 v/ms v rst reset pin threshold v oltage 0.2 v cc 0.85 v cc v t rst minimum pulse w idth on reset pin 5v, 25c 400 ns mcu s t a t us regi s ter (mcusr) brown-o u t re s et circ u it bodlevel [2..0] del a y co u nter s cksel[ 3 :0] ck timeout wdrf borf extrf porf data b u s clock gener a tor spike filter p u ll- u p re s i s tor jtrf jtag re s et regi s ter w a tchdog o s cill a tor sut[1:0] power-on re s et circ u it 59 7593l?avr?09/12 at90usb64/128 v oltage in v okes the delay counter, w hich determines ho w long the de v ice is kept in reset after v cc rise. the reset signal is acti v ated again, w ithout any delay, w hen v cc decreases belo w the detection le v el. figure 9-2. mcu start-up, reset tied to v cc . figure 9-3. mcu start-up, reset extended externally. note: if v por or v ccrr parameter range can not be follo w ed, an external reset is required. 9.4 external reset an external reset is generated by a lo w le v el on the reset pin. reset pulses longer than the minimum pulse w idth (see table 9-1 on page 58 ) w ill generate a reset, e v en if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positi v e edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. v re s et time-out internal re s et t tout v pot v r s t cc v por re s et timeout internal re s et t tout v pot v r s t v cc v por 60 7593l?avr?09/12 at90usb64/128 figure 9-4. external reset during operation. 9.5 brown-out detection atmel at90usb64/128 has an on-chip bro w n-out detection (bod) circuit for monitoring the v cc le v el during operation by comparing it to a fixed trigger le v el. the trigger le v el for the bod can be selected by the bodl evel fuses. the trigger le v el has a hysteresis to ensure spike free bro w n-out detection. the hysteresis on the detection le v el should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. when the bod is enabled, and v cc decreases to a v alue belo w the trigger le v el (v bot- in figure 9-5 on page 61 ), the bro w n-out reset is immediately acti v ated. when v cc increases abo v e the trigger le v el (v bot+ in figure 9-5 on page 61 ), the delay counter starts the mcu after the time- out period t tout has expired. the bod circuit w ill only detect a drop in v cc if the v oltage stays belo w the trigger le v el for lon- ger than t bod gi v en in table 9-1 on page 58 . cc table 9-2. bodlevel fuse coding. bodlevel 2..0 fuses min. v bot typ. v bot max. v bot units 111 bod disabled 110 reser v ed 101 100 011 2.4 2.6 2.8 v 010 3.2 3.4 3.6 001 3.3 3.5 3.7 000 4.1 4.3 4.5 table 9-3. bro w n-out characteristics. symbol parameter min. typ. max. units v hyst bro w n-out detector hysteresis 50 mv t bod min. pulse w idth on bro w n-out reset ns i bod bro w n-out detector consumption 25 a 61 7593l?avr?09/12 at90usb64/128 figure 9-5. bro w n-out reset during operation. 9.6 watchdog reset when the watchdog times out, it w ill generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to page 63 for details on operation of the watchdog timer. figure 9-6. watchdog reset during operation. 9.6.1 mcusr ? mcu status register the mcu status register pro v ides information on w hich reset source caused an mcu reset. ? bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a logic one in the jtag reset register selected by the jtag instruction avr_reset. this bit is reset by a po w er-on reset, or by w riting a logic zero to the flag. ? bit 3 ? wdrf: watchdog reset flag this bit is set if a watchdog reset occurs. the bit is reset by a po w er-on reset, or by w riting a logic zero to the flag. v cc re s et timeout internal re s et v bot- v bot+ t tout ck cc bit 76543210 ? ? ? jtrf wdrf borf extrf porf mcusr read/ w rite r r r r/w r/w r/w r/w r/w initial v alue 0 0 0 see bit description 62 7593l?avr?09/12 at90usb64/128 ? bit 2 ? borf: brown-out reset flag this bit is set if a bro w n-out reset occurs. the bit is reset by a po w er-on reset, or by w riting a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bit is reset by a po w er-on reset, or by w riting a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a po w er-on reset occurs. the bit is reset only by w riting a logic zero to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. 9.7 internal voltage reference atmel at90usb64/128 features an internal bandgap reference. this reference is used for bro w n-out detection, and it can be used as an input to the analog comparator or the adc. 9.7.1 voltage reference enable signals and start-up time the v oltage reference has a start-up time that may influence the w ay it should be used. the start-up time is gi v en in table 9-4 . to sa v e po w er, the reference is not al w ays turned on. the reference is on during the follo w ing situations: 1. when the bod is enabled (by prog ramming the bodlevel [2..0] fuse). 2. when the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, w hen the bod is not enabled, after setting the acbg bit or enabling the adc, the user must al w ays allo w the reference to start up before the output from the analog comparator or adc is used. to reduce po w er consumption in po w er-do w n mode, the user can a v oid the three conditions abo v e to ensure that the reference is turned off before entering po w er-do w n mode. table 9-4. internal v oltage reference characteristics. symbol parameter conditi on min. typ. max. units v bg bandgap reference v oltage 1.0 1.1 1.2 v t bg bandgap reference start-up time 40 70 s i bg bandgap reference current consumption 10 a 63 7593l?avr?09/12 at90usb64/128 9.8 watchdog timer the atmel at90usb64/128 has an enhanced watchdog timer (wdt). the main features are: ? clocked from separate on-chip oscillator ? three operating modes ?interrupt ? system reset ? interrupt and system reset ? selectable time-out pe riod from 16ms to 8s ? possible hardware fuse watchdog always on (wdton) for fail-safe mode figure 9-7. watchdog timer. the watchdog timer (wdt) is a timer counting cy cles of a separate on- chip 128khz oscillator. the wdt gi v es an interrupt or a system reset w hen the counter reaches a gi v en time-out v alue. in normal operation mode, it is required that the system uses the wdr - watchdog timer reset - instruction to restart the counter before the time-out v alue is reached. if the system doesn't restart the counter, an interrupt or system reset w ill be issued. in interrupt mode, the wdt gi v es an interrupt w hen the timer expires. this interrupt can be used to w ake the de v ice from sleep-modes, and also as a gen eral system timer. one example is to limit the maximum time allo w ed for certain operations, gi v ing an interrupt w hen the operation has run longer than expected. in system reset mode, the wdt gi v es a reset w hen the timer expires. this is typically used to pre v ent system hang-up in case of runa w ay code. the third mode, interrupt and system reset mode, combines the other t w o modes by first gi v ing an inter- rupt and then s w itch to system reset mode. this mode w ill for instance allo w a safe shutdo w n by sa v ing critical parameters before a system reset. the watchdog al w ays on (wdton) fuse, if programmed, w ill force the watchdog timer to sys- tem reset mode. with the fuse programmed the system reset mode bit (wde) and interrupt mode bit (wdie) are locked to 1 and 0 respecti v ely. to further ensure program security, altera- tions to the watchdog set-up must follo w timed sequences. the sequence for clearing wde and changing time-out configuration is as follo w s: 128khz oscillator osc/2k osc/4k osc/8k osc/16k osc/ 3 2k osc/64k osc/128k osc/256k osc/512k osc/1024k wdp0 wdp1 wdp2 wdp 3 watchdog reset wde wdif wdie mcu reset interrupt 64 7593l?avr?09/12 at90usb64/128 1. in the same operation, w rite a logic one to the watchdog change enable bit (wdce) and wde. a logic one must be w ritten to wde regardless of the pre v ious v alue of the wde bit. 2. within the next four clock cycles, w rite the wde and watchdog prescaler bits (wdp) as desired, but w ith the wdce bit cleared. this must be done in one operation. the follo w ing code example sho w s one assembly and one c function for turning off the watch- dog timer. the example assumes that interrupt s are controlled (for example by disabling interrupts globally) so that no interrupts w ill occur during the execut ion of these functions. note: 1. the example code assumes that the pa rt specific header file is included. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, ~(0< 67 7593l?avr?09/12 at90usb64/128 . table 9-6. watchdog timer prescale select. wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0 0 0 0 2k (2048) cycles 16ms 0 0 0 1 4k (4096) cycles 32ms 0 0 1 0 8k (8192) cycles 64ms 0 0 1 1 16k (16384) cycles 0.125s 0 1 0 0 32k (32768) cycles 0.25s 0 1 0 1 64k (65536) cycles 0.5s 0 1 1 0 128k (131072) cycles 1.0s 0 1 1 1 256k (262144) cycles 2.0s 1 0 0 0 512k (524288) cycles 4.0s 1 0 0 1 1024k (1048576) cycles 8.0s 1010 reser v ed 1011 1100 1101 1110 1111 68 7593l?avr?09/12 at90usb64/128 10. interrupts this section describes the specifics of the interrupt handling as performed in atmel at90usb64/128. for a general explanation of the avr interrupt handling, refer to ?reset and interrupt handling? on page 17 . 10.1 interrupt vect ors in at90usb64/128 table 10-1. reset and interrupt v ectors. vector no. program address (2) source interrupt definition 1 $0000 (1) reset external pin, po w er-on reset, bro w n-out reset, watchdog reset, a nd jtag avr reset 2 $0002 int0 external interrupt request 0 3 $0004 int1 external interrupt request 1 4 $0006 int2 external interrupt request 2 5 $0008 int3 external interrupt request 3 6 $000a int4 external interrupt request 4 7 $000c int5 external interrupt request 5 8 $000e int6 external interrupt request 6 9 $0010 int7 external interrupt request 7 10 $0012 pcint0 pin change interrupt request 0 11 $0014 usb general usb general interrupt request 12 $0016 usb endpoint/pipe usb endpoint/pipe interrupt request 13 $0018 wdt watchdog time-out interrupt 14 $001a timer2 compa timer/counter2 compare match a 15 $001c timer2 compb timer/counter2 compare match b 16 $001e timer2 ovf timer/counter2 o v erflo w 17 $0020 timer1 capt timer/counter1 capture e v ent 18 $0022 timer1 compa timer/counter1 compare match a 19 $0024 timer1 compb timer/counter1 compare match b 20 $0026 timer1 compc timer/counter1 compare match c 21 $0028 timer1 ovf timer/counter1 o v erflo w 22 $002a timer0 compa timer/counter0 compare match a 23 $002c timer0 compb timer/counter0 compare match b 24 $002e timer0 ovf timer/counter0 o v erflo w 25 $0030 spi, stc spi serial transfer complete 26 $0032 usart1 rx usart1 rx complete 27 $0034 usart1 udre usart1 data register empty 28 $0036 usart1tx usart1 tx complete 29 $0038 analog comp analog comparator 69 7593l?avr?09/12 at90usb64/128 notes: 1. when the bootrst fuse is programmed, the de v ice w ill jump to the boot loader address at reset, see ?memory programming? on page 359 . 2. when the ivsel bit in mcu cr is set, interrupt vectors w ill be mo v ed to the start of the boot flash section. the address of each interrupt vector w ill then be the address in this table added to the start address of the boot flash section. table 10-2 sho w s reset and interrupt vectors placement for the v arious combinations of bootrst and ivsel settin gs. if the program ne v er enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section w hile the interrupt vectors are in the boot section or v ice v ersa. note: 1. the boot reset address is sho w n in table 29-8 on page 357 . for the bootrst fuse ?1? means unprogrammed w hile ?0? means programmed. 10.1.1 moving interrupts between application and boot space the general interrupt control register controls the placement of the interrupt vector table. 10.1.2 mcucr ? mcu control register ? bit 1 ? ivsel: interrupt vector select when the ivsel bit is cleared (z ero), the interrupt vectors are pl aced at the star t of the flash memory. when this bit is set (one), the interrupt vectors are mo v ed to the beginning of the boot 30 $003a adc adc con v ersion complete 31 $003c ee ready eeprom ready 32 $003e timer3 capt timer/counter3 capture e v ent 33 $0040 timer3 compa timer/counter3 compare match a 34 $0042 timer3 compb timer/counter3 compare match b 35 $0044 timer3 compc timer/counter3 compare match c 36 $0046 timer3 ovf timer/counter3 o v erflo w 37 $0048 twi 2- w ire serial interface 38 $004a spm ready store program memory ready table 10-2. reset and interrupt v ectors placement (1) . bootrst ivsel reset address inte rrupt vectors start address 1 0 0x0000 0x0002 1 1 0x0000 boot reset address + 0x0002 0 0 boot reset address 0x0002 0 1 boot reset address boot reset address + 0x0002 table 10-1. reset and interrupt v ectors. (continued) vector no. program address (2) source interrupt definition bit 76543210 jtd ? ? pud ? ? ivsel ivce mcucr read/ w riter/wrrr/wrrr/wr/w initial v alue00000000 70 7593l?avr?09/12 at90usb64/128 loader section of the flash. the actual address of the start of the boot flash section is deter- mined by the bootsz fuses. refer to section ?memory programming? on page 359 for details. to a v oid unintentional changes of interrupt vector tables, a special w rite procedure must be fol- lo w ed to change the ivsel bit: a. write the interrupt vector change enable (ivce) bit to one. b. within four cycles, w rite the desired v alue to ivsel w hile w riting a zero to ivce. interrupts w ill automatically be disabled w hile this sequence is executed. interrupts are disabled in the cycle ivce is set, and they remain disabled until after the instruction follo w ing the w rite to ivsel. if ivsel is not w ritten, interrupts remain disabled for four cycles. the i-bit in the status register is unaffected by the automatic disabling. note: if interrupt vectors are placed in the boot loader section and boot lock bit blb02 is programmed, interrupts are disabled w hile executing from the application sect ion. if interrupt vectors are placed in the application section and boot lock bit bl b12 is programed, interrupts are disabled w hile executing from the boot loader section. refer to the section ?memory programming? on page 359 for details on boot lock bits. ? bit 0 ? ivce: interrupt vector change enable the ivce bit must be w ritten to logic one to enable change of the ivsel bit. ivce is cleared by hard w are four cycles after it is w ritten or w hen ivsel is w ritten. setting the ivce bit w ill disable interrupts, as explained in the ivsel description abo v e. see code example belo w . assembly code example move_interrupts: ; get mcucr in r16, mcucr mov r17, r16 ; enable change of interrupt vectors ori r16, (1< 72 7593l?avr?09/12 at90usb64/128 11.2 ports as general digital i/o the ports are bi-directional i/o ports w ith optional internal pull-ups. figure 11-2 sho w s a func- tional description of one i/o-port pin, here generically called pxn. figure 11-2. general digital i/o (1) . note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins w ithin the same port. clk i/o , sleep, and pud are common to all ports. 11.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as sho w n in ?register description for i/o-ports? on page 89 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direction of this pin. if ddxn is w ritten logic one, pxn is configured as an output pin. if ddxn is w ritten logic zero, pxn is configured as an input pin. if portxn is w ritten logic one w hen the pin is configured as an i nput pin, the pull-up resistor is acti v ated. to s w itch the pull-up resistor off, portxn has to be w ritten logic zero or the pin has to be configured as an output pin. the port pins are tri-stated w hen reset condition becomes acti v e, e v en if no clocks are running. if portxn is w ritten logic one w hen the pin is configured as an output pin, the port pin is dri v en high (one). if portxn is w ritten logic zero w hen the pin is configured as an output pin, the port pin is dri v en lo w (zero). clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 73 7593l?avr?09/12 at90usb64/128 11.2.2 toggling the pin writing a logic one to pinxn toggles the v alue of portxn, independent on the v alue of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 11.2.3 switching between input and output when s w itching bet w een tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state w ith either pull-up enabled {ddxn, portxn} = 0b01) or output lo w ({ddxn, portxn} = 0b10) occurs. normally, the pull-up enabled state is fully acceptable, as a high-impedant en v ironment w ill not notice the difference bet w een a strong high dri v er and a pull-up. if this is not the case, the pud bit in th e mcucr register can be set to disable all pull- ups in all ports. s w itching bet w een input w ith pull-up and output lo w generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 11-1 summarizes the control signals for the pin v alue. 11.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as sho w n in figure 11-2 on page 72 , the pinxn register bit and the preced- ing latch constitute a synchronizer. this is needed to a v oid metastability if the physical pin changes v alue near the edge of the internal clock, but it also introduces a delay. figure 11-3 on page 74 sho w s a timing diagram of the synchronization w hen reading an externally applied pin v alue. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respecti v ely. table 11-1. port pin configurations. ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn w ill source current if ext. pulled lo w 0 1 1 input no tri-state (hi-z) 1 0 x output no output lo w (sink) 1 1 x output no output high (source) 74 7593l?avr?09/12 at90usb64/128 figure 11-3. synchronization w hen reading an externally applied pin v alue. consider the clock period starting shortly after the first falling edge of the system cl ock. the latch is closed w hen the clock is lo w , and goes transparent w hen the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal v alue is latched w hen the system clock goes lo w . it is clocked into the pinxn register at the succeeding positi v e clock edge. as indi- cated by the t w o arro w s tpd,max and tpd,min, a single signal transition on the pin w ill be delayed bet w een ? and 1? system clock period depending upon the time of assertion. when reading back a soft w are assigned pin v alue, a nop instruction must be inserted as indi- cated in figure 11-4 . the out instruction sets the ?sync latch? signal at the positi v e edge of the clock. in this case, the delay tpd through the synchronizer is one system clock period. figure 11-4. synchronization w hen reading a soft w are assigned pin v alue. the follo w ing code example sho w s ho w to set port b pins 0 and 1 high, 2 and 3 lo w , and define the port pins from 4 to 7 as input w ith pull-ups assigned to port pins 6 and 7. the resulting pin v alues are read back again, but as pre v iously discussed, a nop instruction is included to be able to read back the v alue recently assigned to some of the pins. xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, m a x t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 75 7593l?avr?09/12 at90usb64/128 note: 1. for the assembly program, t w o temporary registers are used to minimize the time from pull- ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as lo w and redefining bits 0 and 1 as strong high dri v ers. 11.2.5 digital input enable and sleep modes as sho w n in figure 11-2 on page 72 , the digital input signal can be clamped to ground at the input of the schmitt-trigger. th e signal denoted sleep in the fi gure, is set by the mcu sleep controller in po w er-do w n mode, po w er-sa v e mode, and standby mode to a v oid high po w er consumption if some input signals are left floating, or ha v e an analog signal le v el close to v cc /2. sleep is o v erridden for port pins enabled as external interrupt pins. if the external interrupt request is no t enabled, sleep is acti v e also for these pi ns. sleep is also o v erridden by v arious other alternate functions as described in ?alternate port functions? on page 76 . if a logic high le v el (?one?) is present on an asynchronous external interrupt pin configured as ?interrupt on rising edge, falling edge, or any logic change on pin? w hile the external interrupt is not enabled, the corresponding external interrupt flag w ill be set w hen resuming from the abo v e mentioned sleep mode, as the clamping in these sleep mode produces the requested logic change. 11.2.6 unconnected pins if some pins are unused, it is re commended to ensure that these pins ha v e a defined le v el. e v en though most of the digital inputs are disabled in the deep sleep modes as described abo v e, float- assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 77 7593l?avr?09/12 at90usb64/128 table 11-2 summarizes the function of the o v erriding signals. the pin and port indexes from fig- ure 11-5 on page 76 are not sho w n in the succeeding tables. the o v erriding signals are generated internally in the modules ha v ing the alternate function. the follo w ing subsections shortly describe the alternate functions for each port, and relate the o v erriding signals to the alternate function. refer to the alternate function description for further details. table 11-2. generic description of o v erriding signals for alternate functions. signal name full name description puoe pull-up o v erride enable if this signal is set, the pull-up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled w hen {ddxn, portxn, pud} = 0b010. puov pull-up o v erride value if puoe is set, the pull-up is enabled/disabled w hen puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction o v erride enable if this signal is set, the output dri v er enable is controlled by the ddov signal. if this signal is cleared, the output dri v er is enabled by the ddxn register bit. ddov data direction o v erride value if ddoe is set, the output dri v er is enabled/disabled w hen ddov is set/cleared, regardless of the setting of the ddxn register bit. pvoe port value o v erride enable if this signal is set and the output dri v er is enabled, the port v alue is controlled by the pvov signal. if pvoe is cleared, and the output dri v er is enabled, the port value is controlled by the portxn register bit. pvov port value o v erride value if pvoe is set, the port v alue is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle o v erride enable if ptoe is set, the portxn register bit is in v erted. dieoe digital input enable o v erride enable if this bit is set, the digital input enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable o v erride value if dieoe is set, the digita l input is enabled/disabled w hen dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to alternate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module w ith the alternate function w ill use its o w n synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi-directionally. 78 7593l?avr?09/12 at90usb64/128 11.3.1 mcucr ? mcu control register ? bit 4 ? pud: pull-up disable when this bit is w ritten to one, the pull-ups in the i/o ports are disabled e v en if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?con- figuring the pin? on page 72 for more details about this feature. 11.3.2 alternate functions of port a the port a has an alternate function as the address lo w byte and data lines for the external memory interface. table 11-4 and table 11-5 on page 79 relates the alternate functions of port a to the o v erriding signals sho w n in figure 11-5 on page 76 . bit 7 6 5 4 3 2 1 0 jtd ? ?pud ? ? ivsel ivce mcucr read/ w rite r/w r r r/w r r r/w r/w initial v alue 0 0 0 0 0 0 0 0 table 11-3. port a pins alternate functions. port pin alternate function pa7 ad7 (external memory interface address and data bit 7) pa6 ad6 (external memory interface address and data bit 6) pa5 ad5 (external memory interface address and data bit 5) pa4 ad4 (external memory interface address and data bit 4) pa3 ad3 (external memory interface address and data bit 3) pa2 ad2 (external memory interface address and data bit 2) pa1 ad1 (external memory interface address and data bit 1) pa0 ad0 (external memory interface address and data bit 0) table 11-4. o v erriding signals for alternate functions in pa7..pa4. signal name pa7/ad7 pa6/ad6 pa5/ad5 pa4/ad4 puoe sre sre sre sre puov ~(wr | ada (1) ) ? porta7 ? pud ~(wr | ada) ? porta6 ? pud ~(wr | ada) ? porta5 ? pud ~(wr | ada) ? porta4 ? pud ddoe sre sre sre sre ddov wr | ada wr | ada wr | ada wr | ada pvoe sre sre sre sre pvov a7 ? ada | d7 output ? wr a6 ? ada | d6 output ? wr a5 ? ada | d5 output ? wr a4 ? ada | d4 output ? wr dieoe 0 0 0 0 dieov 0 0 0 0 did7 inputd6 inputd5 inputd4 input aio ? ? ? ? 79 7593l?avr?09/12 at90usb64/128 note: 1. ada is short for address acti v e and represents the time w hen address is output. see ?exter- nal memory interface? on page 31 for details. 11.3.3 alternate functions of port b the port b pins w ith alternate functions are sho w n in table 11-6 . the alternate pin configuration is as follo w s: ? oc0a/oc1c/pcint7, bit 7 oc0a, output compare match a output: the pb7 pin can ser v e as an external output for the timer/counter0 output compare. the pin has to be configured as an output (ddb7 set ?one?) to ser v e this function. the oc0a pin is also the output pin for the pwm mode timer function. table 11-5. o v erriding signals for alternate functions in pa3..pa0. signal name pa3/ad3 pa2/ad2 pa1/ad1 pa0/ad0 puoe sre sre sre sre puov ~(wr | ada) ? porta3 ? pud ~(wr | ada) ? porta2 ? pud ~(wr | ada) ? porta1 ? pud ~(wr | ada) ? porta0 ? pud ddoe sre sre sre sre ddov wr | ada wr | ada wr | ada wr | ada pvoe sre sre sre sre pvov a3 ? ada | d3 output ? wr a2? ada | d2 output ? wr a1 ? ada | d1 output ? wr a0 ? ada | d0 output ? wr dieoe 0 0 0 0 dieov 0 0 0 0 di d3 input d2 input d1 input d0 input aio ? ? ? ? table 11-6. port b pins alternate functions. port pin alternate functions pb7 oc0a/oc1c/pcint7 (output compare and pwm output a for timer/counter0, output compare and pwm output c for timer/counter1 or pin change interrupt 7) pb6 oc1b/pcint6 (output compare and pwm ou tput b for timer/counter1 or pin change interrupt 6) pb5 oc1a/pcint5 (output compare and pwm ou tput a for timer/counter1 or pin change interrupt 5) pb4 oc2a/pcint4 (output compare and pwm ou tput a for timer/counter2 or pin change interrupt 4) pb3 pdo/miso/pcint3 (progra mming data output or spi bus master input/sla v e output or pin change interrupt 3) pb2 pdi/mosi/pcint2 (programming data input orspi bus master output/sla v e input or pin change interrupt 2) pb1 sck/pcint1 (spi bus serial clo ck or pin change interrupt 1) pb0 ss /pcint0 (spi sla v e select input or pin change interrupt 0) 80 7593l?avr?09/12 at90usb64/128 oc1c, output compare match c output: the pb7 pin can ser v e as an external output for the timer/counter1 output compare c. the pin has to be configured as an output (ddb7 set (one)) to ser v e this function. the oc1c pin is also the output pin for the pwm mode timer function. pcint7, pin change interrupt source 7: the pb7 pin can ser v e as an external interrupt source. ? oc1b/pcint6, bit 6 oc1b, output compare match b output: the pb6 pin can ser v e as an external output for the timer/counter1 output compare b. the pin has to be configured as an output (ddb6 set (one)) to ser v e this function. the oc1b pin is also the output pin for the pwm mode timer function. pcint6, pin change interrupt source 6: the pb6 pin can ser v e as an external interrupt source. ? oc1a/pcint5, bit 5 oc1a, output compare match a output: the pb5 pin can ser v e as an external output for the timer/counter1 output compare a. the pin has to be configured as an output (ddb5 set (one)) to ser v e this function. the oc1a pin is also the output pin for the pwm mode timer function. pcint5, pin change interrupt source 5: the pb5 pin can ser v e as an external interrupt source. ? oc2a/pcint4, bit 4 oc2a, output compare match output: the pb4 pin can ser v e as an external output for the timer/counter2 output compare. the pin has to be configured as an output (ddb4 set (one)) to ser v e this function. the oc2a pin is also the output pin for the pwm mode timer function. pcint4, pin change interrupt source 4: the pb4 pin can ser v e as an external interrupt source. ? pdo/miso/pcint3 ? port b, bit 3 pdo, spi serial programming data output. during serial program do w nloading, this pin is used as data output line for the atmel at90usb64/128. miso: master data input, sla v e data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input r egardless of the setting of ddb3. when the spi is enabled as a sla v e, the data direction of this pin is controlled by ddb3. when the pin is forced to be an input, the pull- up can still be controlled by the portb3 bit. pcint3, pin change interrupt source 3: the pb3 pin can ser v e as an external interrupt source. ? pdi/mosi/pcint2 ? port b, bit 2 pdi, spi serial programming data input. during serial program do w nloading, this pin is used as data input line for the at90usb64/128. mosi: spi master data output, sla v e data input for spi channel. when the spi is enabled as a sla v e, this pin is configured as an input regardless of the setting of ddb2. when the spi is enabled as a master, the data direction of this pi n is controlled by ddb2. when the pin is forced to be an input, the pull-up can st ill be controlled by the portb2 bit. pcint2, pin change interrupt source 2: the pb2 pin can ser v e as an external interrupt source. ? sck/pcint1 ? port b, bit 1 sck: master clock output, sla v e clock input pin for spi channel. when the spi is enabled as a sla v e, this pin is configured as an input regardl ess of the setting of ddb1. when the spi0 is enabled as a master, the data direction of this pi n is controlled by ddb1. when the pin is forced to be an input, the pull-up can st ill be controlled by the portb1 bit. 81 7593l?avr?09/12 at90usb64/128 pcint1, pin change interrupt source 1: the pb1 pin can ser v e as an external interrupt source. ?ss /pcint0 ? port b, bit 0 ss : sla v e port select input. when the spi is enabled as a sla v e, this pin is configured as an input regardless of the setting of ddb0. as a sla v e, the spi is acti v ated w hen this pin is dri v en lo w . when the spi is enabled as a master, the data dire ction of this pin is controlled by ddb0. when the pin is forced to be an input, the pull-up can still be controlled by the portb0 bit. table 11-7 and table 11-8 relate the alternate functions of port b to the o v erriding signals sho w n in figure 11-5 on page 76 . spi mstr input and spi sl ave output constitute the miso signal, w hile mosi is di v ided into spi mstr output and spi slave input. pcint0, pin change interrupt source 0: the pb0 pin can ser v e as an external interrupt source.. table 11-7. o v erriding signals for alternate functions in pb7..pb4. signal name pb7/pcint7/oc0a/ oc1c pb6/pcint6/oc1b pb5/pcint5/oc1a pb4/pcint4/oc2a puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe oc0/oc1c enable oc1b enable oc1a enable oc2a enable pvov oc0/oc1c oc1b oc1a oc2a dieoe pcint7 ? pcie0 pcint6 ? pcie 0 pcint5 ? pcie0 pcint4 ? pcie0 dieov 1 1 1 1 di pcint7 input pcint6 input pcint5 input pcint4 input aio ? ? ? ? table 11-8. o v erriding signals for alternate functions in pb3..pb0. signal name pb3/pd0/pcint3/ miso pb2/pdi/pcint2/ mosi pb1/pcint1/ sck pb0/pcint0/ ss puoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr puov portb3 ? pud portb2 ? pud portb1 ? pud portb0 ? pud ddoe spe ? mstr spe ? mstr spe ? mstr spe ? mstr ddov 0 0 0 0 pvoe spe ? mstr spe ? mstr spe ? mstr 0 pvov spi slave output spi mstr output sck output 0 dieoe pcint3 ? pcie0 pcint2 ? pcie 0 pcint1 ? pcie0 pcint0 ? pcie0 dieov 1 1 1 1 di spi mstr input pcint3 input spi slave input pcint2 input sck input pcint1 input spi ss pcint0 input aio ? ? ? ? 82 7593l?avr?09/12 at90usb64/128 11.3.4 alternate functions of port c the port c alternate function is as follo w s: table 11-10 and table 11-11 on page 83 relate the alternate functions of port c to the o v erriding signals sho w n in figure 11-5 on page 76 . table 11-9. port c pins alternate functions. port pin alternate function pc7 a15/ic.3/clko(external memory interface address bit 15 or input capture timer 3 or clko (di v ided system clock) pc6 a14/oc.3a(external memory interface address bit 14 or output compare and pwm output a for timer/counter3) pc5 a13/oc.3b(external memory interface address bit 13 or output compare and pwm output b for timer/counter3) pc4 a12/oc.3c(external memory interface address bit 12 or output compare and pwm output c for timer/counter3) pc3 a11/t.3(external memory interface ad dress bit 11or timer/counter3 clok input) pc2 a10(external memory interface address bit 10) pc1 a9(external memory interface address bit 9) pc0 a8(external memory interface address bit 8) table 11-10. o v erriding signals for alternate functions in pc7..pc4. signal name pc7/a15/ic.3/clko pc6/a14/o c.3a pc5/a13/oc.3b pc4/a12/oc.3c puoe sre ? (xmm<1) sre ? (xmm<2)|oc3a enable sre ? (xmm<3)|oc3b enable sre ? (xmm<4)|oc3c enable puov0 000 ddoe sre ? (xmm<1) sre ? (xmm<2) sre ? (xmm<3) sre ? (xmm<4) ddov 1 1 1 1 pvoe sre ? (xmm<1) sre ? (xmm<2) sre ? (xmm<3) sre ? (xmm<4) pvov a15 if (sre.xmm<2) then a14 else oc3a if (sre.xmm<2) then a13 else oc3b if (sre.xmm<2) then a12 else oc3c dieoe0 000 dieov0 000 di icp3 input ? ? ? aio? ??? 83 7593l?avr?09/12 at90usb64/128 11.3.5 alternate functions of port d the port d pins w ith alternate functions are sho w n in table 11-12 . the alternate pin configuration is as follo w s: ? t0 ? port d, bit 7 t0, timer/counter0 counter source. ? t1 ? port d, bit 6 t1, timer/counter1 counter source. ? xck1 ? port d, bit 5 xck1, usart1 external cloc k. the data direction re gister (ddd5) controls w hether the clock is output (ddd5 set) or input (ddd5 cleared). the xck1 pin is acti v e only w hen the usart1 operates in synchronous mode. table 11-11. o v erriding signals for alternate functions in pc3..pc0. signal name pc3/a11/t.3 pc2/a10 pc1/a9 pc0/a8 puoe sre ? (xmm<5) sre ? (xmm<6) sre ? (xmm<7) sre ? (xmm<7) puov 0 0 0 0 ddoe sre ? (xmm<5) sre ? (xmm<6) sre ? (xmm<7) sre ? (xmm<7) ddov 1 1 1 1 pvoe sre ? (xmm<5) sre ? (xmm<6) sre ? (xmm<7) sre ? (xmm<7) pvov a11 a10 a9 a8 dieoe 0 0 0 0 dieov 0 0 0 0 di t3 input ? ? ? aio ? ? ? ? table 11-12. port d pins alternate functions. port pin alternate function pd7 t0 (timer/counter0 clock input) pd6 t1 (timer/counter1 clock input) pd5 xck1 (usart1 external clock input/output) pd4 icp1 (timer/counter1 input capture trigger) pd3 int3 /txd1 (external interrupt3 input or usart1 transmit pin) pd2 int2/rxd1 (external interrupt2 input or usart1 recei v e pin) pd1 int1 /sda/oc2b (external interrup t1 input or twi serial da ta or output compare for timer/counter2) pd0 int0 /scl/oc0b (external interrupt0 input or tw i serial clock or output compare for timer/counter0) 84 7593l?avr?09/12 at90usb64/128 ? icp1 ? port d, bit 4 icp1 ? input capture pin 1: the pd4 pin can ac t as an input capture pin for timer/counter1. ?int3 /txd1 ? port d, bit 3 int3, external interrupt source 3: the pd3 pin can ser v e as an external interrupt source to the mcu. txd1, transmit data (data output pin for t he usart1). when the usart1 transmitter is enabled, this pin is configured as an output regardless of the v alue of ddd3. ?int2 /rxd1 ? port d, bit 2 int2, external interrupt source 2. the pd2 pin can ser v e as an external interrupt source to the mcu. rxd1, recei v e data (data input pin for the usart1). when the usart1 recei v er is enabled this pin is configured as an input regardless of the v alue of ddd2. when the usart forces this pin to be an input, the pull-up can still be controlled by the portd2 bit. ?int1 /sda/oc2b ? port d, bit 1 int1, external interrupt source 1. the pd1 pin can ser v e as an external interrupt source to the mcu. sda, 2- w ire serial interface data: when the twen bit in twcr is set (one) to enable the 2- w ire serial interface, pin pd1 is disconnected from t he port and becomes the serial data i/o pin for the 2- w ire serial interface. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is dri v en by an open drain dri v er w ith sle w -rate limitation. ?int0 /scl/oc0b ? port d, bit 0 int0, external interrupt source 0. the pd0 pin can ser v e as an external interrupt source to the mcu. scl, 2- w ire serial interface clock: when the twen bit in twcr is set (one) to enable the 2- w ire serial interface, pin pd0 is disconnected from the port and becomes the serial clock i/o pin for the 2- w ire serial interface. in this mode, there is a spike filter on the pin to suppress spikes shorter than 50ns on the input signal, and the pin is dri v en by an open drain dri v er w ith sle w -rate limitation. table 11-13 on page 85 and table 11-14 on page 85 relates the alternate functions of port d to the o v erriding signals sho w n in figure 11-5 on page 76 . 85 7593l?avr?09/12 at90usb64/128 note: 1. when enabled, the 2- w ire serial interface enables sle w -rate controls on the output pins pd0 and pd1. this is not sho w n in this table. in addition, spike filters are connected bet w een the aio outputs sho w n in the port figure and the digital logic of the twi module. table 11-13. o v erriding signals for alternate functions pd7..pd4. signal name pd7/t0 pd6/t1 pd5/xck1 pd4/icp1 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 xck1 output enable 0 ddov 0 0 1 0 pvoe 0 0 xck1 output enable 0 pvov 0 0 xck1 output 0 dieoe 0 0 0 0 dieov 0 0 0 0 di t0 input t1 input xck1 input icp1 input aio ? ? ? ? table 11-14. o v erriding signals for alternate functions in pd3..pd0 (1) . signal name pd3/int3 /txd1 pd2/int2/rxd1 pd1/int1/sda/oc2 b pd0/int0/scl/oc0 b puoe txen1 rxen1 twen twen puov 0 portd2 ? pud portd1 ? pud portd0 ? pud ddoe txen1 rxen1 twen twen ddov 1 0 sda_out scl_out pvoe txen1 0 twen | oc2b enable twen | oc0b enable pvov txd1 0 oc2b oc0b dieoe int3 enable int2 enable int1 enable int0 enable dieov 1 1 1 1 di int3 input int2 input/rxd1 int1 input int0 input aio ? ? sda input scl input 86 7593l?avr?09/12 at90usb64/128 11.3.6 alternate functions of port e the port e pins w ith alternate functions are sho w n in table 11-15 . ? int7/ain.1/uvcon ? port e, bit 7 int7, external interrupt source 7: the pe7 pin can ser v e as an external interrupt source. ain1 ? analog comparator negati v e input. this pin is directly connected to the negati v e input of the analog comparator. uvcon - when using usb host mode, this pin allo w s to control an external vbus generator (acti v e high). ? int6/ain.0 ? port e, bit 6 int6, external interrupt source 6: the pe6 pin can ser v e as an external interrupt source. ain0 ? analog comparator negati v e input. this pin is directly connected to the negati v e input of the analog comparator. ? int5/tosc2 ? port e, bit 5 int5, external interrupt source 5: the pe5 pin can ser v e as an external interrupt source. tosc2, timer/counter2 oscillator pin1. when th e as2 bit in assr is set to enable asynchro- nous clocking of timer/counter2, pin pe5 is disconnected from the port, and becomes the ouput of the in v erting oscillator amplifier. in this mode, a crystal is connected to this pin, and the pin can not be used as an i/o pin. ? int4/tosc1 ? port e, bit 4 int4, external interrupt source 4: the pe4 pin can ser v e as an external interrupt source. tosc1, timer/counter2 oscillator pin2. when th e as2 bit in assr is set to enable asynchro- nous clocking of timer/counter2, pin pe4 is disconnected from the port, and becomes the input of the in v erting oscillator amplifier. in this mode, a crystal is connected to this pin, and the pin can not be used as an i/o pin. ? uid ? port e, bit 3 id pin of the usb bus. table 11-15. port e pins alternate functions. port pin alter nate function pe7 int7/ain.1/uvcon (external interrup t 7 input, analog comparator positi v e input or vbus control) pe6 int6/ain.0 (external interrupt 6 input or analog comparator positi v e input) pe5 int5/tosc2 (external interrupt 5 inpu t or rtc oscillator timer/counter2)) pe4 int4/tosc2 (external interrupt4 in put or rtc oscillator timer/counter2) pe3 uid pe2 ale/hwb (address latch to extenal memory or hard w are bootloader acti v ation) pe1 rd (read strobe to external memory) pe0 wr (write strobe to external memory) 87 7593l?avr?09/12 at90usb64/128 ? ale/hwb ? port e, bit 2 ale is the external data memory address latch enable. hwb allo w s to execute the boot loader section after reset w hen tied to ground during external reset pulse. the hwb mode of this pin is acti v e only w hen the hwbe fuse is enable. ?rd ? port e, bit 1 rd is the external data memory read control enable. ?wr ? port e, bit 0 wr is the external data memory w rite control enable. table 11-16. o v erriding signals for alternate functions pe7..pe4. signal name pe7/int7/ain.1/ uvcon pe6/int6/ain.0 pe5/i nt5/tosc1 pe4/int4/tosc2 puoe 0 0 0 0 puov 0 0 0 0 ddoe uvcone 0 0 0 ddov uvcone 0 0 0 pvoe uvcone 0 0 0 pvov uvcon 0 0 0 dieoe int7 enable int6 enabl e int5 enable int4 enable dieov 1 1 1 1 di int7 input int6 input int5 input int4 input aio ain1 input ain0 input ? ? table 11-17. o v erriding signals for alternate functions in pe3..pe0. signal name pe3/uid pe2/ale/hwb pe1/rd pe0/wr puoe uide 0 sre sre puov 1 0 0 0 ddoe uide sre sre sre ddov 0 1 1 0 pvoe 0 sre sre sre pvov 0 ale rd wr dieoe uide 0 0 0 dieov 1 0 0 1 di uid hwb ? ? pe0 0 0 0 0 aio ? ? ? ? 88 7593l?avr?09/12 at90usb64/128 11.3.7 alternate functions of port f the port f has an alternate function as analog input for the adc as sho w n in table 11-18 . if some port f pins are configured as outputs, it is essential that these do not s w itch w hen a con- v ersion is in progress. this might corrupt the result of the con v ersion. if the jtag interface is enabled, the pull-up resistors on pins pf7(tdi), pf5(tms), and pf4(tck) w ill be acti v ated e v en if a reset occurs. ? tdi, adc7 ? port f, bit 7 adc7, analog to digital con v erter, channel 7 . tdi, jtag test data in: serial input data to be shifted in to the instruction register or data reg- ister (scan chains). when the jtag interface is enabled, this pin can not be used as an i/o pin. ? tdo, adc6 ? port f, bit 6 adc6, analog to digital con v erter, channel 6 . tdo, jtag test data out: serial output data from instruction register or data register. when the jtag interface is enabled, this pin can not be used as an i/o pin. the tdo pin is tri-stated unless tap states that shift out data are entered. ? tms, adc5 ? port f, bit 5 adc5, analog to digital con v erter, channel 5 . tms, jtag test mode select: this pin is used for na v igating through the tap-controller state machine. when the jtag interface is enabled, this pin can not be used as an i/o pin. ? tck, adc4 ? port f, bit 4 adc4, analog to digital con v erter, channel 4 . tck, jtag test clock: jtag operation is synch ronous to tck. when the jtag interface is enabled, this pin can not be used as an i/o pin. ? adc3 ? adc0 ? port f, bit 3..0 analog to digital con v erter, channel 3..0. table 11-18. port f pins alternate functions. port pin alternate function pf7 adc7/tdi (adc input channel 7 or jtag test data input) pf6 adc6/tdo (adc input channel 6 or jtag test data output) pf5 adc5/tms (adc input channel 5 or jtag test mode select) pf4 adc4/tck (adc input channel 4 or jtag test clock) pf3 adc3 (adc input channel 3) pf2 adc2 (adc input channel 2) pf1 adc1 (adc input channel 1) pf0 adc0 (adc input channel 0) 89 7593l?avr?09/12 at90usb64/128 11.4 register description for i/o-ports 11.4.1 porta ? port a data register table 11-19. o v erriding signals for alternate functions in pf7..pf4. signal name pf7/adc7 /tdi pf6/adc6/tdo pf5/adc5/tms pf4/adc4/tck puoe jtagen jtagen jtagen jtagen puov 1 0 1 1 d d o e j tag e n j tag e n j tag e n j tag e n ddov 0 shift_ir + shift_dr 00 pvoe 0 jtagen 0 0 pvov 0 tdo 0 0 d i e o e j tag e n j tag e n j tag e n j tag e n dieov 0 0 0 0 di ? ? ? ? aio tdi/adc7 input adc6 input tms/adc5 input tck/adc4 input table 11-20. o v erriding signals for alternate functions in pf3..pf0. signal name pf3/adc3 pf 2/adc2 pf1/adc1 pf0/adc0 puoe 0 0 0 0 puov 0 0 0 0 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 0 0 0 pvov 0 0 0 0 dieoe 0 0 0 0 dieov 0 0 0 0 di ? ? ? ? aio adc3 input adc2 inpu t adc1 input adc0 input bit 76543210 porta7 porta6 porta5 porta4 porta3 porta2 porta1 porta0 porta read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 90 7593l?avr?09/12 at90usb64/128 11.4.2 ddra ? port a data direction register 11.4.3 pina ? port a input pins address 11.4.4 portb ? port b data register 11.4.5 ddrb ? port b data direction register 11.4.6 pinb ? port b input pins address 11.4.7 portc ? port c data register 11.4.8 ddrc ? port c data direction register 11.4.9 pinc ? port c input pins address 11.4.10 portd ? port d data register bit 76543210 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 pina7 pina6 pina5 pina4 pina 3 pina2 pina1 pina0 pina read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 portc read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 pinc read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 91 7593l?avr?09/12 at90usb64/128 11.4.11 ddrd ? port d data direction register 11.4.12 pind ? port d input pins address 11.4.13 porte ? port e data register 11.4.14 ddre ? port e data direction register 11.4.15 pine ? port e input pins address 11.4.16 portf ? port f data register 11.4.17 ddrf ? port f data direction register 11.4.18 pinf ? port f input pins address bit 76543210 ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 pind read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 porte7 porte6 porte5 porte4 porte3 porte2 porte1 porte0 porte read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 ddre read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 pine read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 portf read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 ddrf read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 pinf read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue n/a n/a n/a n/a n/a n/a n/a n/a 92 7593l?avr?09/12 at90usb64/128 12. external interrupts the external interrupts are triggered by the int7:0 pin or any of the pcint7..0 pins. obser v e that, if enabled, the interrupts w ill trigger e v en if the int7:0 or pcint7..0 pins are configured as outputs. this feature pro v ides a w ay of generating a soft w are interrupt. the pin change interrupt pci0 w ill trigger if any enabled pcint7 :0 pin toggles. pcmsk0 regis- ter control w hich pins contribute to the pin change interrupts. pin change interrupts on pcint7 ..0 are detected asynchronously. this imp lies that these interrupts can be used for w aking the part also from sleep modes other than idle mode. the external interrupts can be triggered by a falling or rising edge or a lo w le v el. this is set up as indicated in the specification for the external interrupt control registers ? eicra (int3:0) and eicrb (int7:4). when the external interrupt is enabled and is configured as le v el triggered, the interrupt w ill trigger as long as the pin is held lo w . note that recognition of falling or rising edge interrupts on int7:4 requires the presence of an i/o clock, described in ?system clock and clock options? on page 40 . lo w le v el interrupts and the edge interrupt on int3:0 are detected asynchronously. this implies that these interrupts can be used for w aking the part also from sleep modes other than idle mode. the i/o clock is halted in all sleep modes except idle mode. note that if a le v el triggered interrupt is used for w ake-up from po w er-do w n, the required le v el must be held long enough for the mcu to complete the w ake-up to trigger the le v el interrupt. if the le v el disappears before the end of the start-up time, the mcu w ill still w ake up, but no inter- rupt w ill be generated. the start-up time is defined by the sut and cksel fuses as described in ?system clock and clock options? on page 40 . 12.0.1 eicra ? external interrupt control register a the external interrupt control register a contains control bits for interrupt sense control. ? bits 7..0 ? isc31, isc30 ? isc00, isc00: external interrupt 3 - 0 sense control bits the external interrupts 3 - 0 are acti v ated by the external pins int3:0 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the le v el and edges on the external pins that acti v ate the interrupts are defined in table 12-1 . edges on int3..int0 are registered asynchro- nously. pulses on int3:0 pins w ider than the minimum pulse w idth gi v en in table 12-2 w ill generate an interrupt. shorter pulses are not guaranteed to generate an interrupt. if lo w le v el interrupt is selected, the lo w le v el must be held until the completion of the currently executing instruction to generate an interrupt. if enabled, a le v el triggered interrupt w ill generate an inter- rupt request as long as the pin is held lo w . when changing the iscn bit, an interrupt can occur. therefore, it is recommended to first disable intn by clearing its interrupt enable bit in the eimsk register. then, the iscn bit can be changed. finally, the intn interrupt flag should be cleared by w riting a logical one to its interrupt flag bit (intfn) in the eifr register before the interrupt is re-enabled. bit 76543210 isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 eicra read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 93 7593l?avr?09/12 at90usb64/128 note: 1. n = 3, 2, 1or 0. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. other w ise an interrupt can occur w hen the bits are changed. 12.0.2 eicrb ? external interrupt control register b ? bits 7..0 ? isc71, isc70 - isc41, isc40: external interrupt 7 - 4 sense control bits the external interrupts 7 - 4 are acti v ated by the external pins int7:4 if the sreg i-flag and the corresponding interrupt mask in the eimsk is set. the le v el and edges on the external pins that acti v ate the interrupts are defined in table 12-3 . the v alue on the int7:4 pins are sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period w ill generate an interrupt. shorter pulses are not guaranteed to generate an inter- rupt. obser v e that cpu clock frequency can be lo w er than the xtal frequency if the xtal di v ider is enabled. if lo w le v el interrupt is selected, the lo w le v el must be held until the comple- tion of the currently executing instructi on to generate an interrupt. if enabled, a le v el triggered interrupt w ill generate an interrup t request as long as the pin is held lo w . note: 1. n = 7, 6, 5 or 4. when changing the iscn1/iscn0 bits, the interrupt must be disabled by clearing its interrupt enable bit in the eimsk register. other w ise an interrupt can occur w hen the bits are changed. 12.0.3 eimsk ? external interrupt mask register table 12-1. interrupt sense control (1) . iscn1 iscn0 description 00the lo w le v el of intn generates an interrupt request. 0 1 any edge of intn generates asynchronously an interrupt request. 1 0 the falling edge of intn generates asynchronously an interrupt request. 1 1 the rising edge of intn generates asynchronously an interrupt request. table 12-2. asynchronous external interrupt characteristics. symbol parameter condition min. typ. max. units t int minimum pulse w idth for asynchronous external interrupt 50 ns bit 76543210 isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 eicrb read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 table 12-3. interrupt sense control (1) . iscn1 iscn0 description 00the lo w le v el of intn generates an interrupt request. 0 1 any logical change on intn generates an interrupt request. 1 0 the falling edge bet w een t w o samples of intn generates an interrupt request. 1 1 the rising edge bet w een t w o samples of intn generates an interrupt request. bit 76543210 int7 int6 int5 int4 int3 int2 int1 iint0 eimsk read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 94 7593l?avr?09/12 at90usb64/128 ? bits 7..0 ? int7 ? int0: external interrupt request 7 - 0 enable when an int7 ? int0 bit is w ritten to one and the i-bit in the status register (sreg) is set (one), the corresponding external pin interrupt is enabled. the interrupt sense control bits in the external interrupt control registers ? eicra and eicrb ? defines w hether the external inter- rupt is acti v ated on rising or falling edge or le v el sensed. acti v ity on any of these pins w ill trigger an interrupt request e v en if the pin is enabled as an output. this pro v ides a w ay of generating a soft w are interrupt. 12.0.4 eifr ? external interrupt flag register ? bits 7..0 ? intf7 - intf0: external interrupt flags 7 - 0 when an edge or logic change on the int7:0 pin triggers an interrupt request, intf7:0 becomes set (one). if the i-bit in sreg and the corresponding interrupt enable bit, int7:0 in eimsk, are set (one), the mcu w ill jump to the interrupt v ector. the flag is cleared w hen the interrupt routine is executed. alternati v ely, the flag can be cleared by w riting a logical one to it. these flags are al w ays cleared w hen int7:0 are configured as le v el interrupt. note that w hen entering sleep mode w ith the int3:0 interrupts disabled, the input buffers on these pins w ill be disabled. this may cause a logic change in internal signals w hich w ill set the intf3:0 flags. see ?digital input enable and sleep modes? on page 75 for more information. 12.0.5 pcicr ? pin change interrupt control register ? bit 0 ? pcie0: pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 0 is enabled. any change on any enabled pcint7..0 pin w ill cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci0 interrupt vector. pcint7..0 pins are enabled indi v idually by the pcmsk0 register. 12.0.6 pcifr ? pin change interrupt flag register ? bit 0 ? pcif0: pin change interrupt flag 0 when a logic change on any pcint7..0 pin triggers an interrupt request, pcif0 becomes set (one). if the i-bit in sreg and the pcie0 bit in eimsk are set (one), the mcu w ill jump to the corresponding interrupt vector. the flag is cleared w hen the interrupt routine is executed. alter- nati v ely, the flag can be cleared by w riting a logical one to it. bit 76543210 intf7 intf6 intf5 intf4 intf3 intf2 intf1 iintf0 eifr read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ? ? ? ? ? pcie0 pcicr read/ w riterrrrrrrr/w initial v alue00000000 bit 76543210 ? ? ? ? ?pcif0pcifr read/ w riterrrrrrrr/w initial v alue00000000 95 7593l?avr?09/12 at90usb64/128 12.0.7 pcmsk0 ? pin change mask register 0 ? bit 7..0 ? pcint7..0: pin change enable mask 7..0 each pcint7..0 bit selects w hether pin change interrupt is enabled on the corresponding i/o pin. if pcint7..0 is set and the pcie0 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint7..0 is cleared, pin change interrupt on the corresponding i/o pin is disabled. bit 76543210 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 96 7593l?avr?09/12 at90usb64/128 13. timer/counter0, timer/counter1 , and timer/counter3 prescalers timer/counter0, 1, and 3 share the same prescaler module, but the timer/counters can ha v e different prescaler settings. the description belo w applies to all timer/coun ters. tn is used as a general name, n = 0, 1 or 3. 13.1 internal clock source the timer/counter can be clocked directly by the system clock (by setting the csn2:0 = 1). this pro v ides the fastest operation, w ith a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternati v ely, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 13.2 prescaler reset the prescaler is free running, that is, operates independently of the clock select logic of the timer/counter, and it is shared by the timer/counter tn. since the prescaler is not affected by the timer/counter?s clock select, the state of the prescaler w ill ha v e implications for situations w here a prescaled clock is used. one exam ple of prescaling artefacts occurs w hen the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from w hen the timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles, w here n equals the prescaler di v isor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing the timer/counter to program execu- tion. ho w e v er, care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a prescaler reset w ill affect the prescaler period for all timer/co unters it is connected to. 13.3 external clock source an external clock source applied to the tn pin can be used as timer/counter clock (clk tn ). the tn pin is sampled once e v ery system clock cycle by the pin sy nchronization logic. the synchro- nized (sampled) signal is then passed through the edge detector. figure 13-1 sho w s a functional equi v alent block diagram of the tn synchronization and edge detector logic. the registers are clocked at the positi v e edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk tn pulse for each positi v e (csn2:0 = 7) or negati v e (csn2:0 = 6) edge it detects. figure 13-1. tn/t0 pin sampling. the synchronization and e dge detector logic introduces a de lay of 2.5 to 3.5 system clock cycles from an edge has been applied to the tn pin to the counter is updated. enabling and disabling of the clock input must be done w hen tn has been stable for at least one system clock cycle, other w ise it is a risk that a false timer/counter clock pulse is generated. tn_ s ync (to clock s elect logic) edge detector synchroniz a tion dq dq le dq tn clk i/o 97 7593l?avr?09/12 at90usb64/128 each half period of the external clock applie d must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to ha v e less than half the sys- tem clock frequency (f extclk < f clk_i/o /2) gi v en a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (nyquist sampling theorem). ho w e v er, due to v ariation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 13-2. prescaler for synchronous timer/counters 13.4 gtccr ? general timer/counter control register ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one acti v ates the timer/counter synchronization mode. in this mode, the v alue that is w ritten to the psrasy and psrsync bits is kept, hence keeping the correspond- ing prescaler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be configured to the same v alue w ithout the risk of one of them ad v ancing during configuration. when the tsm bit is w ritten to zero, the psrasy and psrsync bits are cleared by hard w are, and the timer/counters start counting simultaneously. ? bit 0 ? psrsync: prescaler reset for synchronous timer/counters when this bit is one, timer/counter0 and timer/counter1 and timer/counter3 prescaler w ill be reset. this bit is normally cleared immediately by hard w are, except if the tsm bit is set. note that timer/counter0, timer/counter1 and timer/counter3 share the same prescaler and a reset of this prescaler w ill affect all timers. psr10 cle a r tn tn clk i/o synchroniz a tion synchroniz a tion timer/countern clock source clk tn timer/countern clock source clk tn csn0 csn1 csn2 csn0 csn1 csn2 bit 7 6 5 4 3 2 1 0 tsm ? ? ? ? ? psrasy psrsync gtccr read/ w rite r/w r r r r r r/w r/w initial v alue 0 0 0 0 0 0 0 0 98 7593l?avr?09/12 at90usb64/128 14. 8-bit timer/counter0 with pwm timer/counter0 is a general purpose 8-bit timer/counter module, w ith t w o independent output compare units, and w ith pwm support. it allo w s accurate program execution timing (e v ent man- agement) and w a v e generation. the main features are: ? two independent output compare units ? double buffered output compare registers ? clear timer on compare match (auto reload) ? glitch free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? three independent interrupt sources (tov0, ocf0a, and ocf0b) 14.1 overview a simplified block diagram of the 8-bit timer/counter is sho w n in figure 14-1 . for the actual placement of i/o pins, refer to ?pinout atmel at90usb64/128-tqfp.? on page 3 . cpu accessi- ble i/o registers, including i/ o bits and i/o pins, are sho w n in bold. the de v ice-specific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 108 . figure 14-1. 8-bit timer/counter block diagram. 14.1.1 registers the timer/counter (tcnt0) and output compare registers (ocr0a and ocr0b) are 8-bit registers. interrupt request (abbre v iated to int.req. in the figure) signals are all v isible in the timer interrupt flag register (tifr0). all interrupts are indi v idually masked w ith the timer inter- rupt mask register (timsk0). tifr0 and timsk0 are not sho w n in the figure. the timer/counter can be clocked internally, v ia the prescaler, or by an external clock source on the t0 pin. the clock select logic block controls w hich clock source and edge the timer/counter uses to increment (or decrement) its v alue. the timer/counter is inacti v e w hen no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t0 ). clock s elect timer/co u nter data b u s ocrna ocrnb = = tcntn w a veform gener a tion w a veform gener a tion ocna ocnb = fixed top v a l u e control logic = 0 top bottom co u nt cle a r direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb tn edge detector (from pre s c a ler) clk tn 99 7593l?avr?09/12 at90usb64/128 the double buffered output compare registers (ocr0a and ocr0b) are compared w ith the timer/counter v alue at all times. the result of the compare can be used by the wa v eform gen- erator to generate a pwm or v ariable frequency output on the output compare pins (oc0a and oc0b). see ?output compare unit? on page 100. for details. the compare match e v ent w ill also set the compare flag (ocf0a or ocf0b) w hich can be used to generate an output compare interrupt request. 14.1.2 definitions many register and bit references in this section are w ritten in general form. a lo w er case ?n? replaces the timer/counter number, in this case 0. a lo w er case ?x? replaces the output com- pare unit, in this case compar e unit a or compare unit b. ho w e v er, w hen using the register or bit defines in a program, the precise form must be used, that is, tcnt0 for accessing timer/counter0 counter v alue and so on. the definitions in the table belo w are also used extensi v ely throughout the document. 14.2 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic w hich is controlled by the clock select (cs02:0) bits located in the timer/counter control register (tccr0b). for details on clock sources and pres- caler, see ?timer/counter0, timer/counter1, and timer/counter3 prescalers? on page 96 . 14.3 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 14-2 sho w s a block diagram of the counter and its surroundings. figure 14-2. counter unit block diagram. bottom the counter reaches the bottom w hen it becomes 0x00. max the counter reaches its maximum w hen it becomes 0xff (decimal 255). top the counter reaches the top w hen it becomes equal to the highest v alue in the count sequence. the top v alue can be assigned to be the fixed v alue 0xff (max) or the v alue stored in the ocr0a register. the assignment is dependent on the mode of operation. data b u s tcntn control logic count tovn (int.re q .) clock select top tn edge detector (from prescaler) clk tn bottom direction clear 100 7593l?avr?09/12 at90usb64/128 signal description (internal signals): count increment or decrement tcnt0 by 1. direction select bet w een increment and decrement. clear clear tcnt0 (set all bits to zero). clk t n timer/counter clock, referred to as clk t0 in the follo w ing. top signalize that tcnt0 has reached maximum v alue. bottom signalize that tcnt0 has reached minimum v alue (zero). depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bits (cs02:0). w hen no clock source is selected (cs02:0 = 0) the timer is stopped. ho w e v er, the tcnt0 v alue can be accessed by the cpu, regardless of w hether clk t0 is present or not. a cpu w rite o v errides (has priority o v er) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a) and the wgm02 bit located in the timer/counter control register b (tccr0b). there are close connections bet w een ho w the counter beha v es (counts) and ho w w a v eforms are generated on the output compare outputs oc0a and oc0b. for more details about ad v anced counting sequences and w a v eform generation, see ?modes of operation? on page 103 . the timer/counter o v erflo w flag (tov0) is set according to the mode of operation selected by the wgm02:0 bits. tov0 can be used for generating a cpu interrupt. 14.4 output compare unit the 8-bit comparator continuously compares tcnt0 w ith the output compare registers (ocr0a and ocr0b). whene v er tcnt0 equals ocr0a or ocr0b, the comparator signals a match. a match w ill set the output compare flag (ocf0a or ocf0b) at the next timer clock cycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared w hen the interrupt is exe- cuted. alternati v ely, the flag can be cleared by soft w are by w riting a logical one to its i/o bit location. the wa v eform generator uses the match signal to generate an output according to operating mode set by the wgm02:0 bits and compare output mode (com0x1:0) bits. the maximum and bottom signals are used by the wa v eform generator for handling the special cases of the extreme v alues in some modes of operation ( ?modes of operation? on page 103 ). figure 14-3 on page 101 sho w s a block diagram of the output compare unit. 101 7593l?avr?09/12 at90usb64/128 figure 14-3. output compare unit, block diagram. the ocr0x registers are double buffered w hen using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the dou- ble buffering is disabled. the double buffering synchronizes the update of the ocr0x compare registers to either top or bottom of the counting sequence. the synchronization pre v ents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr0x buffer register, and if double buffering is dis- abled the cpu w ill access the ocr0x directly. 14.4.1 force output compare in non-pwm w a v eform generation modes, the match output of the comparator can be forced by w riting a one to the force output compare (foc0x) bit. forcing compare match w ill not set the ocf0x flag or reload/clear the timer, but the oc0x pin w ill be updated as if a real compare match had occurred (the com0x1:0 bits settings define w hether the oc0x pin is set, cleared or toggled). 14.4.2 compare match blocking by tcnt0 write all cpu w rite operations to the tcnt0 register w ill block any compare matc h that occur in the next timer clock cycle, e v en w hen the timer is stopped. this feature allo w s ocr0x to be initial- ized to the same v alue as tcnt0 w ithout triggering an interrupt w hen the timer/counter clock is enabled. 14.4.3 using the output compare unit since w riting tcnt0 in any mode of operation w ill block all compare matches for one timer clock cycle, there are risks in v ol v ed w hen changing tcnt0 w hen using the output compare unit, independently of w hether the timer/counter is running or not. if the v alue w ritten to tcnt0 equals the ocr0x v alue, the compare match w ill be missed, resulting in incorrect w a v eform generation. similarly, do not w rite the tcnt0 v alue equal to bottom w hen the counter is do w n-counting. ocfn x (int.re q .) = ( 8 -bit comparator) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 102 7593l?avr?09/12 at90usb64/128 the setup of the oc0x should be performed before setting the data direction register for the port pin to output. the easiest w ay of setting the oc0x v alue is to use the force output com- pare (foc0x) strobe bits in normal mode. the oc0x registers keep their v alues e v en w hen changing bet w een wa v eform generation modes. be a w are that the com0x1:0 bits are not double buffered together w ith the compare v alue. changing the com0x1:0 bits w ill take effect immediately. 14.5 compare match output unit the compare output mode (com0x1:0) bits ha v e t w o functions. the wa v eform generator uses the com0x1:0 bits for defining the output compare (oc0x) state at the next compare match. also, the com0x1:0 bits control the oc0x pin output source. figure 14-4 sho w s a simplified schematic of the logic affected by the com0x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are sho w n in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com0x1:0 bits are sho w n. when referring to the oc0x state, the reference is for the internal oc0x register, not the oc0x pin. if a system reset occur, the oc0x register is reset to ?0?. figure 14-4. compare match output unit, schematic. the general i/o port function is o v erridden by the output compare (oc0x) from the wa v eform generator if either of the com0x1:0 bits are set. ho w e v er, the oc0x pin direction (input or out- put) is still controlled by the da ta direction register (ddr) for th e port pin. the data direction register bit for the oc0x pin (ddr_oc0x) mu st be set as output before the oc0x v alue is v isi- ble on the pin. the port o v erride function is independent of the wa v eform generation mode. the design of the output compare pin logic allo w s initialization of the oc0x state before the out- put is enabled. note that some com0x1:0 bit settings are reser v ed for certain modes of operation. see ?8-bit timer/counter register description? on page 108. 14.5.1 compare output mode and waveform generation the wa v eform generator uses the com0x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com0x1:0 = 0 tells the wa v eform generator that no action on the oc0x register is to be performed on the next compare match. for compare output actions in port ddr dq dq ocnx pin ocnx dq w a veform gener a tor comnx1 comnx0 0 1 data b u s focn clk i/o 103 7593l?avr?09/12 at90usb64/128 the non-pwm modes refer to table 14-1 on page 109 . for fast pwm mode, refer to table 14-2 on page 109 , and for phase correct pwm refer to table 14-3 on page 109 . a change of the com0x1:0 bits state w ill ha v e effect at the first compare match after the bits are w ritten. for non-pwm modes, the action can be forced to ha v e immediate effect by using the foc0x strobe bits. 14.6 modes of operation the mode of operation, that is, the beha v ior of the timer/counter and the output compare pins, is defined by the combination of the wa v eform generation mode (wgm02:0) and compare out- put mode (com0x1:0) bits. the compare output mode bits do not affect the counting sequence, w hile the wa v eform generation mode bits do. the com0x1:0 bits control w hether the pwm out- put generated should be in v erted or not (in v erted or non-in v erted pwm). for non-pwm modes the com0x1:0 bits control w hether the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 102. ). for detailed timing information see ?timer/counter timing diagrams? on page 107 . 14.6.1 normal mode the simplest mode of operation is the normal mode (wgm02:0 = 0). in this mode the counting direction is al w ays up (incrementing), and no counter cl ear is performed. the counter simply o v erruns w hen it passes its maximum 8-bit v alue (top = 0xff) and then restarts from the bot- tom (0x00). in normal operation the timer/counter o v erflo w flag (tov0) w ill be set in the same timer clock cycle as the tcnt0 becomes zero. the tov0 flag in this case beha v es like a ninth bit, except that it is only set, not cleared. ho w e v er, combined w ith the timer o v erflo w interrupt that automatically clears the tov0 flag, the timer resolution can be increased by soft w are. there are no special cases to consider in the normal mode, a ne w counter v alue can be w ritten anytime. the output compare unit can be used to generate interrupts at some gi v en time. using the out- put compare to generate w a v eforms in normal mode is not recommended, since this w ill occupy too much of the cpu time. 14.6.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm 02:0 = 2), the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero w hen the counter v alue (tcnt0) matches the ocr0a. the ocr0a defines the top v alue for the counter, hence also its resolution. this mode allo w s greater control of the compare match output frequency. it also simplifies the operation of counting external e v ents. the timing diagram for the ctc mode is sho w n in figure 14-5 on page 104 . the counter v alue (tcnt0) increases until a compare match occurs bet w een tcnt0 and ocr0a, and then coun- ter (tcnt0) is cleared. 104 7593l?avr?09/12 at90usb64/128 figure 14-5. ctc mode, timing diagram. an interrupt can be generated each time the counter v alue reaches the top v alue by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top v alue. ho w e v er, changing top to a v alue close to bottom w hen the counter is run- ning w ith none or a lo w prescaler v alue must be done w ith care since the ctc mode does not ha v e the double buffering feature. if the ne w v alue w ritten to ocr0a is lo w er than the current v alue of tcnt0, the counter w ill miss the compare match. the counter w ill then ha v e to count to its maximum v alue (0xff) and w rap around starting at 0x00 before the compare match can occur. for generating a w a v eform output in ctc mode, the oc0a output can be set to toggle its logical le v el on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a v alue w ill not be v isible on the port pin unless the data direction for the pin is set to output. the w a v eform generated w ill ha v e a maximum frequency of f oc0 = f clk_i/o /2 w hen ocr0a is set to zero (0x00). the w a v eform frequency is defined by the follo w ing equation: the n v ariable represents the prescale factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 14.6.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm02:0 = 3 or 7) pro v ides a high fre- quency pwm w a v eform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to top then restarts from bot- tom. top is defined as 0xff w hen wgm2:0 = 3, and ocr0a w hen wgm2:0 = 7. in non- in v erting compare output mode, the output compare (oc0x) is cleared on the compare match bet w een tcnt0 and ocr0x, and set at bottom. in in v erting compare output mode, the out- put is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be t w ice as high as the phase correct pwm mode that use dual-slope operation. this high frequency makes the fast pwm mode w ell suited for po w er regulation, rectification, and dac applications. high frequency allo w s physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter v alue matches the top v alue. the counter is then cleared at the follo w ing timer clock cycle. the timing diagram for the fast tcntn ocn (toggle) ocnx interrupt flag s et 1 4 period 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = 105 7593l?avr?09/12 at90usb64/128 pwm mode is sho w n in figure 14-6 . the tcnt0 v alue is in the timing diagram sho w n as a his- togram for illustrating the single-slope operation. the diagram includes non-in v erted and in v erted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent com- pare matches bet w een ocr0x and tcnt0. figure 14-6. fast pwm mode, timing diagram. the timer/counter o v erflo w flag (tov0) is set each time the counter reaches top. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare v alue. in fast pwm mode, the compare unit allo w s generation of pwm w a v eforms on the oc0x pins. setting the com0x1:0 bits to t w o w ill produce a non-in v erted pwm and an in v erted pwm output can be generated by setting the com0x1:0 to three: setting the com0a1:0 bits to one allo w s the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not a v ailable for the oc0b pin (see table 14-2 on page 109 ). the actual oc0x v alue w ill only be v isible on the port pin if the data direction for the port pin is set as output. the pwm w a v eform is gener- ated by setting (or clearing) the oc0x register at the compare match bet w een ocr0x and tcnt0, and clearing (or setting) the oc0x regist er at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the follo w ing equation: the n v ariable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme v alues for the ocr0a register represents special cases w hen generating a pwm w a v eform output in the fast pwm mode. if the ocr0a is set equal to bottom, the output w ill be a narro w spike for each max+1 timer clock cycle. setting the ocr0a equal to max w ill result in a constantly high or lo w output (depending on the polarity of the output set by the com0a1:0 bits.) a frequency ( w ith 50% duty cycle) w a v eform output in fast pwm mode can be achie v ed by set- ting oc0x to togg le its logical le v el on each compare match (com0x1:0 = 1). the w a v eform generated w ill ha v e a maximum frequency of f oc0 = f clk_i/o /2 w hen ocr0a is set to zero. this tcntn ocrnx update and tovn interrupt flag s et 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag s et 4 5 6 7 f ocnxpwm f clk_i/o n 256 ? ------------------ = 106 7593l?avr?09/12 at90usb64/128 feature is similar to the oc0a toggle in ctc mode, except the double buffer feature of the out- put compare unit is enabled in the fast pwm mode. 14.6.4 phase correct pwm mode the phase correct pwm mode (wgm02:0 = 1 or 5) pro v ides a high resolution phase correct pwm w a v eform generation option. the phase corr ect pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bot- tom. top is defined as 0xff w hen wgm2:0 = 1, and ocr0a w hen wgm2:0 = 5. in non- in v erting compare output mode, the output compare (oc0x) is cleared on the compare match bet w een tcnt0 and ocr0x w hile up-counting, and set on the compare match w hile do w n- counting. in in v erting output compare mode, the operation is in v erted. the dual-slope operation has lo w er maximum operation frequency than single slope operation. ho w e v er, due to the sym- metric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented until the counter v alue matches top. when the counter reaches top, it c hanges the count direction. the tcnt0 v alue w ill be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is sho w n on figure 14-7 . the tcnt0 v alue is in the timing diagram sho w n as a histogram for illustrating the dual-slope operation. the diagram includes non-in v erted and in v erted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches bet w een ocr0x and tcnt0. figure 14-7. phase correct pwm mode, timing diagram. the timer/counter o v erflo w flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom v alue. in phase correct pwm mode, the compare unit allo w s generation of pwm w a v eforms on the oc0x pins. setting the com0x1:0 bits to t w o w ill produce a non-in v erted pwm. an in v erted pwm output can be generated by setting the com0x1:0 to three: setting the com0a0 bits to tovn interr u pt fl a g set ocnx interr u pt fl a g set 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3 ) ocrnx u pd a te 107 7593l?avr?09/12 at90usb64/128 one allo w s the oc0a pin to toggle on compare matches if the wgm02 bit is set. this option is not a v ailable for the oc0b pin (see table 14-3 on page 109 ). the actual oc0x v alue w ill only be v isible on the port pin if the data direction for the port pin is set as output. the pwm w a v eform is generated by clearing (or setting) the oc0x register at the compare match bet w een ocr0x and tcnt0 w hen the counter increments, and setting (or clearing) the oc0x register at com- pare match bet w een ocr0x and tcnt0 w hen the counter decrements. the pwm frequency for the output w hen using phase correct pwm can be calculated by the follo w ing equation: the n v ariable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme v alues for the ocr0a register represent special cases w hen generating a pwm w a v eform output in the phase correct pwm mode. if the ocr0a is set equal to bottom, the output w ill be continuously lo w and if set equal to max the output w ill be continuously high for non-in v erted pwm mode. for in v erted pwm the output w ill ha v e the opposite logic v alues. at the v ery start of period 2 in figure 14-7 on page 106 ocnx has a transition from high to lo w e v en though there is no compare match. the point of this transition is to guarantee symmetry around bottom. there are t w o cases that gi v e a transition w ithout compare match. ? ocr0a changes its v alue from max, like in figure 14-7 on page 106 . when the ocr0a v alue is max the ocn pin v alue is the same as the result of a do w n-counting compare match. to ensure symmetry around bottom the ocn v alue at max must correspond to the result of an up-counting compare match ? the timer starts counting from a v alue higher than the one in ocr0a, and for that reason misses the compare match and hence the ocn change that w ould ha v e happened on the w ay up 14.7 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore sho w n as a clock enable signal in the follo w ing figures. the figures include information on w hen interrupt flags are set. figure 14-8 contains timing data for basic timer/counter operation. the figure sho w s the count sequence close to the max v alue in all modes other than phase correct pwm mode. figure 14-8. timer/counter timing diagram, no prescaling. figure 14-9 on page 108 sho w s the same timing data, but w ith the prescaler enabled. f ocnxpcpwm f clk_i/o n 510 ? ------------------ = clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 108 7593l?avr?09/12 at90usb64/128 figure 14-9. timer/counter timing diagram, w ith prescaler (f clk_i/o /8). figure 14-10 sho w s the setting of ocf0b in all modes and ocf0a in all modes except ctc mode and pwm mode, w here ocr0a is top. figure 14-10. timer/counter timing diagram, setting of ocf0x, w ith prescaler (f clk_i/o /8). figure 14-11 sho w s the setting of ocf0a and the clearing of tcnt0 in ctc mode and fast pwm mode w here ocr0a is top. figure 14-11. timer/counter timing diagram, clear timer on compare match mode, w ith pres- caler (f clk_i/o /8) 14.8 8-bit timer/counter register description 14.8.1 tccr0a ? timer/counter control register a tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx v a l u e ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) bit 76543210 com0a 1 com0a 0 com0b 1 com0b 0 ?? wgm01 wgm00 tccr0a read/ w rite r/w r/w r/w r/w r r r/w r/w initial v alue 0 0 0 0 0 0 0 0 109 7593l?avr?09/12 at90usb64/128 ? bits 7:6 ? com01a:0: compare match output a mode these bits control the output compare pin (oc0a) beha v ior. if one or both of the com0a1:0 bits are set, the oc0a output o v errides the normal port functionality of the i/o pin it is connected to. ho w e v er, note that the data direction register (ddr) bit corresponding to the oc0a pin must be set in order to enable the output dri v er. when oc0a is connected to the pin, the function of the com0a1:0 bits depends on the wgm02:0 bit setting. table 14-1 sho w s the com0a1:0 bit functionality w hen the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 14-2 sho w s the com0a1:0 bit functionality w hen the wgm01:0 bits are set to fast pwm mode. note: 1. a special case occurs w hen ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 104 for more details. table 14-3 sho w s the com0a1:0 bit functionality w hen the wgm02:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs w hen ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 106 for more details. table 14-1. compare output mode, non-pwm mode. com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 14-2. compare output mode, fast pwm mode (1) . com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port op eration, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 1 0 clear oc0a on compare match, set oc0a at top 1 1 set oc0a on compare match, clear oc0a at top table 14-3. compare output mode, phase correct pwm mode (1) . com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port op eration, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 10 clear oc0a on compare match w hen up-counting. set oc0a on compare match w hen do w n-counting. 11 set oc0a on compare match w hen up-counting. clear oc0a on compare match w hen do w n-counting. 110 7593l?avr?09/12 at90usb64/128 ? bits 5:4 ? com0b1:0: compare match output b mode these bits control the output compare pin (oc0b) beha v ior. if one or both of the com0b1:0 bits are set, the oc0b output o v errides the normal port functionality of the i/o pin it is connected to. ho w e v er, note that the data direction register (ddr) bit corresponding to the oc0b pin must be set in order to enable the output dri v er. when oc0b is connected to the pin, the function of the com0b1:0 bits depends on the wgm02:0 bit setting. table 14-1 sho w s the com0a1:0 bit functionality w hen the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 14-2 sho w s the com0b1:0 bit functionality w hen the wgm02:0 bits are set to fast pwm mode. note: 1. a special case occurs w hen ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 104 for more details. table 14-3 sho w s the com0b1:0 bit functionality w hen the wgm02:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs w hen ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 106 for more details. ? bits 3, 2 ? res: reserved bits these bits are reser v ed bits in the atmel at90usb64/128 and w ill al w ays read as zero. table 14-4. compare output mode, non-pwm mode. com01 com00 description 0 0 normal port operation, oc0b disconnected. 0 1 toggle oc0b on compare match 1 0 clear oc0b on compare match 1 1 set oc0b on compare match table 14-5. compare output mode, fast pwm mode (1) . com01 com00 description 0 0 normal port operation, oc0b disconnected. 01reser v ed. 1 0 clear oc0b on compare match, set oc0b at top. 1 1 set oc0b on compare match, clear oc0b at top. table 14-6. compare output mode, phase correct pwm mode (1) . com0a1 com0a0 description 0 0 normal port operation, oc0b disconnected. 01reser v ed. 10 clear oc0b on compare match w hen up-counting. set oc0b on compare match w hen do w n-counting. 11 set oc0b on compare match w hen up-counting. clear oc0b on compare match w hen do w n-counting. 111 7593l?avr?09/12 at90usb64/128 ? bits 1:0 ? wgm01:0: waveform generation mode combined w ith the wgm02 bit found in the tccr0b register, these bits control the counting sequence of the counter, the source for maximum (top) counter v alue, and w hat type of w a v e- form generation to be used, see table 14-7 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and t w o types of pulse width modulation (pwm) modes (see ?modes of operation? on page 103 ). notes: 1. max = 0xff 2. bottom = 0x00 14.8.2 tccr0b ? timer/counter control register b ? bit 7 ? foc0a: force output compare a the foc0a bit is only acti v e w hen the wgm bits specify a non-pwm mode. ho w e v er, for ensuring compatibility w ith future de v ices, this bit must be set to zero w hen tccr0b is w ritten w hen operating in pwm mode. when w riting a logical one to the foc0a bit, an immediate compare match is forced on the wa v eform generation unit. the oc0a output is changed according to its com0a1:0 bits setting. note that the foc0a bit is implemented as a strobe. therefore it is the v alue present in the com0a1:0 bits that determines the effect of the forced compare. a foc0a strobe w ill not generate any interrupt, nor w ill it clear the timer in ctc mode using ocr0a as top. the foc0a bit is al w ays read as zero. ? bit 6 ? foc0b: force output compare b the foc0b bit is only acti v e w hen the wgm bits specify a non-pwm mode. ho w e v er, for ensuring compatibility w ith future de v ices, this bit must be set to zero w hen tccr0b is w ritten w hen operating in pwm mode. when w riting a logical one to the foc0b bit, an immediate compare match is forced on the wa v eform generation unit. the oc0b output is changed according to its com0b1:0 bits setting. note that the foc0b bit is implemented as a table 14-7. wa v eform generation mode bit description. mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 1 0 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff top max 4 1 0 0 reser v ed ? ? ? 5 1 0 1 pwm, phase correct ocra top bottom 6 1 1 0 reser v ed ? ? ? 7 1 1 1 fast pwm ocra top top bit 76543210 foc0a foc0b ? ? wgm02 cs02 cs01 cs00 tccr0b read/ w rite w w r r r/w r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 112 7593l?avr?09/12 at90usb64/128 strobe. therefore it is the v alue present in the com0b1:0 bits that determines the effect of the forced compare. a foc0b strobe w ill not generate any interrupt, nor w ill it clear the timer in ctc mode using ocr0b as top. the foc0b bit is al w ays read as zero. ? bits 5:4 ? res: reserved bits these bits are reser v ed bits and w ill al w ays read as zero. ? bit 3 ? wgm02: waveform generation mode see the description in the ?tccr0a ? timer/counter control register a? on page 108 . ? bits 2:0 ? cs02:0: clock select the three clock select bits select the clock source to be used by the timer/counter. if external pin modes are used for the timer/counter0, transitions on the t0 pin w ill clock the counter e v en if the pin is configured as an output. this feature allo w s soft w are control of the counting. 14.8.3 tcnt0 ? timer/counter register the timer/counter register gi v es direct access, both for read and w rite operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (remo v es) the compare match on the follo w ing timer clock. modifying the counter (tcnt0) w hile the counter is running, introduces a risk of missing a compare match bet w een tcnt0 and the ocr0x registers. 14.8.4 ocr0a ? output compare register a table 14-8. clock select bit description. cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 tcnt0 [7:0] tcnt0 read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ocr0a [7:0] ocr0a read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 113 7593l?avr?09/12 at90usb64/128 the output compare register a contains an 8-bit v alue that is continuously compared w ith the counter v alue (tcnt0). a match can be used to generate an output compare interrupt, or to generate a w a v eform output on the oc0a pin. 14.8.5 ocr0b ? output compare register b the output compare register b contains an 8-bit v alue that is continuously compared w ith the counter v alue (tcnt0). a match can be used to generate an output compare interrupt, or to generate a w a v eform output on the oc0b pin. 14.8.6 timsk0 ? timer/counter interrupt mask register ? bits 7..3, 0 ? res: reserved bits these bits are reser v ed bits and w ill al w ays read as zero. ? bit 2 ? ocie0b: timer/counter output compare match b interrupt enable when the ocie0b bit is w ritten to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enab led. the corresponding interrupt is executed if a compare match in timer/counter occurs, that is, w hen the ocf0b bit is set in the timer/counter interrupt flag register ? tifr0. ? bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is w ritten to one, and the i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter0 occurs, that is, w hen the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is w ritten to one, and the i-bit in the status register is set, the timer/counter0 o v erflo w interrupt is enabled. the corresponding interrupt is executed if an o v erflo w in timer/counter0 occurs, that is, w hen the tov0 bit is set in the timer/counter 0 inter- rupt flag register ? tifr0. 14.8.7 tifr0 ? timer/counter 0 interrupt flag register ? bits 7..3, 0 ? res: reserved bits these bits are reser v ed bits in the atmel at90usb64/128 and w ill al w ays read as zero. bit 76543210 ocr0b [7:0] ocr0b read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543 2 10 ? ? ? ? ? ocie0b ocie0a toie0 timsk0 read/ w rite r r r r r r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 bit 76543210 ?????ocf0bocf0a tov0 tifr0 read/ w riterrrrrr/wr/wr/w initial v alue00000000 114 7593l?avr?09/12 at90usb64/128 ? bit 2 ? ocf0b: timer/counter 0 output compare b match flag the ocf0b bit is set w hen a compare match occurs bet w een the timer/counter and the data in ocr0b ? output compare register0 b. ocf0b is cleared by hard w are w hen executing the cor- responding interrupt handling v ector. alternati v ely, ocf0b is cleared by w riting a logic one to the flag. when the i-bit in sreg, ocie0b (timer/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. ? bit 1 ? ocf0a: timer/counter 0 output compare a match flag the ocf0a bit is set w hen a compare match occurs bet w een the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hard w are w hen executing the cor- responding interrupt handling v ector. alternati v ely, ocf0a is cleared by w riting a logic one to the flag. when the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match interrupt is executed. ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set w hen an o v erflo w occurs in timer/counter0. tov0 is cleared by hard w are w hen executing the corresponding interrupt handling v ector. alternati v ely, tov0 is cleared by w riting a logic one to the flag. when the sreg i-bit, toie0 (timer/counter0 o v erflo w interrupt enable), and tov0 are set, the timer/counter0 o v erflo w interrupt is executed. the setting of this flag is dependent of the wgm02:0 bit setting. refer to table 14-7 , ?wa v eform generation mode bit description.? on page 111 . 115 7593l?avr?09/12 at90usb64/128 15. 16-bit timer/counter (timer/counter1 and timer/counter3) the 16-bit timer/counter unit allo w s accurate program execution timing (e v ent management), w a v e generation, and signal timing measurement. the main features are: ? true 16-bit design (that is, allows 16-bit pwm) ? three independent output compare units ? double buffered output compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? ten independent interrupt sources (tov1, ocf1a, ocf1b, ocf1c, icf1, tov3, ocf3a, ocf3b, ocf3c, and icf3) 15.1 overview most register and bit references in this section are w ritten in general form. a lo w er case ?n? replaces the timer/counter number, and a lo w er case ?x? replaces the output compare unit channel. ho w e v er, w hen using the register or bit defines in a program, the precise form must be used, that is, tcnt1 for accessing timer/counter1 counter v alue and so on. a simplified block diagram of the 16-bit timer/counter is sho w n in figure 15-1 on page 116 . for the actual placement of i/o pins, see ?pinout atmel at90usb64/128-tqfp.? on page 3 . cpu accessible i/o registers, including i/o bits and i/o pins, are sho w n in bold. the de v ice-specific i/o register and bit locations are listed in the ?16-bit timer/counter (timer/counter1 and timer/counter3)? on page 115 . the po w er reduction timer/counter1 bit, prtim1, in ?prr0 ? po w er reduction register 0? on page 54 must be w ritten to zero to enable timer/counter1 module. the po w er reduction timer/counter3 bit, prtim3, in ?prr1 ? po w er reduction register 1? on page 55 must be w ritten to zero to enable timer/counter3 module. 116 7593l?avr?09/12 at90usb64/128 figure 15-1. 16-bit timer/counter block diagram (1) . note: 1. refer to figure 1-1 on page 3 , table 11-6 on page 79 , and table 11-9 on page 82 for timer/counter1 and 3 and 3 pin placement and description. 15.1.1 registers the timer/counter (tcntn), output compare registers (ocrna/b/c), and input capture reg- ister (icrn) are all 16-bit registers. special procedures must be follo w ed w hen accessing the 16- bit registers. these procedures are described in the section ?accessing 16-bit registers? on page 117 . the timer/counter control registers (tccrna/b/c) are 8-bit registers and ha v e no cpu access restrictions. interrupt requests (shorten as int.req.) signals are all v isible in the timer interrupt flag register (tifrn). all interrupts are indi v idually masked w ith the timer interrupt mask register (timskn). tifrn and timskn are not sho w n in the figure since these registers are shared by other timer units. the timer/counter can be clocked internally, v ia the prescaler, or by an external clock source on the tn pin. the clock select logic block controls w hich clock source and edge the timer/counter uses to increment (or decrement) its v alue. the timer/counter is inacti v e w hen no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t n ). the double buffered output compare registers (ocrna/b/c) are compared w ith the timer/counter v alue at all time. the result of the compare can be used by the wa v eform gener- ator to generate a pwm or v ariable frequency output on the output compare pin (ocna/b/c). icfn (int.req.) tovn (int.req.) clock select timer/counter databus icrn = = = tcntn waveform generation waveform generation waveform generation ocna ocnb ocnc noise canceler icpn = fixed top values edge detector control logic = 0 top bottom count clear direction ocfna (int.req.) ocfnb (int.req.) ocfnc (int.req.) tccrna tccrnb tccrnc ( from analog comparator ouput ) tn edge detector (from prescaler) tclk ocrnc ocrnb ocrna 117 7593l?avr?09/12 at90usb64/128 see ?output compare units? on page 124. . the compare match e v ent w ill also set the compare match flag (ocfna/b/c) w hich can be used to generate an output compare interrupt request. the input capture register can capture the timer/counter v alue at a gi v en external (edge trig- gered) e v ent on either the input capture pin (icpn) or on the analog comparator pins ( see ?analog comparator? on page 304 ) the input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. the top v alue, or maximum timer/counter v alue, can in some modes of operation be defined by either the ocrna register, the icrn register, or by a set of fixed v alues. when using ocrna as top v alue in a pwm mode, the ocrna register can not be used for generating a pwm output. ho w e v er, the top v alue w ill in this case be double buffered allo w ing the top v alue to be changed in run time. if a fixed top v alue is required, the icrn register can be used as an alternati v e, freeing the ocrna to be used as pwm output. 15.1.2 definitions the follo w ing definitions are used extensi v ely throughout the document: 15.2 accessing 16-bit registers the tcntn, ocrna/b/c, and icrn are 16-bit registers that can be accessed by the avr cpu v ia the 8-bit data bus. the 16-bit register must be byte accessed using t w o read or w rite opera- tions. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16- bit access. the same temporary register is shared bet w een all 16-bit registers w ithin each 16- bit timer. accessing the lo w byte triggers the 16-bit read or w rite operation. when the lo w byte of a 16-bit register is w ritten by the cpu, the high byte stored in the temporary register, and the lo w byte w ritten are both copied into the 16-bit regi ster in the same clock cycle. when the lo w byte of a 16-bit register is read by the cpu, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the lo w byte is read. not all 16-bit accesses uses the temporary regi ster for the high byte. reading the ocrna/b/c 16-bit registers does not in v ol v e using the temporary register. to do a 16-bit w rite, the high byte must be w ritten before the lo w byte. for a 16-bit read, the lo w byte must be read before the high byte. the follo w ing code examples sho w ho w to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocrna/b/c and icrn registers. note that w hen using ?c?, the compiler handles the 16-bit access. bottom the counter reaches the bottom w hen it becomes 0x0000. max the counter reaches its max imum w hen it becomes 0xffff (decimal 65535). top the counter reaches the top w hen it becomes equal to the highest v alue in the count sequence. the top v alue can be assigned to be one of the fixed v alues: 0x00ff, 0x01ff, or 0x03ff, or to the v alue stored in the ocrna or icrn register. the assignment is dependent of the mode of operation. 118 7593l?avr?09/12 at90usb64/128 note: 1. see ?about code examples? on page 10. the assembly code example returns the tcntn v alue in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs bet w een the t w o instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer regis- ters, then the result of the access outside the interrupt w ill be corrupted. therefore, w hen both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. assembly code examples (1) ... ; set tcntn to 0x01ff ldi r17,0x01 ldi r16,0xff out tcntnh,r17 out tcntnl,r16 ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ... c code examples (1) unsigned int i; ... /* set tcntn to 0x01ff */ tcntn = 0x1ff; /* read tcntn into i */ i = tcntn; ... 119 7593l?avr?09/12 at90usb64/128 the follo w ing code examples sho w ho w to do an atomic read of the tcntn register contents. reading any of the ocrna/b/c or icrn registers can be done by using the same principle. note: 1. see ?about code examples? on page 10. the assembly code example returns the tcntn v alue in the r17:r16 register pair. assembly code example (1) tim16_readtcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcntn into r17:r16 in r16,tcntnl in r17,tcntnh ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcntn( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ __disable_interrupt(); /* read tcntn into i */ i = tcntn; /* restore global interrupt flag */ sreg = sreg; return i; } 120 7593l?avr?09/12 at90usb64/128 the follo w ing code examples sho w ho w to do an atomic w rite of the tcntn register contents. writing any of the ocrna/b/c or icrn registers can be done by using the same principle. note: 1. see ?about code examples? on page 10. the assembly code example requires that the r17:r16 register pair contains the v alue to be w rit- ten to tcntn. 15.2.1 reusing the temporary high byte register if w riting to more than one 16-bit register w here the high byte is the same for all registers w ritten, then the high byte only needs to be w ritten once. ho w e v er, note that the same rule of atomic operation described pre v iously also applie s in this case. 15.3 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic w hich is controlled by the clock select (csn2:0) bits located in the timer/counter control register b (tccrnb). for details on clock sources and prescaler, see section ?timer/counter0, timer/counter1, and timer/counter3 prescalers? on page 96 . assembly code example (1) tim16_writetcntn: ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcntn to r17:r16 out tcntnh,r17 out tcntnl,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcntn( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ __disable_interrupt(); /* set tcntn to i */ tcntn = i; /* restore global interrupt flag */ sreg = sreg; } 121 7593l?avr?09/12 at90usb64/128 15.4 counter unit the main part of the 16-bit timer/counter is th e programmable 16-bit bi-directional counter unit. figure 15-2 sho w s a block diagram of the counter and its surroundings. figure 15-2. counter unit block diagram. signal description (internal signals): count increment or decrement tcntn by 1. direction select bet w een increment and decrement. clear clear tcntn (set all bits to zero). clk t n timer/counter clock. top signalize that tcntn has reached maximum v alue. bottom signalize that tcntn has reached minimum v alue (zero). the 16-bit counter is mapped into t w o 8-bit i/o memory locations: counter high (tcntnh) con- taining the upper eight bits of the counter, and counter low (tcntnl) containing the lo w er eight bits. the tcntnh register can only be indirect ly accessed by the cpu. when the cpu does an access to the tcntnh i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated w ith the tcntnh v alue w hen the tcntnl is read, and tcntnh is updated w ith the temporary register v alue w hen tcntnl is w ritten. this allo w s the cpu to read or w rite the entire 16-bit counter v alue w ithin one clock cycle v ia the 8-bit data bus. it is important to notice that there are special cases of w riting to the tcntn register w hen the counter is counting that w ill gi v e unpredictable results. the special cases are described in the sections w here they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t n ). the clk t n can be generated from an external or internal clock source, selected by the clock select bits (csn2:0). when no clock source is selected (csn2:0 = 0) the timer is stopped. ho w e v er, the tcntn v alue can be accessed by the cpu, independent of w hether clk t n is present or not. a cpu w rite o v errides (has priority o v er) all counter clear or count operations. the counting sequence is determined by the setting of the waveform generation mode bits (wgmn3:0) located in the timer/counter control registers a and b (tccrna and tccrnb). there are close connections bet w een ho w the counter beha v es (counts) and ho w w a v eforms are generated on the output compare outputs ocnx. for more details about ad v anced counting sequences and w a v eform generation, see section ?modes of operation? on page 127 . temp (8- b it) data bus (8- b it) tcntn (16- b it co u nter) tcntnh (8- b it) tcntnl (8- b it) control logic co u nt cle a r direction tovn (int.req.) clock s elect top bottom tn edge detector (from pre s c a ler) clk tn 122 7593l?avr?09/12 at90usb64/128 the timer/counter o v erflo w flag (tovn) is set according to the mode of operation selected by the wgmn3:0 bits. tovn can be used for generating a cpu interrupt. 15.5 input capture unit the timer/counter incorporates an input capture unit that can capture external e v ents and gi v e them a time-stamp indicating time of occurrence. the external signal indicating an e v ent, or mul- tiple e v ents, can be applied v ia the icpn pin or alternati v ely, for the timer/counter1 only, v ia the analog comparator unit. the time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. alternati v ely the time-stamps can be used for creating a log of the e v ents. the input captur e unit is illustrated by the block diagram sho w n in figure 15-3 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. the small ?n? in register and bit names indicates the timer/counter number. figure 15-3. input capture unit block diagram. note: the analog comparator output (aco) ca n only trigger the timer/counter1 icp ? not timer/counter3, 4, or 5. when a change of the logic le v el (an e v ent) occurs on the input capture pin (icpn), alternati v ely on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a capture w ill be triggered. when a capture is trig gered, the 16-bit v alue of the counter (tcntn) is w ritten to the input capture register (icrn). the input capture flag (icfn) is set at the same system clock as the tcntn v alue is copied into icrn register. if enabled (ticien = 1), the input capture flag generates an input capt ure interrupt. the icfn flag is automatically cleared w hen the interrupt is executed. alternati v ely the icfn flag can be cleared by soft w are by w riting a logical one to its i/o bit location. icfn (int.req.) an a log comp a r a tor write icrn (16- b it regi s ter) icrnh (8- b it) noi s e c a nceler icpn edge detector temp (8- b it) data bus (8- b it) icrnl (8- b it) tcntn (16- b it co u nter) tcntnh (8- b it) tcntnl (8- b it) acic* icnc ice s aco* 123 7593l?avr?09/12 at90usb64/128 reading the 16-bit v alue in the input capture register (icrn) is done by first reading the lo w byte (icrnl) and then the high byte (icrnh). when the lo w byte is read the high byte is copied into the high byte temporary register (temp). when the cpu reads the icrnh i/o location it w ill access the temp register. the icrn register can only be w ritten w hen using a wa v eform generation mode that utilizes the icrn register for defining the counter?s top v alue. in these cases the waveform genera- tion mode (wgmn3:0) bits must be set before the top v alue can be w ritten to the icrn register. when w riting the icrn register the high byte must be w ritten to the icrnh i/o location before the lo w byte is w ritten to icrnl. for more information on ho w to access the 16-bit registers refer to section ?accessing 16-bit registers? on page 117 . 15.5.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icpn). timer/counter1 can alternati v ely use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (acic) bit in the analog comparator control and status register (acsr). be a w are that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icpn) and the analog comparator output (aco) inputs are sampled using the same technique as for the tn pin ( figure 13-1 on page 96 ). the edge detector is also identical. ho w e v er, w hen the noise canceler is enabled, addi tional logic is inserted before the edge detector, w hich increases the delay by four system clock cycles. note that the input of the noise canceler and edge detector is al w ays enabled unless the timer/counter is set in a wa v e- form generation mode that uses icrn to define top. an input capture can be triggered by soft w are by controlling the po rt of the icpn pin. 15.5.2 noise canceler the noise canceler impro v es noise immunity by using a simp le digital filtering scheme. the noise canceler input is monitored o v er four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icncn) bit in timer/counter control register b (tccrnb). when enabled the noise canceler introduces addi- tional four system clock cycles of delay from a change applied to the input, to the update of the icrn register. the noise canceler uses the sy stem clock and is therefore not affected by the prescaler. 15.5.3 using the input capture unit the main challenge w hen using the input capture unit is to assign enough processor capacity for handling the incoming e v ents. the time bet w een t w o e v ents is critical. if the processor has not read the captured v alue in the icrn register before the next e v ent occurs, the icrn w ill be o v er w ritten w ith a ne w v alue. in this case the result of the capture w ill be incorrect. when using the input capture interrupt, the icrn register should be read as early in the inter- rupt handler routine as possible. e v en though the input capture interrupt has relati v ely high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 124 7593l?avr?09/12 at90usb64/128 using the input capture unit in any mode of operation w hen the top v alue (resolution) is acti v ely changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icrn register has been read. after a change of the edge, the input capture flag (icfn) must be cleared by soft w are ( w riting a logical one to the i/o bit location). for measuring frequency only, the clearing of the icfn flag is not required (if an interrupt handler is used). 15.6 output compare units the 16-bit comparator continuously compares tcntn w ith the output compare register (ocrnx). if tcnt equals ocrnx the comparator signals a match. a match w ill set the output compare flag (ocfnx) at the next timer clock cycle. if enabled (ocienx = 1), the output com- pare flag generates an output compare interrupt. the ocfnx flag is automatically cleared w hen the interrupt is executed. alternati v ely the ocfnx flag can be cleared by soft w are by w rit- ing a logical one to its i/o bit location. the wa v eform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (wgmn3:0) bits and compare output mode (comnx1:0) bits. the top and bottom signals are used by the wa v eform generator for handling the special cases of the extreme v alues in some modes of operation ( see ?modes of operation? on page 127 ) a special feature of output compare unit a allo w s it to define the timer/counter top v alue (that is, counter resolution). in addition to the counter resolution, the top v alue defines the period time for w a v eforms generated by the wa v eform generator. figure 15-4 sho w s a block diagram of the output compare unit. the small ?n? in the register and bit names indicates the de v ice number (n = n for timer/counter n), and the ?x? indicates output compare unit (a/b/c). the elements of the block diagram that are not directly a part of the out- put compare unit are gray shaded. figure 15-4. output compare unit, block diagram. ocfnx (int.req.) = (16- b it comp a r a tor ) ocrnx bu ffer (16- b it regi s ter) ocrnxh bu f. (8- b it) ocnx temp (8- b it) data bus (8- b it) ocrnxl bu f. (8- b it) tcntn (16- b it co u nter) tcntnh (8- b it) tcntnl (8- b it) comnx1:0 wgmn 3 :0 ocrnx (16- b it regi s ter) ocrnxh (8- b it) ocrnxl (8- b it) w a veform gener a tor top bottom 125 7593l?avr?09/12 at90usb64/128 the ocrnx register is double buffered w hen using any of the t w el v e pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocrnx com- pare register to either top or bottom of the counting sequence. the synchronization pre v ents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the out- put glitch-free. the ocrnx register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocrnx buffer register, and if double buffering is dis- abled the cpu w ill access the ocrnx directly. the content of the ocr1x (buffer or compare) register is only changed by a w rite operation (the timer/counter does not update this register automatically as the tcnt1 and icr1 register). therefore ocr1x is not read v ia the high byte temporary register (temp). ho w e v er, it is a good practice to read the lo w byte first as w hen accessing other 16-bit registers. writing the ocrnx registers must be done v ia the temp reg- ister since the compare of all 16 bits is done continuously. the high byte (ocrnxh) has to be w ritten first. when the high byte i/o location is w ritten by the cpu, the temp register w ill be updated by the v alue w ritten. then w hen the lo w byte (ocrnxl) is w ritten to the lo w er eight bits, the high byte w ill be copied into the upper 8-bits of ei ther the ocrnx buffer or ocrnx compare register in the same system clock cycle. for more information of ho w to access the 16-bit registers refer to section ?accessing 16-bit reg- isters? on page 117 . 15.6.1 force output compare in non-pwm wa v eform generation modes, the match output of the comparator can be forced by w riting a one to the force output compare (focnx) bit. forcing compare match w ill not set the ocfnx flag or reload/clear the timer, but the ocnx pin w ill be updated as if a real compare match had occurred (the comn1:0 bits settings define w hether the ocnx pin is set, cleared or toggled). 15.6.2 compare match blocking by tcntn write all cpu w rites to the tcntn register w ill block any compare match that occurs in the next timer clock cycle, e v en w hen the timer is stopped. this feature allo w s ocrnx to be initialized to the same v alue as tcntn w ithout triggering an interrupt w hen the timer/counter clock is enabled. 15.6.3 using the output compare unit since w riting tcntn in any mode of operation w ill block all compare matches for one timer clock cycle, there are risks in v ol v ed w hen changing tcntn w hen using any of the output compare channels, independent of w hether the timer/counter is running or not. if the v alue w ritten to tcntn equals the ocrnx v alue, the compare match w ill be missed, result ing in incorrect w a v e- form generation. do not w rite the tcntn equal to top in pwm modes w ith v ariable top v alues. the compare match for the top w ill be ignored and the counter w ill continue to 0xffff. similarly, do not w rite the tcntn v alue equal to bottom w hen the counter is counting do w n. the setup of the ocnx should be performed before setting the data direction register for the port pin to output. the easiest w ay of setting the ocnx v alue is to use the force output com- pare (focnx) strobe bits in normal mode. the ocnx register keeps its v alue e v en w hen changing bet w een wa v eform generation modes. be a w are that the comnx1:0 bits are not double buffered together w ith the compare v alue. changing the comnx1:0 bits w ill take effect immediately. 126 7593l?avr?09/12 at90usb64/128 15.7 compare match output unit the compare output mode (comnx1:0) bits ha v e t w o functions. the wa v eform generator uses the comnx1:0 bits for defining the output compare (ocnx) state at the next compare match. secondly the comnx1:0 bits control the ocnx pin output source. figure 15-5 sho w s a simplified schematic of the logic affected by the comnx1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are sho w n in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the comnx1:0 bits are sho w n. when referring to the ocnx state, the reference is for the internal ocnx register, not the ocnx pin. if a system reset occur, the ocnx register is reset to ?0?. figure 15-5. compare match output unit, schematic. the general i/o port function is o v erridden by the output compare (ocnx) from the wa v eform generator if either of the comnx1:0 bits are set. ho w e v er, the ocnx pin direction (input or out- put) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the ocnx pin (ddr_ocnx) mu st be set as output before the ocnx v alue is v isi- ble on the pin. the port o v erride function is generally independent of the wa v eform generation mode, but there are some exceptions. refer to table 15-1 on page 137 , table 15-2 on page 137 , and table 15-3 on page 138 for details. the design of the output compare pin logic allo w s initialization of the ocnx state before the out- put is enabled. note that some comnx1:0 bit settings are reser v ed for certain modes of operation. see ?16-bit timer/counter (timer/counter1 and timer/counter3)? on page 115. the comnx1:0 bits ha v e no effect on the input capture unit. 15.7.1 compare output mode and waveform generation the wa v eform generator uses the comnx1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the comnx1:0 = 0 tells the wa v eform generator that no action on the ocnx register is to be performed on the next compare match. for compare output actions in the port ddr dq dq ocnx pin ocnx dq w a veform gener a tor comnx1 comnx0 0 1 data b u s focnx clk i/o 127 7593l?avr?09/12 at90usb64/128 non-pwm modes refer to table 15-1 on page 137 . for fast pwm mode refer to table 15-2 on page 137 , and for phase correct and phase and frequency correct pwm refer to table 15-3 on page 138 . a change of the comnx1:0 bits state w ill ha v e effect at the first compare match after the bits are w ritten. for non-pwm modes, the action can be forced to ha v e immediate effect by using the focnx strobe bits. 15.8 modes of operation the mode of operation, that is, the beha v ior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgmn3:0) and compare out- put mode (comnx1:0) bits. the compare output mode bits do not affect the counting sequence, w hile the wa v eform generation mode bits do. the comnx1:0 bits control w hether the pwm out- put generated should be in v erted or not (in v erted or non-in v erted pwm). for non-pwm modes the comnx1:0 bits control w hether the output should be set, cleared or toggle at a compare match ( see ?compare match output unit? on page 126 ). for detailed timing information refer to ?timer/counter timing diagrams? on page 134 . 15.8.1 normal mode the simplest mode of operation is the normal mode (wgmn3:0 = 0). in this mode the counting direction is al w ays up (incrementing), and no counter cl ear is performed. the counter simply o v erruns w hen it passes its maximum 16-bit v alue (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/counter overflow flag (tovn) w ill be set in the same timer clock cycle as the tcntn beco mes zero. the tovn flag in this case beha v es like a 17th bit, except that it is only set, not cleared. ho w e v er, combined w ith the timer o v erflo w interrupt that automatically clears the tovn flag, the timer resolution can be increased by soft- w are. there are no special cases to consider in the normal mode, a ne w counter v alue can be w ritten anytime. the input capture unit is easy to use in normal mode. ho w e v er, obser v e that the maximum inter v al bet w een the external e v ents must not exceed the resolution of the counter. if the inter v al bet w een e v ents are too long, the timer o v erflo w interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generate interrupts at some gi v en time. using the output compare to generate w a v eforms in normal mode is not recommended, since this w ill occupy too much of the cpu time. 15.8.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgmn3:0 = 4 or 12), the ocrna or icrn register are used to manipulate the counter resolution . in ctc mode the counter is cleared to zero w hen the counter v alue (tcntn) matches either the ocrna (wgmn3:0 = 4) or the icrn (wgmn3:0 = 12). the ocrna or icrn define the top v alue for the counter, hence also its resolution. this mode allo w s greater control of the compare match output frequency. it also simplifies the opera- tion of counting external e v ents. the timing diagram for the ctc mode is sho w n in figure 15-6 on page 128 . the counter v alue (tcntn) increases until a compare match occurs w ith either ocrna or icrn, and then counter (tcntn) is cleared. 128 7593l?avr?09/12 at90usb64/128 figure 15-6. ctc mode, timing diagram. an interrupt can be generated at each time the counter v alue reaches the top v alue by either using the ocfna or icfn flag according to the register used to define the top v alue. if the interrupt is enabled, the interrupt handler routine can be used for updating the top v alue. ho w - e v er, changing the top to a v alue close to bottom w hen the counter is running w ith none or a lo w prescaler v alue must be done w ith care since the ctc mode does not ha v e the double buff- ering feature. if the ne w v alue w ritten to ocrna or icrn is lo w er than the current v alue of tcntn, the counter w ill miss the compare ma tch. the counter w ill then ha v e to count to its max- imum v alue (0xffff) and w rap around starting at 0x0000 before the compare match can occur. in many cases this feature is not desirable. an alternati v e w ill then be to use the fast pwm mode using ocrna for defining top (wgmn3:0 = 15) since the ocrna then w ill be double buffered. for generating a w a v eform output in ctc mode, the ocna output can be set to toggle its logical le v el on each compare match by setting the compare output mode bits to toggle mode (comna1:0 = 1). the ocna v alue w ill not be v isible on the port pin unless the data direction for the pin is set to outp ut (ddr_ocna = 1). the w a v eform generated w ill ha v e a maximum fre- quency of f oc n a = f clk_i/o /2 w hen ocrna is set to zero (0x0000). the w a v eform frequency is defined by the follo w ing equation: the n v ariable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tovn flag is set in the same timer clock cycle that the counter counts from max to 0x0000. 15.8.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgmn3:0 = 5, 6, 7, 14, or 15) pro v ides a high frequency pwm w a v eform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-in v erting compare output mode, the output compare (ocnx) is set on the compare match bet w een tcntn and ocrnx, and cleared at top. in in v erting compare output mode output is cleared on compare match and set at top. due to the single-slope oper- ation, the operating frequency of the fast pwm mode can be t w ice as high as the phase correct and phase and frequency correct pwm modes that use dual-slope operation. this high fre- quency makes the fast pwm mode w ell suited for po w er regulation, rectification, and dac applications. high frequency allo w s physically small sized exter nal components (c oils, capaci- tors), hence reduces total system cost. tcntn ocna (toggle) ocna interr u pt fl a g set or icfn interr u pt fl a g set (interr u pt on top) 1 4 period 2 3 (comna1:0 = 1) f ocna f clk_i/o 2 n 1 ocrna + () ?? -------------------------------------------------- - = 129 7593l?avr?09/12 at90usb64/128 the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimu m resolution allo w ed is 2-bit (icrn or ocrna set to 0x0003), and the max- imum resolution is 16-bit (icrn or ocrna set to max). the pwm resolution in bits can be calculated by using the follo w ing equation: in fast pwm mode the counter is incremented until the counter v alue matches either one of the fixed v alues 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 5, 6, or 7), the v alue in icrn (wgmn3:0 = 14), or the v alue in ocrna (wgmn3:0 = 15). the counter is then cleared at the follo w ing timer clock cycle. the timing diagram for the fast pwm mode is sho w n in figure 15-7 . the figure sho w s fast pwm mode w hen ocrna or icrn is used to define top. the tcntn v alue is in the timing diagram sho w n as a histogram for illustrating the single-slope operation. the diagram includes non-in v erted and in v erted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matches bet w een ocrnx and tcntn. the ocnx interrupt flag w ill be set w hen a compare match occurs. figure 15-7. fast pwm mode, timing diagram. the timer/counter o v erflo w flag (tovn) is set each time the counter reaches top. in addition the ocna or icfn flag is set at the same timer clock cycle as tovn is set w hen either ocrna or icrn is used for defining the top v alue. if one of the interrupts are enabled, the interrupt han- dler routine can be used for updating the top and compare v alues. when changing the top v alue the program must ensure that the ne w top v alue is higher or equal to the v alue of all of the compare registers. if the top v alue is lo w er than any of the compare registers, a compare match w ill ne v er occur bet w een the tcntn and the ocrnx. note that w hen using fixed top v alues the unused bits are masked to zero w hen any of the ocrnx registers are w ritten. the procedure for updating icrn differs from updating ocrna w hen used for defining the top v alue. the icrn register is not double buffered. this means that if icrn is changed to a lo w v alue w hen the counter is running w ith none or a lo w prescaler v alue, there is a risk that the ne w icrn v alue w ritten is lo w er than the current v alue of tcntn. the result w ill then be that the counter w ill miss the compare match at the top v alue. the counter w ill then ha v e to count to the max v alue (0xffff) and w rap around starting at 0x0000 before the compare match can occur. the ocrna register ho w e v er, is double buffered. this feature allo w s the ocrna i/o location r fpwm top 1 + () log 2 () log ---------------------------------- - = tcntn ocrnx / top update and tovn interrupt flag s et and ocna interrupt flag s et or icfn interrupt flag s et (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 130 7593l?avr?09/12 at90usb64/128 to be w ritten anytime. when the ocrna i/o location is w ritten the v alue w ritten w ill be put into the ocrna buffer register. the ocrna compare register w ill then be updated w ith the v alue in the buffer register at the next timer clo ck cycle the tcntn matches top. the update is done at the same timer clock cycle as the tcnt n is cleared and the tovn flag is set. using the icrn register for defining top w orks w ell w hen using fixed top v alues. by using icrn, the ocrna register is free to be used for generating a pwm output on ocna. ho w e v er, if the base pwm frequency is acti v ely changed (by changing the top v alue), using the ocrna as top is clearly a better choice due to its double buffer feature. in fast pwm mode, the compare units allo w generation of pwm w a v eforms on the ocnx pins. setting the comnx1:0 bits to t w o w ill produce a non-in v erted pwm and an in v erted pwm output can be generated by setting the comnx1:0 to three (see table on page 137 ). the actual ocnx v alue w ill only be v isible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm w a v eform is generated by setting (or clearing) the ocnx register at the compare match bet w een ocrnx and tcntn, and clearing (or setting) the ocnx register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the follo w ing equation: the n v ariable represents the prescaler di v ider (1, 8, 64, 256, or 1024). the extreme v alues for the ocrnx register represents special cases w hen generating a pwm w a v eform output in the fast pwm mode. if the ocrnx is set equal to bottom (0x0000) the out- put w ill be a narro w spike for each top+1 timer clock cycle. setting the ocrnx equal to top w ill result in a constant high or lo w output (depending on the polarity of the output set by the comnx1:0 bits.) a frequency ( w ith 50% duty cycle) w a v eform output in fast pwm mode can be achie v ed by set- ting ocna to toggle its logical le v el on each compare match (comna1:0 = 1). this applies only if ocr1a is used to define the top v alue (wgm13:0 = 15). the w a v eform generated w ill ha v e a maximum frequency of f oc n a = f clk_i/o /2 w hen ocrna is set to zero (0x0000). this feature is similar to the ocna toggle in ctc mode, except the double buffer feature of the output com- pare unit is enabled in the fast pwm mode. 15.8.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pwm mode (wgmn3:0 = 1, 2, 3, 10, or 11) pro v ides a high resolution phase correct pwm w a v eform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual- slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-in v erting compare output mode, the output compare (ocnx) is cleared on the compare match bet w een tcntn and ocrnx w hile upcounting, and set on the compare match w hile do w ncounting. in in v erting output compare mode, the operation is in v erted. the dual-slope operation has lo w er maximum operation frequency than single slope operation. ho w e v er, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit, or defined by either icrn or ocrna. the minimum resolution allo w ed is 2-bit (icrn or ocrna set to f ocnxpwm f clk_i/o n 1 top + () ? ---------------------------------- - = 131 7593l?avr?09/12 at90usb64/128 0x0003), and the maximum resolution is 16-bit (icrn or ocrna set to max). the pwm resolu- tion in bits can be calculated by using the follo w ing equation: in phase correct pwm mode the counter is incremented until the counter v alue matches either one of the fixed v alues 0x00ff, 0x01ff, or 0x03ff (wgmn3:0 = 1, 2, or 3), the v alue in icrn (wgmn3:0 = 10), or the v alue in ocrna (wgmn3:0 = 11). the counter has then reached the top and changes the count direction. the tcntn v alue w ill be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is sho w n on figure 15-8 . the figure sho w s phase correct pwm mode w hen ocrna or icrn is used to define top. the tcntn v alue is in the timing diagram sho w n as a histogram for illustrating the dual-slope operation. the diagram includes non-in v erted and in v erted pwm outputs. the small horizontal line marks on the tcntn slopes represent compare matches bet w een ocrnx and tcntn. the ocnx inter- rupt flag w ill be set w hen a compare match occurs. figure 15-8. phase correct pwm mode, timing diagram. the timer/counter o v erflo w flag (tovn) is set each time the counter reaches bottom. when either ocrna or icrn is used for defining the top v alue, the ocna or icfn flag is set accord- ingly at the same timer clock cycl e as the ocrnx registers are updated w ith the double buffer v alue (at top). the interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom v alue. when changing the top v alue the program must ensure that the ne w top v alue is higher or equal to the v alue of all of the compare registers. if the top v alue is lo w er than any of the compare registers, a compare match w ill ne v er occur bet w een the tcntn and the ocrnx. note that w hen using fixed top v alues, the unused bits are masked to zero w hen any of the ocrnx registers are w ritten. as the third period sho w n in figure 15-8 illustrates, changing the top acti v ely w hile the timer/counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocrnx reg- r pcpwm top 1 + () log 2 () log ---------------------------------- - = ocrnx/top update and ocna interrupt flag s et or icfn interrupt flag s et (interrupt on top) 1 2 3 4 tovn interrupt flag s et (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 132 7593l?avr?09/12 at90usb64/128 ister. since the ocrnx update occurs at top, the pwm period starts and ends at top. this implies that the length of the falling slope is determined by the pre v ious top v alue, w hile the length of the rising slope is determined by the ne w top v alue. when these t w o v alues differ the t w o slopes of the period w ill differ in length. the difference in length gi v es the unsymmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode w hen changing the top v alue w hile the timer/counter is running. when using a static top v alue there are practically no differences bet w een the t w o modes of operation. in phase correct pwm mode, the compare units allo w generation of pwm w a v eforms on the ocnx pins. setting the comnx1:0 bits to t w o w ill produce a non-in v erted pwm and an in v erted pwm output can be generated by setting the comnx1:0 to three (see table 15-3 on page 138 ). the actual ocnx v alue w ill only be v isible on the port pin if the data direction for the port pin is set as output ( ddr_ocnx). the pwm w a v eform is generated by setting (or clearing) the ocnx register at the compare match bet w een ocrnx and tcntn w hen the counter increments, and clearing (or setting) the ocnx register at compare match bet w een ocrnx and tcntn w hen the counter decrements. the pwm frequency for the output w hen using phase correct pwm can be calculated by the follo w ing equation: the n v ariable represents the prescaler di v ider (1, 8, 64, 256, or 1024). the extreme v alues for the ocrnx register represent special cases w hen generating a pwm w a v eform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the output w ill be continuously lo w and if set equal to top the output w ill be continuously high for non-in v erted pwm mode. for in v erted pwm the output w ill ha v e the opposite logic v alues. if ocr1a is used to define the top v alue (wgm13:0 = 11) and com1a1:0 = 1, the oc1a output w ill toggle w ith a 50% duty cycle. 15.8.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgmn3:0 = 8 or 9) pro v ides a high resolution phase and frequency correct pwm w a v e- form generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-in v erting compare output mode, the output compare (ocnx) is cleared on the compare match bet w een tcntn and ocrnx w hile upcounting, and set on the compare match w hile do w ncounting. in in v erting compare output mode, the operation is in v erted. the dual-slope operation gi v es a lo w er maximum operation fre- quency compared to the single-slope operation. ho w e v er, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the main difference bet w een the phase correct, and the phase and frequency correct pwm mode is the time the ocrnx register is up dated by the ocrnx buffer register, (see figure 15- 8 on page 131 and figure 15-9 on page 133 ). the pwm resolution for the phase and frequency correct pwm mode can be defined by either icrn or ocrna. the minimum resolution allo w ed is 2-bit (icrn or ocrna set to 0x0003), and f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------- - = 133 7593l?avr?09/12 at90usb64/128 the maximum resolution is 16-bit (icrn or ocrn a set to max). the pwm resolution in bits can be calculated using the follo w ing equation: in phase and frequency correct pwm mode the counter is incremented until the counter v alue matches either the v alue in icrn (wgmn3:0 = 8), or the v alue in ocrna (wgmn3:0 = 9). the counter has then reached the top and changes the count direction. the tcntn v alue w ill be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is sho w n on figure 15-9 . the figure sho w s phase and frequency correct pwm mode w hen ocrna or icrn is used to define top. the tcntn v alue is in the timing dia- gram sho w n as a histogram for illustrating the dual-s lope operation. the di agram includes non- in v erted and in v erted pwm outputs. the small horizontal line marks on the tcntn slopes repre- sent compare matches bet w een ocrnx and tcntn. the ocnx interrupt flag w ill be set w hen a compare match occurs. figure 15-9. phase and frequency correct pwm mode, timing diagram. the timer/counter o v erflo w flag (tovn) is set at the same timer clock cycle as the ocrnx registers are updated w ith the double buffer v alue (at bottom). when either ocrna or icrn is used for defining the top v alue, the ocna or icfn flag set w hen tcntn has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom v alue. when changing the top v alue the program must ensure that the ne w top v alue is higher or equal to the v alue of all of the compare registers. if the top v alue is lo w er than any of the compare registers, a compare match w ill ne v er occur bet w een the tcntn and the ocrnx. as figure 15-9 sho w s the output generated is, in contrast to the phase correct mode, symmetri- cal in all periods. since the ocrnx registers are updated at bottom, the length of the rising and the falling slopes w ill al w ays be equal. this gi v es symmetrical output pulses and is therefore frequency correct. r pfcpwm top 1 + () log 2 () log ---------------------------------- - = ocrnx/top updateand tovn interrupt flag s et (interrupt on bottom) ocna interrupt flag s et or icfn interrupt flag s et (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 134 7593l?avr?09/12 at90usb64/128 using the icrn register for defining top w orks w ell w hen using fixed top v alues. by using icrn, the ocrna register is free to be used for generating a pwm output on ocna. ho w e v er, if the base pwm frequency is acti v ely changed by changing the top v alue, using the ocrna as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compare units allo w generation of pwm w a v e- forms on the ocnx pins. setting the comnx1:0 bits to t w o w ill produce a non-in v erted pwm and an in v erted pwm output can be generated by setting the comnx1:0 to three (see table 15-3 on page 138 ). the actual ocnx v alue w ill only be v isible on the port pin if the data direction for the port pin is set as output (ddr_ocnx). the pwm w a v eform is generated by setting (or clearing) the ocnx register at the compare match bet w een ocrnx and tcntn w hen the counter incre- ments, and clearing (or setting) the ocnx register at compare match bet w een ocrnx and tcntn w hen the counter decrements. the pwm frequency for the output w hen using phase and frequency correct pwm can be calculated by the follo w ing equation: the n v ariable represents the prescaler di v ider (1, 8, 64, 256, or 1024). the extreme v alues for the ocrnx register represents special cases w hen generating a pwm w a v eform output in the phase correct pwm mode. if the ocrnx is set equal to bottom the output w ill be continuously lo w and if set equal to top the output w ill be set to high for non- in v erted pwm mode. for in v erted pwm the output w ill ha v e the opposite logic v alues. if ocr1a is used to define the top v alue (wgm13:0 = 9) and com1a1:0 = 1, the oc1a output w ill toggle w ith a 50% duty cycle. 15.9 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk tn ) is therefore sho w n as a clock enable signal in the follo w ing figures. the figures include information on w hen interrupt flags are set, and w hen the ocrnx register is updated w ith the ocrnx buffer v alue (only for modes utilizing double buffering). figure 15-10 sho w s a timing diagram for the setting of ocfnx. figure 15-10. timer/counter timing diagram, setting of ocfnx, no prescaling. figure 15-11 on page 135 sho w s the same timing data, but w ith the prescaler enabled. f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------- - = clk tn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 135 7593l?avr?09/12 at90usb64/128 figure 15-11. timer/counter timing diagram, setting of ocfnx, w ith prescaler (f clk_i/o /8). figure 15-12 sho w s the count sequence close to top in v arious modes. when using phase and frequency correct pwm mode the ocrnx register is updated at bottom. the timing diagrams w ill be the same, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the tovn flag at bottom. figure 15-12. timer/counter timing diagram, no prescaling. figure 15-13 on page 136 sho w s the same timing data, but w ith the prescaler enabled. ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o / 8 ) tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o 136 7593l?avr?09/12 at90usb64/128 figure 15-13. timer/counter timing diagram, w ith prescaler (f clk_i/o /8). 15.10 16-bit timer/counter register description 15.10.1 tccr1a ? timer/counter1 control register a 15.10.2 tccr3a ? timer/counter3 control register a ? bit 7:6 ? comna1:0: compare output mode for channel a ? bit 5:4 ? comnb1:0: compare output mode for channel b ? bit 3:2 ? comnc1:0: compare output mode for channel c the comna1:0, comnb1:0, and comnc1:0 control the output compare pins (ocna, ocnb, and ocnc respecti v ely) beha v ior. if one or both of the comna1:0 bits are w ritten to one, the ocna output o v errides the normal port functionality of the i/o pin it is connected to. if one or both of the comnb1:0 bits are w ritten to one, the ocnb output o v errides the normal port func- tionality of the i/o pin it is connected to. if one or both of the comnc1:0 bits are w ritten to one, the ocnc output o v errides the normal port functionality of the i/o pin it is connected to. ho w - e v er, note that the data direction register (ddr) bit corresponding to the ocna, ocnb or ocnc pin must be set in order to enable the output dri v er. tovn (fpwm) and icf n (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o / 8 ) bit 76543210 com1a1 com1a0 com1b1 com1b0 co m1c1 com1c0 wgm11 wgm10 tccr1a read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 com3a1 com3a0 com3b1 com3b0 co m3c1 com3c0 wgm31 wgm30 tccr3a read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 137 7593l?avr?09/12 at90usb64/128 when the ocna, ocnb or ocnc is connected to the pin, the function of the comnx1:0 bits is dependent of the wgmn3:0 bits setting. table 15-1 sho w s the comnx1:0 bit functionality w hen the wgmn3:0 bits are set to a normal or a ctc mode (non-pwm). table 15-2 sho w s the comnx1:0 bit functionality w hen the wgmn3:0 bits are set to the fast pwm mode. note: a special case occurs w hen ocrna/ocrnb/ocrnc equals top and comna1/comnb1/comnc1 is set. in this case t he compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 104. for more details. table 15-3 on page 138 sho w s the comnx1:0 bit functionality w hen the wgmn3:0 bits are set to the phase correct and frequency correct pwm mode. table 15-1. compare output mode, non-pwm. comna1/comnb1/ comnc1 comna0/comnb0/ comnc0 description 00 normal port operation, ocna/ocnb/ocnc disconnected. 0 1 toggle ocna/ocnb/ocnc on compare match. 10 clear ocna/ocnb/ocnc on compare match (set output to lo w le v el). 11 set ocna/ocnb/ocnc on compare match (set output to high le v el). table 15-2. compare output mode, fast pwm. comna1/comnb1/ comnc0 comna0/comnb0/ comnc0 description 00 normal port operation, ocna/ocnb/ocnc disconnected. 01 wgm13:0 = 14 or 15: toggle oc1a on compare match, oc1b and oc1c disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b/oc1c disconnected. 10 clear ocna/ocnb/ocnc on compare match, set ocna/ocnb/ocnc at top 11 set ocna/ocnb/ocnc on compare match, clear ocna/ocnb/ocnc at top 138 7593l?avr?09/12 at90usb64/128 note: a special case occurs w hen ocrna/ocrnb/ocrnc equals top and comna1/comnb1//comnc1 is set. see ?phase correct pwm mode? on page 106. for more details. ? bit 1:0 ? wgmn1:0: waveform generation mode combined w ith the wgmn3:2 bits found in the tccrnb register, these bits control the counting sequence of the counter, the source for maximum (top) counter v alue, and w hat type of w a v e- form generation to be used, see table 15-4 on page 138 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes. ( see ?modes of operation? on page 103. ). table 15-3. compare output mode, phase correct and phase and frequency correct pwm. comna1/comnb/ comnc1 comna0/comnb0/ comnc0 description 00 normal port operation, ocna/ocnb/ocnc disconnected. 01 wgm13:0 = 8, 9 10 or 11: toggle oc1a on compare match, oc1b and oc1c disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b/oc1c disconnected. 10 clear ocna/ocnb/ocnc on compare match w hen up-counting. set ocna/ocnb/ocnc on compare match w hen counting do w n. 11 set ocna/ocnb/ocnc on compare match w hen up-counting. clear ocna/ocnb/ocnc on compare match w hen counting do w n. table 15-4. wa v eform generation mode bit description (1) . mode wgmn3 wgmn2 (ctcn) wgmn1 (pwmn1) wgmn0 (pwmn0) timer/counter mode of operation top update of ocrn x at tovn flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 3 0 0 1 1 pwm, phase correct, 10-bit 0x03ff top bottom 4 0 1 0 0 ctc ocrna immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff top top 6 0 1 1 0 fast pwm, 9-bit 0x01ff top top 7 0 1 1 1 fast pwm, 10-bit 0x03ff top top 81000 pwm, phase and frequency correct icrn bottom bottom 91001 pwm, phase and frequency correct ocrna bottom bottom 10 1 0 1 0 pwm, phase correct icrn top bottom 139 7593l?avr?09/12 at90usb64/128 note: 1. the ctcn and pwmn1:0 bit definition names are obsolete. use the wgmn2:0 definitions. ho w e v er, the functionality and location of these bits are compatible w ith pre v ious v ersions of the timer. 15.10.3 tccr1b ? timer/counter1 control register b 15.10.4 tccr3b ? timer/counter3 control register b ? bit 7 ? icncn: input capture noise canceler setting this bit (to one) acti v ates the input capture noise canceler. when the noise canceler is acti v ated, the input from the input capture pin (icpn) is filtered. the filter function requires four successi v e equal v alued samples of the icpn pin for changing its output. the input capture is therefore delayed by four oscillator cycles w hen the noise canceler is enabled. ? bit 6 ? icesn: input capture edge select this bit selects w hich edge on the input capture pin (icpn) that is used to trigger a capture e v ent. when the icesn bit is w ritten to zero, a falling (negati v e) edge is used as trigger, and w hen the icesn bit is w ritten to one, a rising (positi v e) edge w ill trigger the capture. when a capture is triggered according to the icesn setting, the counter v alue is copied into the input capture register (icrn). the e v ent w ill also set the input capture flag (icfn), and this can be used to cause an input capture interrupt, if this interrupt is enabled. when the icrn is used as top v alue (see description of the wgmn3:0 bits located in the tccrna and the tccrnb register), the icpn is disconnected and consequently the input cap- ture function is disabled. ? bit 5 ? reserved bit this bit is reser v ed for future use. fo r ensuring compatibility w ith future de v ices, this bit must be w ritten to zero w hen tccrnb is w ritten. ? bit 4:3 ? wgmn3:2: waveform generation mode see tccrna register description. 11 1 0 1 1 pwm, phase correct ocrna top bottom 12 1 1 0 0 ctc icrn immediate max 131101(reser v ed) ? ? ? 14 1 1 1 0 fast pwm icrn top top 15 1 1 1 1 fast pwm ocrna top top table 15-4. wa v eform generation mode bit description (1) . (continued) mode wgmn3 wgmn2 (ctcn) wgmn1 (pwmn1) wgmn0 (pwmn0) timer/counter mode of operation top update of ocrn x at tovn flag set on bit 76543 210 icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/ w rite r/w r/w r r/w r/w r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 bit 76543210 icnc3 ices3 ? wgm33 wgm32 cs32 cs31 cs30 tccr3b read/ w rite r/w r/w r r/w r/w r/w r/w r/w initial v alue00000000 140 7593l?avr?09/12 at90usb64/128 ? bit 2:0 ? csn2:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see figure 14-8 on page 107 and figure 14-9 on page 108 . if external pin modes are used for the timer/countern, transitions on the tn pin w ill clock the counter e v en if the pin is configured as an output. this feature allo w s soft w are control of the counting. 15.10.5 tccr1c ? timer/counter1 control register c 15.10.6 tccr3c ? timer/counter3 control register c ? bit 7 ? focna: force output compare for channel a ? bit 6 ? focnb: force output compare for channel b ? bit 5 ? focnc: force output compare for channel c the focna/focnb/focnc bits are only acti v e w hen the wgmn3:0 bits specifies a non-pwm mode. when w riting a logical one to the focna/focnb/focnc bit, an immediate compare match is forced on the w a v eform generation unit. the ocna/ocnb/ocnc output is changed according to its comnx1:0 bits setting. note that the focna/focnb/focnc bits are imple- mented as strobes. therefore it is the v alue present in the comnx1:0 bits that determine the effect of the forced compare. a focna/focnb/focnc strobe w ill not generate any interrupt nor w ill it clear the timer in clear timer on compare match (ctc) mode using ocrna as top. the focna/focnb/focnb bits are al w ays read as zero. ? bit 4:0 ? reserved bits these bits are reser v ed for future use. for ensuring compatibility w ith future de v ices, these bits must be w ritten to zero w hen tccrnc is w ritten. table 15-5. clock select bit description. csn2 csn1 csn0 description 0 0 0 no clock source. (timer/counter stopped) 001clk i/o /1 (no prescaling 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on tn pin. clock on falling edge 1 1 1 external clock source on tn pin. clock on rising edge bit 7654 3 210 foc1a foc1b foc1c ? ? ? ? ? tccr1c read/ w ritewwwr r rrr initial v alue 0 0 0 0 0 0 0 0 bit 7654 3 210 foc3a foc3b foc3c ? ? ? ? ? tccr3c read/ w ritewwwr r rrr initial v alue 0 0 0 0 0 0 0 0 141 7593l?avr?09/12 at90usb64/128 15.10.7 tcnt1h and tcnt1l ? timer/counter1 15.10.8 tcnt3h and tcnt3l ? timer/counter3 the t w o timer/counter i/o locations (tcntnh and tcntnl, combined tcntn) gi v e direct access, both for read and for w rite operations, to the timer/counter unit 16-bit counter. to ensure that both the high and lo w bytes are read and w ritten simultaneously w hen the cpu accesses these registers, the access is perfo rmed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 117. modifying the counter (tcntn) w hile the counter is running introduces a risk of missing a com- pare match bet w een tcntn and one of the ocrnx registers. writing to the tcntn re gister blocks (remo v es) the compare match on the follo w ing timer clock for all compare units. 15.10.9 ocr1ah and ocr1al ? ou tput compare register 1 a 15.10.10 ocr1bh and ocr1bl ? ou tput compare register 1 b 15.10.11 ocr1ch and ocr1cl ? ou tput compare register 1 c bit 76543210 tcnt1[15:8] tcnt1h tcnt1[7:0] tcnt1l read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 tcnt3[15:8] tcnt3h tcnt3[7:0] tcnt3l read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ocr1a[15:8] ocr1ah ocr1a[7:0] ocr1al read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ocr1b[15:8] ocr1bh ocr1b[7:0] ocr1bl read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ocr1c[15:8] ocr1ch ocr1c[7:0] ocr1cl read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 142 7593l?avr?09/12 at90usb64/128 15.10.12 ocr3ah and ocr3al ? ou tput compare register 3 a 15.10.13 ocr3bh and ocr3bl ? ou tput compare register 3 b 15.10.14 ocr3ch and ocr3cl ? ou tput compare register 3 c the output compare registers contain a 16-bit v alue that is continuously compared w ith the counter v alue (tcntn). a match can be used to generate an output compare interrupt, or to generate a w a v eform output on the ocnx pin. the output compare registers are 16-bit in size. to ensure that both the high and lo w bytes are w ritten simultaneously w hen the cpu w rites to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 117. 15.10.15 icr1h and icr1l ? input capture register 1 15.10.16 icr3h and icr3l ? input capture register 3 the input capture is updated w ith the counter (tcntn) v alue each time an e v ent occurs on the icpn pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top v alue. the input capture register is 16-bit in size. to ensure that both the high and lo w bytes are read simultaneously w hen the cpu accesses these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers. see ?accessing 16-bit registers? on page 117. bit 76543210 ocr3a[15:8] ocr3ah ocr3a[7:0] ocr3al read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ocr3b[15:8] ocr3bh ocr3b[7:0] ocr3bl read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ocr3c[15:8] ocr3ch ocr3c[7:0] ocr3cl read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 icr1[15:8] icr1h icr1[7:0] icr1l read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 icr3[15:8] icr3h icr3[7:0] icr3l read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 143 7593l?avr?09/12 at90usb64/128 15.10.17 timsk1 ? timer/count er1 interrupt mask register 15.10.18 timsk3 ? timer/count er3 interrupt mask register ? bit 5 ? icien: timer/countern, input capture interrupt enable when this bit is w ritten to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern input capture interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 68 ) is executed w hen the icfn flag, located in tifrn, is set. ? bit 3 ? ocienc: timer/countern, output compare c match interrupt enable when this bit is w ritten to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern output compare c match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 68 ) is executed w hen the ocfnc flag, located in tifrn, is set. ? bit 2 ? ocienb: timer/countern, output compare b match interrupt enable when this bit is w ritten to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern output compare b match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 68 ) is executed w hen the ocfnb flag, located in tifrn, is set. ? bit 1 ? ociena: timer/countern, output compare a match interrupt enable when this bit is w ritten to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern output compare a match interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 68 ) is executed w hen the ocfna flag, located in tifrn, is set. ? bit 0 ? toien: timer/countern, overflow interrupt enable when this bit is w ritten to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/countern o v erflo w interrupt is enabled. the corresponding interrupt vector ( see ?interrupts? on page 68 ) is executed w hen the tovn flag, located in tifrn, is set. 15.10.19 tifr1 ? timer/counte r1 interrupt flag register 15.10.20 tifr3 ? timer/counte r3 interrupt flag register bit 765432 1 0 ? ?icie1 ? ocie1c ocie1b ocie1a toie1 timsk1 read/ w rite r r r/w r r/w r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 bit 765432 1 0 ? ?icie3 ? ocie3c ocie3b ocie3a toie3 timsk3 read/ w rite r r r/w r r/w r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 bit 76543210 ? ?icf1 ? ocf1c ocf1b ocf1a tov1 tifr1 read/ w rite r r r/w r r/w r/w r/w r/w initial v alue00000000 bit 76543210 ? ?icf3 ? ocf3c ocf3b ocf3a tov3 tifr3 read/ w rite r r r/w r r/w r/w r/w r/w initial v alue00000000 144 7593l?avr?09/12 at90usb64/128 ? bit 5 ? icfn: timer/count ern, input capture flag this flag is set w hen a capture e v ent occurs on the icpn pin. when the input capture register (icrn) is set by the wgmn3:0 to be used as the top v alue, the icfn flag is set w hen the coun- ter reaches the top v alue. icfn is automatically cleared w hen the input capture interrupt vector is executed. alternati v ely, icfn can be cleared by w riting a logic one to its bit location. ? bit 3? ocfnc: timer/countern, output compare c match flag this flag is set in the timer cl ock cycle after the counter (tcntn) v alue matches the output compare register c (ocrnc). note that a forced output compare (focnc) strobe w ill not set the ocfnc flag. ocfnc is automatically cleared w hen the output compare match c interrupt vector is exe- cuted. alternati v ely, ocfnc can be cleared by w riting a logic one to its bit location. ? bit 2 ? ocfnb: timer/counter1, output compare b match flag this flag is set in the timer cl ock cycle after the counter (tcntn) v alue matches the output compare register b (ocrnb). note that a forced output compare (focnb) strobe w ill not set the ocfnb flag. ocfnb is automatically cleared w hen the output compare match b interrupt vector is exe- cuted. alternati v ely, ocfnb can be cleared by w riting a logic one to its bit location. ? bit 1 ? ocf1a: timer/counter1, output compare a match flag this flag is set in the timer clock cycle after the counter (tcntn v alue matches the output com- pare register a (ocrna). note that a forced output compare (focna) strobe w ill not set the ocfna flag. ocfna is automatically cleared w hen the output compare match a interrupt vector is exe- cuted. alternati v ely, ocfna can be cleared by w riting a logic one to its bit location. ? bit 0 ? tovn: timer/countern, overflow flag the setting of this flag is dependent of the wgmn3:0 bits setting. in normal and ctc modes, the tovn flag is set w hen the timer o v erflo w s. refer to table 15-4 on page 138 for the tovn flag beha v ior w hen using another wgmn3:0 bit setting. tovn is automatically cleared w hen the timer/countern o v erflo w interrupt vector is executed. alternati v ely, tovn can be cleared by w riting a logic one to its bit location. 145 7593l?avr?09/12 at90usb64/128 16. 8-bit timer/counter2 with pwm and asynchronous operation timer/counter2 is a general purpose, single channel, 8-bit timer/counter module. the main features are: ? single channel counter ? clear timer on compare match (auto reload) ? glitch-free, phase correct pulse width modulator (pwm) ? frequency generator ? 10-bit clock prescaler ? overflow and compare match interrup t sources (tov2, ocf2a and ocf2b) ? allows clocking from external 32khz watch crystal independent of the i/o clock 16.1 overview a simplified block diagram of the 8-bit timer/counter is sho w n in figure 16-1. for the actual placement of i/o pins, see ?pin configurations? on page 3 . cpu accessible i/o registers, includ- ing i/o bits and i/o pins, are sho w n in bold. the de v ice-specific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 156 . the po w er reduction timer/counter2 bit, prtim2, in ?prr0 ? po w er reduction register 0? on page 54 must be w ritten to zero to enable timer/counter2 module. figure 16-1. 8-bit timer/counter, block diagram. timer/co u nter data b u s ocrna ocrnb = = tcntn w a veform gener a tion w a veform gener a tion ocna ocnb = fixed top v a l u e control logic = 0 top bottom co u nt cle a r direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb clk tn a ss rn synchroniz a tion u nit pre s c a ler t/c o s cill a tor clk i/o clk asy as ynchrono us mode s elect (asn) synchronized s t a t us fl a g s to s c1 to s c2 st a t us fl a g s clk i/o 146 7593l?avr?09/12 at90usb64/128 16.1.1 registers the timer/counter (tcnt2) and output compare register (ocr2a and ocr2b) are 8-bit reg- isters. interrupt request (abbre v iated to int.req.) signals are all v isible in the timer interrupt flag register (tifr2). all interrupts are indi v idually masked w ith the timer interrupt mask register (timsk2). tifr2 and timsk2 are not sho w n in the figure. the timer/counter can be clocked internally, v ia the prescaler, or asynchronously clocked from the tosc1/2 pins, as detailed later in this section. the asynchronous operation is controlled by the asynchronous status re gister (assr). the clock select logic block controls w hich clock source the timer/counter uses to increment (or decrement) its v alue. the timer/counter is inac- ti v e w hen no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare register (ocr2a and ocr2b) are compared w ith the timer/counter v alue at all times. the result of the compare can be used by the wa v eform gen- erator to generate a pwm or v ariable frequency output on the output compare pins (oc2a and oc2b). see ?output compare unit? on page 147. for details. the compare match e v ent w ill also set the compare flag (ocf2a or ocf2b) w hich can be used to generate an output compare interrupt request. 16.1.2 definitions many register and bit references in this document are w ritten in general form. a lo w er case ?n? replaces the timer/counter number, in this case 2. ho w e v er, w hen using the register or bit defines in a program, the precise form must be used, that is, tcnt2 for accessing timer/counter2 counter v alue and so on. the definitions in the table belo w are also used extensi v ely throughout the section. 16.2 timer/counter clock sources the timer/counter can be clocked by an internal synchronous or an external asynchronous clock source. the clock source clk t2 is by default equal to the mcu clock, clk i/o . when the as2 bit in the assr register is w ritten to logic one, the clock source is taken from the timer/counter oscillator connected to tosc1 and tosc2. fo r details on asynchronous operation, see ?assr ? asynchronous status register? on page 161 . for details on clock sour ces and prescaler, see ?timer/counter prescaler? on page 164 . 16.3 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 16-2 on page 147 sho w s a block diagram of the counter and its surrounding en v ironment. bottom the counter reaches the bottom w hen it becomes zero (0x00). max the counter reaches its maximum w hen it becomes 0xff (decimal 255). top the counter reaches the top w hen it becomes equal to the highest v alue in the count sequence. the top v alue can be assigned to be the fixed v alue 0xff (max) or the v alue stored in the ocr2a register. the assignment is dependent on the mode of operation. 147 7593l?avr?09/12 at90usb64/128 figure 16-2. counter unit block diagram. signal description (internal signals): count increment or decrement tcnt2 by 1. direction selects bet w een increment and decrement. clear clear tcnt2 (set all bits to zero). clk tn timer/counter clock, referred to as clk t2 in the follo w ing. top signalizes that tcnt2 has reached maximum v alue. bottom signalizes that tcnt2 has reached minimum v alue (zero). depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal clock source, selected by the clock select bits (cs22:0). w hen no clock source is selected (cs22:0 = 0) the timer is stopped. ho w e v er, the tcnt2 v alue can be accessed by the cpu, regardless of w hether clk t2 is present or not. a cpu w rite o v errides (has priority o v er) all counter clear or count operations. the counting sequence is determined by the setting of the wgm21 and wgm20 bits located in the timer/counter control register (tccr2a) and the wgm22 located in the timer/counter control register b (tccr2b). there are close connections bet w een ho w the counter beha v es (counts) and ho w w a v eforms are generated on the output compare outputs oc2a and oc2b. for more details about ad v anced counting sequences and w a v eform generation, see ?modes of operation? on page 150 . the timer/counter o v erflo w flag (tov2) is set according to the mode of operation selected by the wgm22:0 bits. tov2 can be used for generating a cpu interrupt. 16.4 output compare unit the 8-bit comparator continuously compares tcnt2 w ith the output compare register (ocr2a and ocr2b). whene v er tcnt2 equals ocr2a or ocr2b, the comparator signals a match. a match w ill set the output compare flag (ocf2a or ocf2b) at the next timer clock cycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared w hen the interrupt is exe- cuted. alternati v ely, the output compare flag can be cleared by soft w are by w riting a logical one to its i/o bit location. the wa v eform generator uses the match signal to generate an output according to operating mode set by the wgm22:0 bits and compare output mode (com2x1:0) bits. the max and bottom signals are used by the wa v eform generator for handling the special cases of the extreme v alues in some modes of operation ( ?modes of operation? on page 150 ). figure 15-10 on page 134 sho w s a block diagram of the output compare unit. data b u s tcntn control logic count tovn (int.re q .) top bottom direction clear tosc1 t/c oscillator tosc2 prescaler clk i/o clk tn 148 7593l?avr?09/12 at90usb64/128 figure 16-3. output compare unit, block diagram. the ocr2x register is double buffered w hen using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr2x compare register to either top or bottom of the counting sequence. the synchronization pre v ents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr2x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr2x buffer register, and if double buffering is dis- abled the cpu w ill access the ocr2x directly. 16.4.1 force output compare in non-pwm w a v eform generation modes, the match output of the comparator can be forced by w riting a one to the force output compare (foc2x) bit. forcing compare match w ill not set the ocf2x flag or reload/clear the timer, but the oc2x pin w ill be updated as if a real compare match had occurred (the com2x1:0 bits settings define w hether the oc2x pin is set, cleared or toggled). 16.4.2 compare match bloc king by tcnt2 write all cpu w rite operations to the tcnt2 register w ill block any compare matc h that occurs in the next timer clock cycle, e v en w hen the timer is stopped. this feature allo w s ocr2x to be initial- ized to the same v alue as tcnt2 w ithout triggering an interrupt w hen the timer/counter clock is enabled. 16.4.3 using the output compare unit since w riting tcnt2 in any mode of operation w ill block all compare matches for one timer clock cycle, there are risks in v ol v ed w hen changing tcnt2 w hen using the output compare channel, independently of w hether the timer/counter is running or not. if the v alue w ritten to tcnt2 equals the ocr2x v alue, the compare match w ill be missed, resulting in incorrect w a v eform generation. similarly, do not w rite the tcnt2 v alue equal to bottom w hen the counter is do w ncounting. ocfn x (int.re q .) = ( 8 -bit comparator) ocrnx ocnx data b u s tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 149 7593l?avr?09/12 at90usb64/128 the setup of the oc2x should be performed before setting the data direction register for the port pin to output. the easiest w ay of setting the oc2x v alue is to use the force output com- pare (foc2x) strobe bit in normal mode. the oc2x register keeps its v alue e v en w hen changing bet w een wa v eform generation modes. be a w are that the com2x1:0 bits are not double buffered together w ith the compare v alue. changing the com2x1:0 bits w ill take effect immediately. 16.5 compare match output unit the compare output mode (com2x1:0) bits ha v e t w o functions. the wa v eform generator uses the com2x1:0 bits for defining the output compare (oc2x) state at the next compare match. also, the com2x1:0 bits control the oc2x pin output source. figure 16-4 sho w s a simplified schematic of the logic affected by the com2x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are sho w n in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com2x1:0 bits are sho w n. when referring to the oc2x state, the reference is for the internal oc2x register, not the oc2x pin. figure 16-4. compare match output unit, schematic. the general i/o port function is o v erridden by the output compare (oc2x) from the wa v eform generator if either of the com2x1:0 bits are set. ho w e v er, the oc2x pin direction (input or out- put) is still controlled by the da ta direction register (ddr) for th e port pin. the data direction register bit for the oc2x pin (ddr_oc2x) mu st be set as output before the oc2x v alue is v isi- ble on the pin. the port o v erride function is independent of the wa v eform generation mode. the design of the output compare pin logic allo w s initialization of the oc2x state before the out- put is enabled. note that some com2x1:0 bit settings are reser v ed for certain modes of operation. see ?8-bit timer/counter register description? on page 156. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data b u s focnx clk i/o 150 7593l?avr?09/12 at90usb64/128 16.5.1 compare output mode and waveform generating the wa v eform generator uses the com2x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com2x1:0 = 0 tells the wa v eform generator that no action on the oc2x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 16-4 on page 157 . for fast pwm mode, refer to table 16-5 on page 158 , and for phase correct pwm refer to table 16-6 on page 158 . a change of the com2x1:0 bits state w ill ha v e effect at the first compare match after the bits are w ritten. for non-pwm modes, the action can be forced to ha v e immediate effect by using the foc2x strobe bits. 16.6 modes of operation the mode of operation, that is, the beha v ior of the timer/counter and the output compare pins, is defined by the combination of the wa v eform generation mode (wgm22:0) and compare out- put mode (com2x1:0) bits. the compare output mode bits do not affect the counting sequence, w hile the wa v eform generation mode bits do. the com2x1:0 bits control w hether the pwm out- put generated should be in v erted or not (in v erted or non-in v erted pwm). for non-pwm modes the com2x1:0 bits control w hether the output should be set, cleared, or toggled at a compare match ( see ?compare match output unit? on page 149 ). for detailed timing information refer to section ?timer/counter timing diagrams? on page 154 . 16.6.1 normal mode the simplest mode of operation is the normal mode (wgm22:0 = 0). in this mode the counting direction is al w ays up (incrementing), and no counter cl ear is performed. the counter simply o v erruns w hen it passes its maximum 8-bit v alue (top = 0xff) and then restarts from the bot- tom (0x00). in normal operation the timer/counter o v erflo w flag (tov2) w ill be set in the same timer clock cycle as the tcnt2 becomes zero. the tov2 flag in this case beha v es like a ninth bit, except that it is only set, not cleared. ho w e v er, combined w ith the timer o v erflo w interrupt that automatically clears the tov2 flag, the timer resolution can be increased by soft w are. there are no special cases to consider in the normal mode, a ne w counter v alue can be w ritten anytime. the output compare unit can be used to generate interrupts at some gi v en time. using the out- put compare to generate w a v eforms in normal mode is not recommended, since this w ill occupy too much of the cpu time. 16.6.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm 22:0 = 2), the ocr2a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero w hen the counter v alue (tcnt2) matches the ocr2a. the ocr2a defines the top v alue for the counter, hence also its resolution. this mode allo w s greater control of the compare match output frequency. it also simplifies the operation of counting external e v ents. the timing diagram for the ctc mode is sho w n in table 16-5 on page 151 . the counter v alue (tcnt2) increases until a compare match occurs bet w een tcnt2 and ocr2a, and then coun- ter (tcnt2) is cleared. 151 7593l?avr?09/12 at90usb64/128 figure 16-5. ctc mode, timing diagram. an interrupt can be generated each time the counter v alue reaches the top v alue by using the ocf2a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top v alue. ho w e v er, changing top to a v alue close to bottom w hen the counter is run- ning w ith none or a lo w prescaler v alue must be done w ith care since the ctc mode does not ha v e the double buffering feature. if the ne w v alue w ritten to ocr2a is lo w er than the current v alue of tcnt2, the counter w ill miss the compare match. the counter w ill then ha v e to count to its maximum v alue (0xff) and w rap around starting at 0x00 before the compare match can occur. for generating a w a v eform output in ctc mode, the oc2a output can be set to toggle its logical le v el on each compare match by setting the compare output mode bits to toggle mode (com2a1:0 = 1). the oc2a v alue w ill not be v isible on the port pin unless the data direction for the pin is set to output. the w a v eform generated w ill ha v e a maximum frequency of f oc2a = f clk_i/o /2 w hen ocr2a is set to zero (0x00). the w a v eform frequency is defined by the follo w ing equation: the n v ariable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). as for the normal mode of operation, the tov2 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 16.6.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm22:0 = 3 or 7) pro v ides a high fre- quency pwm w a v eform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to top then restarts from bot- tom. top is defined as 0xff w hen wgm22:0 = 3, and ocr2a w hen mgm22:0 = 7. in non- in v erting compare output mode, the output compare (oc2x) is cleared on the compare match bet w een tcnt2 and ocr2x, and set at bottom. in in v erting compare output mode, the out- put is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be t w ice as high as the phase correct pwm mode that uses dual-slope operation. this high frequency makes the fast pwm mode w ell suited for po w er regulation, rectification, and dac applications. high frequency allo w s physically small sized external components (coils, capacitors), and therefore reduces total system cost. tcntn ocnx (toggle) ocnx interrupt flag s et 1 4 period 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------- - = 152 7593l?avr?09/12 at90usb64/128 in fast pwm mode, the counter is incremented until the counter v alue matches the top v alue. the counter is then cleared at the follo w ing timer clock cycle. the timing diagram for the fast pwm mode is sho w n in figure 16-6 . the tcnt2 v alue is in the timing diagram sho w n as a his- togram for illustrating the single-slope operation. the diagram includes non-in v erted and in v erted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches bet w een ocr2x and tcnt2. figure 16-6. fast pwm mode, timing diagram. the timer/counter o v erflo w flag (tov2) is set each time the counter reaches top. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare v alue. in fast pwm mode, the compare unit allo w s generation of pwm w a v eforms on the oc2x pin. setting the com2x1:0 bits to t w o w ill produce a non-in v erted pwm and an in v erted pwm output can be generated by setting the com2x1:0 to three. top is defined as 0xff w hen wgm2:0 = 3, and ocr2a w hen wgm2:0 = 7 (see table 16-2 on page 157 ). the actual oc2x v alue w ill only be v isible on the port pin if the data direction for the port pin is set as output. the pwm w a v e- form is generated by setting (or clearing) the oc2x register at the compare match bet w een ocr2x and tcnt2, and clearing (or setting) the oc2x register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the follo w ing equation: the n v ariable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme v alues for the ocr2a register represent special cases w hen generating a pwm w a v eform output in the fast pwm mode. if the ocr2a is set equal to bottom, the output w ill be a narro w spike for each max+1 timer clock cycle. setting the ocr2a equal to max w ill result in a constantly high or lo w output (depending on the polarity of the output set by the com2a1:0 bits.) a frequency ( w ith 50% duty cycle) w a v eform output in fast pwm mode can be achie v ed by set- ting oc2x to toggle its logical le v el on each compare match (com2x1:0 = 1). the w a v eform tcntn ocrnx update and tovn interrupt flag s et 1 period 2 3 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag s et 4 5 6 7 f ocnxpwm f clk_i/o n 256 ? ------------------ = 153 7593l?avr?09/12 at90usb64/128 generated w ill ha v e a maximum frequency of f oc2 = f clk_i/o /2 w hen ocr2a is set to zero. this fea- ture is similar to the oc2a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. 16.6.4 phase correct pwm mode the phase correct pwm mode (wgm22:0 = 1 or 5) pro v ides a high resolution phase correct pwm w a v eform generation option. the phase corr ect pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bot- tom. top is defined as 0xff w hen wgm22:0 = 1, and ocr2a w hen mgm22:0 = 5. in non- in v erting compare output mode, the output compare (oc2x) is cleared on the compare match bet w een tcnt2 and ocr2x w hile upcounting, and set on the compare match w hile do w ncount- ing. in in v erting output compare mode, the operation is in v erted. the dual-slope operation has lo w er maximum operation frequency than single slope operation. ho w e v er, due to the symmet- ric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. in phase correct pwm mode the counter is incremented until the counter v alue matches top. when the counter reaches top, it c hanges the count direction. the tcnt2 v alue w ill be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is sho w n on figure 16-7 . the tcnt2 v alue is in the timing diagram sho w n as a histogram for illustrating the dual-slope operation. the diagram includes non-in v erted and in v erted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches bet w een ocr2x and tcnt2. figure 16-7. phase correct pwm mode, timing diagram. the timer/counter o v erflo w flag (tov2) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom v alue. in phase correct pwm mode, the compare unit allo w s generation of pwm w a v eforms on the oc2x pin. setting the com2x1:0 bits to t w o w ill produce a non-in v erted pwm. an in v erted pwm tovn interrupt flag s et ocnx interrupt flag s et 1 2 3 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update 154 7593l?avr?09/12 at90usb64/128 output can be generated by setting the com2x1:0 to three. top is defined as 0xff w hen wgm2:0 = 3, and ocr2a w hen mgm2:0 = 7 (see table 16-3 on page 157 ). the actual oc2x v alue w ill only be v isible on the port pin if the data direction for the port pin is set as output. the pwm w a v eform is generated by clearing (or setting) the oc2x register at the compare match bet w een ocr2x and tcnt2 w hen the counter increments, and setting (or clearing) the oc2x register at compare match bet w een ocr2x and tcnt2 w hen the counter decrements. the pwm frequency for the output w hen using phase correct pwm can be calculated by the follo w - ing equation: the n v ariable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme v alues for the ocr2a register represent special cases w hen generating a pwm w a v eform output in the phase correct pwm mode. if the ocr2a is set equal to bottom, the output w ill be continuously lo w and if set equal to max the output w ill be continuously high for non-in v erted pwm mode. for in v erted pwm the output w ill ha v e the opposite logic v alues. at the v ery start of period 2 in figure 16-7 on page 153 ocnx has a transition from high to lo w e v en though there is no compare match. the point of this transition is to guarantee symmetry around bottom. there are t w o cases that gi v e a transition w ithout compare match. ? ocr2a changes its v alue from max, like in figure 16-7 on page 153 . when the ocr2a v alue is max the ocn pin v alue is the same as the result of a do w n-counting compare match. to ensure symmetry around bottom the ocn v alue at max must correspond to the result of an up-counting compare match ? the timer starts counting from a v alue higher than the one in ocr2a, and for that reason misses the compare match and hence the ocn change that w ould ha v e happened on the w ay up 16.7 timer/counter timing diagrams the follo w ing figures sho w the timer/counter in synchronous mode, and the timer clock (clk t2 ) is therefore sho w n as a clock enable signal. in asynchronous mode, clk i/o should be replaced by the timer/counter oscillator clock. the figures include information on w hen interrupt flags are set. figure 16-8 contains timing data for basic time r/counter operation. the figure sho w s the count sequence close to the max v alue in all modes other than phase correct pwm mode. figure 16-8. timer/counter timing diagram, no prescaling. f ocnxpcpwm f clk_i/o n 510 ? ------------------ = clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 155 7593l?avr?09/12 at90usb64/128 figure 16-9 sho w s the same timing data, but w ith the prescaler enabled. figure 16-9. timer/counter timing diagram, w ith prescaler (f clk_i/o /8). figure 16-10 sho w s the setting of ocf2a in all modes except ctc mode. figure 16-10. timer/counter timing diagram, setting of ocf2a, w ith prescaler (f clk_i/o /8). figure 16-11 on page 156 sho w s the setting of ocf2a and the clearing of tcnt2 in ctc mode. tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o / 8 ) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o / 8 ) 156 7593l?avr?09/12 at90usb64/128 figure 16-11. timer/counter timing diagram, clear timer on compare match mode, w ith pres- caler (f clk_i/o /8). 16.8 8-bit timer/counter register description 16.8.1 tccr2a ? timer/counter control register a ? bits 7:6 ? com2a1:0: compare match output a mode these bits control the output compare pin (oc2a) beha v ior. if one or both of the com2a1:0 bits are set, the oc2a output o v errides the normal port functionality of the i/o pin it is connected to. ho w e v er, note that the data direction register (ddr) bit corresponding to the oc2a pin must be set in order to enable the output dri v er. when oc2a is connected to the pin, the function of the com2a1:0 bits depends on the wgm22:0 bit setting. table 16-1 sho w s the com2a1:0 bit functionality w hen the wgm22:0 bits are set to a normal or ctc mode (non-pwm). ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o / 8 ) bit 76543210 com2a 1 com2a 0 com2b 1 com2b 0 ?? wgm21 wgm20 tccr2a read/ w rite r/w r/w r/w r/w r r r/w r/w initial v alue 0 0 0 0 0 0 0 0 table 16-1. compare output mode, non-pwm mode. com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected 0 1 toggle oc2a on compare match 1 0 clear oc2a on compare match 1 1 set oc2a on compare match 157 7593l?avr?09/12 at90usb64/128 table 16-2 sho w s the com2a1:0 bit functionality w hen the wgm21:0 bits are set to fast pwm mode. note: 1. a special case occurs w hen ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 151 for more details. table 16-3 sho w s the com2a1:0 bit functionality w hen the wgm22:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs w hen ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 153 for more details. ? bits 5:4 ? com2b1:0: compare match output b mode these bits control the output compare pin (oc2b) beha v ior. if one or both of the com2b1:0 bits are set, the oc2b output o v errides the normal port functionality of the i/o pin it is connected to. ho w e v er, note that the data direction register (ddr) bit corresponding to the oc2b pin must be set in order to enable the output dri v er. when oc2b is connected to the pin, the function of the com2b1:0 bits depends on the wgm22:0 bit setting. table 16-4 sho w s the com2b1:0 bit functionality w hen the wgm22:0 bits are set to a normal or ctc mode (non-pwm). table 16-2. compare output mode, fast pwm mode (1) . com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected 01 wgm22 = 0: normal port op eration, oc0a disconnected. wgm22 = 1: toggle oc2a on compare match. 1 0 clear oc2a on compare match, set oc2a at top 1 1 set oc2a on compare match, clear oc2a at top table 16-3. compare output mode, phase correct pwm mode (1) . com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected 01 wgm22 = 0: normal port operation, oc2a disconnected. wgm22 = 1: toggle oc2a on compare match. 10 clear oc2a on compare match w hen up-counting. set oc2a on compare match w hen do w n-counting. 11 set oc2a on compare match w hen up-counting. clear oc2a on compare match w hen do w n-counting. table 16-4. compare output mode, non-pwm mode. com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected 0 1 toggle oc2b on compare match 1 0 clear oc2b on compare match 1 1 set oc2b on compare match 158 7593l?avr?09/12 at90usb64/128 table 16-5 sho w s the com2b1:0 bit functionality w hen the wgm22:0 bits are set to fast pwm mode. note: 1. a special case occurs w hen ocr2b equals top and com2b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 151 for more details. table 16-6 sho w s the com2b1:0 bit functionality w hen the wgm22:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs w hen ocr2b equals top and com2b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 153 for more details. ? bits 3, 2 ? res: reserved bits these bits are reser v ed bits in the atmel at90usb64/128 and w ill al w ays read as zero. ? bits 1:0 ? wgm21:0: waveform generation mode combined w ith the wgm22 bit found in the tccr2b register, these bits control the counting sequence of the counter, the source for maximum (top) counter v alue, and w hat type of w a v e- form generation to be used, see table 16-7 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and t w o types of pulse width modulation (pwm) modes (see ?modes of operation? on page 150 ). table 16-5. compare output mode, fast pwm mode (1) . com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 01reser v ed 1 0 clear oc2b on compare match, set oc2b at top 1 1 set oc2b on compare match, clear oc2b at top table 16-6. compare output mode, phase correct pwm mode (1) . com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected 01reser v ed 10 clear oc2b on compare match w hen up-counting. set oc2b on compare match w hen do w n-counting 11 set oc2b on compare match w hen up-counting. clear oc2b on compare match w hen do w n-counting table 16-7. wa v eform generation mode bit description. mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 1 0 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff top max 4100reser v ed ? ? ? 159 7593l?avr?09/12 at90usb64/128 notes: 1. max= 0xff 2. bottom= 0x00 16.8.2 tccr2b ? timer/counter control register b ? bit 7 ? foc2a: force output compare a the foc2a bit is only acti v e w hen the wgm bits specify a non-pwm mode. ho w e v er, for ensuring compatibility w ith future de v ices, this bit must be set to zero w hen tccr2b is w ritten w hen operating in pwm mode. when w riting a logical one to the foc2a bit, an immediate compare match is forced on the wa v eform generation unit. the oc2a output is changed according to its com2a1:0 bits setting. note that the foc2a bit is implemented as a strobe. therefore it is the v alue present in the com2a1:0 bits that determines the effect of the forced compare. a foc2a strobe w ill not generate any interrupt, nor w ill it clear the timer in ctc mode using ocr2a as top. the foc2a bit is al w ays read as zero. ? bit 6 ? foc2b: force output compare b the foc2b bit is only acti v e w hen the wgm bits specify a non-pwm mode. ho w e v er, for ensuring compatibility w ith future de v ices, this bit must be set to zero w hen tccr2b is w ritten w hen operating in pwm mode. when w riting a logical one to the foc2b bit, an immediate compare match is forced on the wa v eform generation unit. the oc2b output is changed according to its com2b1:0 bits setting. note that the foc2b bit is implemented as a strobe. therefore it is the v alue present in the com2b1:0 bits that determines the effect of the forced compare. a foc2b strobe w ill not generate any interrupt, nor w ill it clear the timer in ctc mode using ocr2b as top. the foc2b bit is al w ays read as zero. ? bits 5:4 ? res: reserved bits these bits are reser v ed bits in the at90usb64/128 and w ill al w ays read as zero. ? bit 3 ? wgm22: waveform generation mode see the description in the ?tccr2a ? timer/counter control register a? on page 156 . 5 1 0 1 pwm, phase correct ocra top bottom 6110reser v ed ? ? ? 7111fast pwm ocratop top table 16-7. wa v eform generation mode bit description. (continued) mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) bit 76543210 foc2a foc2b ? ? wgm22 cs22 cs21 cs20 tccr2b read/ w rite w w r r r/w r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 160 7593l?avr?09/12 at90usb64/128 ? bit 2:0 ? cs22:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see table 16-8 . 16.8.3 tcnt2 ? timer/counter register the timer/counter register gi v es direct access, both for read and w rite operations, to the timer/counter unit 8-bit counter. writing to the tcnt2 register blocks (remo v es) the compare match on the follo w ing timer clock. modifying the counter (tcnt2) w hile the counter is running, introduces a risk of missing a compare match bet w een tcnt2 and the ocr2x registers. 16.8.4 ocr2a ? output compare register a the output compare register a contains an 8-bit v alue that is continuously compared w ith the counter v alue (tcnt2). a match can be used to generate an output compare interrupt, or to generate a w a v eform output on the oc2a pin. 16.8.5 ocr2b ? output compare register b the output compare register b contains an 8-bit v alue that is continuously compared w ith the counter v alue (tcnt2). a match can be used to generate an output compare interrupt, or to generate a w a v eform output on the oc2b pin. table 16-8. clock select bit description. cs22 cs21 cs20 description 0 0 0 no clock source (timer/counter stopped) 001clk t2s /(no prescaling) 010clk t2s /8 (from prescaler) 011clk t2s /32 (from prescaler) 100clk t2s /64 (from prescaler) 101clk t2s /128 (from prescaler) 110clk t 2 s /256 (from prescaler) 111clk t 2 s /1024 (from prescaler) bit 76543210 tcnt2 [7:0] tcnt2 read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ocr2a [7:0] ocr2a read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 ocr2b [7:0] ocr2b read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 161 7593l?avr?09/12 at90usb64/128 16.9 asynchronous operation of the timer/counter 16.9.1 assr ? asynchronous status register ? bit 6 ? exclk: enable external clock input when exclk is w ritten to one, and asynchronous clock is selected, the external clock input buf- fer is enabled and an external cl ock can be input on timer oscilla tor 1 (tosc1) pin instead of a 32 khz crystal. writing to exclk should be done before asynchronous operation is selected. note that the crystal oscillator w ill only run w hen this bit is zero. ? bit 5 ? as2: asynchronous timer/counter2 when as2 is w ritten to zero, timer/counter2 is clocked from the i/o clock, clk i/o . when as2 is w ritten to one, timer/counter2 is clocked from a crystal oscillato r connected to the timer oscil- lator 1 (tosc1) pin. when the v alue of as2 is changed, the contents of tcnt2, ocr2a, ocr2b, tccr2a and tccr2b might be corrupted. ? bit 4 ? tcn2ub: timer/counter2 update busy when timer/counter2 operates asynchronously and tcnt2 is w ritten, this bit becomes set. when tcnt2 has been updated from the temporary storage register, this bit is cleared by hard- w are. a logical zero in this bit indicates that tcnt2 is ready to be updated w ith a ne w v alue. ? bit 3 ? ocr2aub: output co mpare register2 update busy when timer/counter2 operates asynchronously and ocr2a is w ritten, this bit becomes set. when ocr2a has been updated from the temporary storage register, this bit is cleared by hard- w are. a logical zero in this bit indicates that ocr2a is ready to be updated w ith a ne w v alue. ? bit 2 ? ocr2bub: output compare register2 update busy when timer/counter2 operates asynchronously and ocr2b is w ritten, this bit becomes set. when ocr2b has been updated from the temporary storage register, this bit is cleared by hard- w are. a logical zero in this bit indicates that ocr2b is ready to be updated w ith a ne w v alue. ? bit 1 ? tcr2aub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2a is w ritten, this bit becomes set. when tccr2a has been updated from the tempor ary storage register, this bit is cleared by hard w are. a logical zero in this bit indica tes that tccr2a is ready to be updated w ith a ne w v alue. ? bit 0 ? tcr2bub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2b is w ritten, this bit becomes set. when tccr2b has been updated from the tempor ary storage register, this bit is cleared by hard w are. a logical zero in this bit indica tes that tccr2b is ready to be updated w ith a ne w v alue. if a w rite is performed to any of the fi v e timer/counter2 registers w hile its update busy flag is set, the updated v alue might get corrupted and cause an unintentional interrupt to occur. bit76543210 ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub assr read/ w riterr/wr/wrrrrr initial v alue 0 0 0 0 0 0 0 0 162 7593l?avr?09/12 at90usb64/128 the mechanisms for reading tcnt2, ocr2a, ocr2b, tccr2a and tccr2b are different. when reading tcnt2, the actual timer v alue is read. when readin g ocr2a, ocr2b, tccr2a and tccr2b the v alue in the temporary storage register is read. 16.9.2 asynchronous operation of timer/counter2 when timer/counter2 operates asynchronously, some considerations must be taken. ? warning: when s w itching bet w een asynchronous and synchronous clocking of timer/counter2, the timer registers tcnt2, ocr2x, and tccr2x might be corrupted. a safe procedure for s w itching clock source is: a. disable the timer/counter2 interrupts by clearing ocie2x and toie2. b. select clock source by setting as2 as appropriate. c. write ne w v alues to tcnt2, ocr2x, and tccr2x. d. to s w itch to asynchronous operation: wait for tcn2ub, ocr2xub, and tcr2xub. e. clear the timer/counter2 interrupt flags. f. enable interrupts, if needed. ? the cpu main clock frequency must be more than four times th e oscillator frequency ? when w riting to one of the registers tcnt2, ocr2x, or tccr2x, the v alue is transferred to a temporary register, and latched after t w o positi v e edges on tosc1. the user should not w rite a ne w v alue before the contents of the temporary register ha v e been transferred to its destination. each of the fi v e mentioned registers ha v e their indi v idual temporary register, w hich means that, for example, w riting to tcnt2 does not disturb an ocr2x w rite in progress. to detect that a transfer to the destination register has taken place, the asynchronous status register ? assr has been implemented ? when entering po w er-sa v e or adc noise reduction mode after ha v ing w ritten to tcnt2, ocr2x, or tccr2x, the user must w ait until the w ritten register has been updated if timer/counter2 is used to w ake up the de v ice. other w ise, the mcu w ill enter sleep mode before the changes are effecti v e. this is particularly important if any of the output compare2 interrupt is used to w ake up the de v ice, since the output compare function is disabled during w riting to ocr2x or tcnt2. if the w rite cycle is not finished, and the mcu enters sleep mode before the corresponding ocr2xub bit returns to zero, the de v ice w ill ne v er recei v e a compare match interrupt, and the mcu w ill not w ake up ? if timer/counter2 is used to w ake the de v ice up from po w er-sa v e or adc noise reduction mode, precautions must be taken if the user w ants to re-enter one of these modes: the interrupt logic needs one tosc1 cycle to be reset. if the time bet w een w ake-up and re- entering sleep mode is less than one tosc1 cycle, the interrupt w ill not occur, and the de v ice w ill fail to w ake up. if the user is in doubt w hether the time before re-entering po w er- sa v e or adc noise reduction mo de is sufficient, the follo w ing algorithm can be used to ensure that one tosc1 cycle has elapsed: a. write a v alue to tccr2x, tcnt2, or ocr2x. b. wait until the corresponding update busy flag in assr returns to zero. c. enter po w er-sa v e or adc noise reduction mode. ? when the asynchronous operatio n is selected, the 32.768khz oscillator for timer/counter2 is al w ays running, except in po w er-do w n and standby modes. after a po w er-up reset or w ake-up from po w er-do w n or standby mode, the user should be a w are of the fact that this oscillator might take as long as one second to stabilize. the user is ad v ised to w ait for at least one second before using timer/counter2 after po w er-up or w ake-up from po w er-do w n or standby mode. the contents of all timer/coun ter2 registers must be considered lost after 163 7593l?avr?09/12 at90usb64/128 a w ake-up from po w er-do w n or standby mode due to unstable clock signal upon start-up, no matter w hether the oscillator is in use or a cl ock signal is applied to the tosc1 pin ? description of w ake up from po w er-sa v e or adc noise reduction mode w hen the timer is clocked asynchronously: when the interrupt condition is met, the w ake up process is started on the follo w ing cycle of the timer clock, that is, the timer is al w ays ad v anced by at least one before the processor can read the counter v alue. after w ake-up, the mcu is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction follo w ing sleep ? reading of the tcnt2 register shortly after w ake-up from po w er-sa v e may gi v e an incorrect result. since tcnt2 is clocked on the asynchronous tosc clock, reading tcnt2 must be done through a register synchronized to the internal i/o clock domain. synchronization takes place for e v ery rising tosc1 edge. when w aking up from po w er-sa v e mode, and the i/o clock (clk i/o ) again becomes acti v e, tcnt2 w ill read as the pre v ious v alue (before entering sleep) until the next rising tosc1 edge. the phase of the tosc clock after w aking up from po w er-sa v e mode is essentially unpredictable, as it depends on the w ake-up time. the recommended procedure for reading tcnt2 is thus as follo w s: a. write any v alue to either of the registers ocr2x or tccr2x. b. wait for the corresponding update busy flag to be cleared. c. read tcnt2. ? during asynchronous operation, the synchronization of the interrupt flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. the timer is therefore ad v anced by at least one before the processor can read the timer v alue causing the setting of the interrupt flag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock 16.9.3 timsk2 ? timer/counter2 interrupt mask register ? bit 2 ? ocie2b: timer/counter2 output compare match b interrupt enable when the ocie2b bit is w ritten to one and the i-bit in the status register is set (one), the timer/counter2 compare match b interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter2 occurs, that is, w hen the ocf2b bit is set in the timer/counter2 interrupt flag register ? tifr2. ? bit 1 ? ocie2a: timer/counter2 output compare match a interrupt enable when the ocie2a bit is w ritten to one and the i-bit in the status register is set (one), the timer/counter2 compare match a interrupt is enabled. the corresponding interrupt is executed if a compare match in timer/counter2 occurs, that is, w hen the ocf2a bit is set in the timer/counter2 interrupt flag register ? tifr2. ? bit 0 ? toie2: timer/counter2 overflow interrupt enable when the toie2 bit is w ritten to one and the i-bit in the status register is set (one), the timer/counter2 o v erflo w interrupt is enabled. the corresponding interrupt is executed if an o v erflo w in timer/counter2 occurs, that is, w hen the tov2 bit is set in the timer/counter2 inter- rupt flag register ? tifr2. bit 765432 1 0 ?????ocie2bocie2atoie2timsk2 read/ w riterrrrrr/w r/wr/w initial v alue000000 0 0 164 7593l?avr?09/12 at90usb64/128 16.9.4 tifr2 ? timer/counter2 interrupt flag register ? bit 2 ? ocf2b: output compare flag 2 b the ocf2b bit is set (one) w hen a compare match occurs bet w een the timer/counter2 and the data in ocr2b ? output compare register2. ocf2b is cleared by hard w are w hen executing the corresponding interrupt handling v ector. alternati v ely, ocf2b is cleared by w riting a logic one to the flag. when the i-bit in sreg, ocie2b (timer/counter2 compare match interrupt enable), and ocf2b are set (one), the timer/counter2 compare match interrupt is executed. ? bit 1 ? ocf2a: output compare flag 2 a the ocf2a bit is set (one) w hen a compare match occurs bet w een the timer/counter2 and the data in ocr2a ? output compare register2. ocf2a is cleared by hard w are w hen executing the corresponding interrupt handling v ector. alternati v ely, ocf2a is cleared by w riting a logic one to the flag. when the i-bit in sreg, ocie2a (timer/counter2 compare match interrupt enable), and ocf2a are set (one), the timer/counter2 compare match interrupt is executed. ? bit 0 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) w hen an o v erflo w occurs in timer/counter2. tov2 is cleared by hard- w are w hen executing the corresponding interrupt handling v ector. alternati v ely, tov2 is cleared by w riting a logic one to the flag. when the sreg i-bit, toie2a (timer/counter2 o v erflo w inter- rupt enable), and tov2 are set (one), the timer/counter2 o v erflo w interrupt is executed. in pwm mode, this bit is set w hen timer/counter2 changes counting direction at 0x00. 16.10 timer/counter prescaler figure 16-12. prescaler for timer/counter2. bit 76543210 ?????ocf2bocf2atov2tifr2 read/ w riterrrrrr/wr/wr/w initial v alue00000000 10-bit t/c pre s caler timer/counter2 clock s ource clk i/o clk t2 s to s c1 a s 2 c s 20 c s 21 c s 22 clk t2 s / 8 clk t2 s /64 clk t2 s /12 8 clk t2 s /1024 clk t2 s /256 clk t2 s /32 0 p s ra s y clear clk t2 165 7593l?avr?09/12 at90usb64/128 the clock source for timer/counter2 is named clk t2s . clk t2s is by default connected to the main system i/o clock clk i o . by setting the as2 bit in assr, timer/counter2 is asynchronously clocked from the tosc1 pin. this enables us e of timer/counter2 as a real time counter (rtc). when as2 is set, pins tosc1 and tosc 2 are disconnected from port c. a crystal can then be connected bet w een the tosc1 and tosc2 pins to ser v e as an independent clock source for timer/counter2. the os cillator is op timized for use w ith a 32.768khz crystal. apply- ing an external clock source to tosc1 is not recommended. for timer/counter2, the possible prescaled selections are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as w ell as 0 (stop) may be selected. setting the psrasy bit in gtccr resets the prescaler. this allo w s the user to operate w ith a predictable prescaler. 16.10.1 gtccr ? general time r/counter control register ? bit 1 ? psrasy: prescaler reset timer/counter2 when this bit is one, the timer/counter2 prescaler w ill be reset. this bit is normally cleared immediately by hard w are. if the bit is w ritten w hen timer/counter2 is operating in asynchronous mode, the bit w ill remain one until the prescaler has been reset. the bit w ill not be cleared by hard w are if the tsm bit is set. refer to the description of the section ?gtccr ? general timer/counter control register? on page 97 for a description of the timer/counter synchroniza- tion mode. bit 7 6 5 4 3 2 1 0 tsm ? ? ? ? ?psra- sy psrsy nc gtccr read/ w rite r/w r r r r r r/w r/w initial v alue 0 0 0 0 0 0 0 0 166 7593l?avr?09/12 at90usb64/128 17. output compare modulator (ocm1c0a) 17.1 overview the output compare modulator (ocm) allo w s generation of w a v eforms modulated w ith a carrier frequency. the modulator uses the outputs from the output compare unit c of the 16-bit timer/counter1 and the output compare unit of the 8-bit timer/counter0. for more details about these timer/counters see ?timer/counter0, timer/counter1, and timer/counter3 pres- calers? on page 96 and ?8-bit timer/counter2 w ith pwm and asynchronous operation? on page 145 . figure 17-1. output compare modulator, block diagram. when the modulator is enabled, the t w o output compare channels are modulated together as sho w n in the block diagram ( figure 17-1 ). 17.2 description the output compare unit 1c and output compare unit 2 shares the pb7 port pin for output. the outputs of the output compare units (oc1c and oc0a) o v errides the normal portb7 register w hen one of them is enabled (that is, w hen comnx1:0 is not equal to zero). when both oc1c and oc0a are enabled at the same time, the modulator is automatically enabled. the functional equi v alent schematic of the modulator is sho w n on figure 17-2 . the schematic includes part of the timer/counter units and the port b pin 7 output dri v er circuit. figure 17-2. output compare modulator, schematic. oc1c pin oc1c / oc0a / pb7 timer/counter 1 timer/counter 0 oc0a portb7 ddrb7 dq dq pin coma01 coma00 databus oc1c / oc0a/ pb7 com1c1 com1c0 modulator 1 0 oc1c dq oc0a dq (from waveform generator) (from waveform generator) 0 1 vcc 167 7593l?avr?09/12 at90usb64/128 when the modulator is enabled the type of modulation (logical and or or) can be selected by the portb7 register. note that the ddrb7 controls the direction of the port independent of the comnx1:0 bit setting. 17.2.1 timing example figure 17-3 illustrates the modulator in ac tion. in this example the ti mer/counter1 is set to oper- ate in fast pwm mode (non-in v erted) and timer/counter0 uses ctc w a v eform mode w ith toggle compare output mode (comnx1:0 = 1). figure 17-3. output compare modulator, timing diagram. in this example, timer/counter2 pro v ides the carrier, w hile the modulating signal is generated by the output compare unit c of the timer/counter1. the resolution of the pwm signal (oc1c) is reduced by the modulation. the reduction factor is equal to the number of system clock cycles of one period of the carrier (oc0a). in this example the resolution is reduced by a factor of t w o. the reason for the reduction is illustrated in figure 17-3 at the second and third period of the pb7 output w hen portb7 equals zero. the period 2 high time is one cycle longer than the period 3 high time, but the result on the pb7 output is equal in both periods. 1 2 oc0a (ctc mode) oc1c (fpwm mode) pb7 (portb7 = 0) pb7 (portb7 = 1) (period) 3 clk i/o 168 7593l?avr?09/12 at90usb64/128 18. spi ? serial peripheral interface the serial peripheral interface (spi) allo w s high-speed synchronous data transfer bet w een the atmel at90usb64/128 and peripheral de v ices or bet w een se v eral avr de v ices. the at90usb64/128 spi includes the follo w ing features: ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmissi on interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode usart can also be used in master spi mode, see ?usart in spi mode? on page 202 . the po w er reduction spi bit, prspi, in ?prr0 ? po w er reduction register 0? on page 54 must be w ritten to zero to enable spi module. figure 18-1. spi block diagram (1) . note: 1. refer to figure 1-1 on page 3 , and table 11-6 on page 79 for spi pin placement. the interconnection bet w een master and sla v e cpus w ith spi is sho w n in figure 18-2 on page 169 . the system consists of t w o shift registers, and a master clock generator. the spi master initiates the communication cycle w hen pulling lo w the sla v e select ss pin of the desired sla v e. spi2x spi2x divider /2/4/ 8 /16/32/64/12 8 169 7593l?avr?09/12 at90usb64/128 master and sla v e prepare the data to be sent in their respecti v e shift registers, and the master generates the required clock pulses on the sck line to interchange data. data is al w ays shifted from master to sla v e on the master out ? sla v e in, mosi, line, and from sla v e to master on the master in ? sla v e out, miso, line. after each data packet, the master w ill synchronize the sla v e by pulling high the sla v e select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user soft w are before communication can start. when this is done, w riting a byte to the spi data register starts the spi clock generator, and the hard w are shifts the eight bits into the sla v e. after shifting one byte, the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by w riting it into spdr, or signal the end of packet by pulling high the sla v e select, ss line. the last incoming byte w ill be kept in the buffer register for later use. when configured as a sla v e, the spi interface w ill remain sleeping w ith miso tri-stated as long as the ss pin is dri v en high. in this state, soft w are may update the contents of the spi data register, spdr, but the data w ill not be shifted out by incoming clock pulses on the sck pin until the ss pin is dri v en lo w . as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the sla v e may continue to place ne w data to be sent into spdr before reading the incoming data. the last incoming byte w ill be kept in the buffer register for later use. figure 18-2. spi master-sla v e interconnection. the system is single buffered in the transmi t direction and double buffered in the recei v e direc- tion. this means that bytes to be transmitted cannot be w ritten to the spi data register before the entire shift cycle is completed. when recei v ing data, ho w e v er, a recei v ed character must be read from the spi data register before the next character has been completely shifted in. oth- er w ise, the first byte is lost. in spi sla v e mode, the control logic w ill sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal, the frequency of the spi clock should ne v er exceed f osc /4. when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is o v erridden according to table 18-1 on page 170 . for more details on automatic port o v errides, refer to ?alternate port functions? on page 76 . s hift enable 170 7593l?avr?09/12 at90usb64/128 note: 1. see ?alternate functions of port b? on page 79 for a detailed description of ho w to define the direction of the user defined spi pins. the follo w ing code examples sho w ho w to initialize the spi as a master and ho w to perform a simple transmission. ddr_spi in the examples mu st be replaced by the actual data direction register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data direction bits for these pins. for example, if mosi is placed on pin pb5, replace dd_mosi w ith ddb5 and ddr_spi w ith ddrb. table 18-1. spi pin o v errides (1) . pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input 171 7593l?avr?09/12 at90usb64/128 note: 1. see ?about code examples? on page 10. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 174 7593l?avr?09/12 at90usb64/128 ? bit 3 ? cpol: clock polarity when this bit is w ritten to one, sck is high w hen idle. when cpol is w ritten to zero, sck is lo w w hen idle. refer to figure 18-3 and figure 18-4 for an example. the cpol functionality is sum- marized in table 18-2 : ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 18-3 and figure 18-4 for an example. the cpol functionality is summarized table 18-3 : ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these t w o bits control the sck rate of the de v ice configured as a master. spr1 and spr0 ha v e no effect on the sla v e. the relationship bet w een sck and the oscillator clock frequency f osc is sho w n in table 18-4 : 18.1.4 spsr ? spi status register ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is dri v en lo w w hen the spi is in master mode, this w ill also set the spif flag. spif is cleared by hard w are w hen executing the table 18-2. cpol functionality. cpol leading edge trailing edge 0 rising falling 1 falling rising table 18-3. cpha functionality. cpha leading edge trailing edge 0 sample setup 1 setup sample table 18-4. relationship bet w een sck and the o scillator frequency. spi2x spr1 spr0 sck frequency 000 f osc / 4 001 f osc / 16 010 f osc / 64 011 f osc / 128 100 f osc / 2 101 f osc / 8 110 f osc / 32 111 f osc / 64 bit 76543210 spif wcol ? ? ? ? ? spi2x spsr read/ w riterrrrrrrr/w initial v alue00000000 175 7593l?avr?09/12 at90usb64/128 corresponding interrupt handling v ector. alternati v ely, the spif bit is cleared by first reading the spi status register w ith spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the sp i data register (spdr) is w ritten during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi status register w ith wcol set, and then accessing the spi data register. ? bit 5..1 ? res: reserved bits these bits are reser v ed bits in the atmel at90usb64/128 and w ill al w ays read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is w ritten logic one the spi speed (sck frequency) w ill be doubled w hen the spi is in master mode (see table 18-4 on page 174 ). this means that the minimum sck period w ill be t w o cpu clock periods. when the spi is configured as sla v e, the spi is only guaranteed to w ork at f osc /4 or lo w er. the spi interface on the at 90usb64/128 is also used for progra m memory and eeprom do w nloading or uploading. see page 373 for serial programming and v erification. 18.1.5 spdr ? spi data register the spi data register is a read/ w rite register used for data transfer bet w een the register file and the spi shift register. writing to the register initiates data transmission. reading the regis- ter causes the shift register recei v e buffer to be read. 18.2 data modes there are four combinations of sck phase and polarity w ith respect to serial data, w hich are determined by control bits cpha and cpol. the spi data transfer formats are sho w n in figure 18-3 on page 176 and figure 18-4 on page 176 . data bits are shifted out and latched in on opposite edges of the sck signal, ensuring sufficient time for data signals to stabilize. this is clearly seen by summarizing table 18-2 on page 174 and table 18-3 on page 174 , as done belo w : bit 76543210 msb lsb spdr read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue x x x x x x x x undefined table 18-5. cpol functionality. leading edge traili ng edge spi mode cpol=0, cpha=0 sample (rising) setup (falling) 0 cpol=0, cpha=1 setup (rising) sample (falling) 1 cpol=1, cpha=0 sample (falling) setup (rising) 2 cpol=1, cpha=1 setup (falling) sample (rising) 3 176 7593l?avr?09/12 at90usb64/128 figure 18-3. spi transfer format w ith cpha = 0. figure 18-4. spi transfer format w ith cpha = 1. bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb fir s t (dord = 0) lsb fir s t (dord = 1) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb fir s t (dord = 0) lsb fir s t (dord = 1) 177 7593l?avr?09/12 at90usb64/128 19. usart the uni v ersal synchronous and asynchronous serial recei v er and transmitter (usart) is a highly flexible serial communication de v ice. the main features are: ? full duplex operation (independent se rial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high resolution baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bit detection and digital low pass filter ? three separate interrupts on tx complete, tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode 19.1 overview a simplified block diagram of the usart transmitter is sho w n in figure 19-1 . cpu accessible i/o registers and i/o pins are sho w n in bold. figure 19-1. usart block diagram (1) . note: 1. see figure 1-1 on page 3 , table 11-12 on page 83 and for usart pin placement. parity generator ubrr[h:l] udr (transmit) ucsra ucsrb ucsrc baud rate generator transmit shift register receive shift register rxd txd pin control udr (receive) pin control xck data recovery clock recovery pin control tx control rx control parity checker data bus osc sync logic clock generator transmitter receiver 178 7593l?avr?09/12 at90usb64/128 the dashed boxes in the block diagram separate the three main parts of the usart (listed from the top): clock generator, transmitter and recei v er. control registers are shared by all units. the clock generation logic consis ts of synchronization logic fo r external clock input used by synchronous sla v e operation, and the baud rate generator. the xckn (transfer clock) pin is only used by synchronous transfer mode. t he transmitter consists of a single w rite buffer, a serial shift register, parity generator and cont rol logic for handling different serial frame for- mats. the w rite buffer allo w s a continuous transfer of data w ithout any delay bet w een frames. the recei v er is the most complex part of the usart module due to its clock and data reco v ery units. the reco v ery units are used for asynchronous data reception. in addition to the reco v ery units, the recei v er includes a parity checker, control logic, a shift register and a t w o le v el recei v e buffer (udrn). the recei v er supports the same frame formats as the transmitter, and can detect frame error, data o v errun and parity errors. 19.2 clock generation the clock generation logic generates the base clock for the transmitter and recei v er. the usartn supports four modes of clock opera tion: normal asynchronous, double speed asyn- chronous, master synchronous and sla v e synchronous mode. the umseln bit in usart control and status register c (ucsrnc) selects bet w een asynchronous and synchronous operation. double speed (asynchronous mode only) is controlled by the u2xn found in the ucsrna register. when using synchronous mode (umseln = 1), the data direction register for the xckn pin (ddr_xckn) controls w hether the clock source is internal (master mode) or external (sla v e mode). the xckn pin is only acti v e w hen using synchronous mode. figure 19-2 sho w s a block diagram of the clock generation logic. figure 19-2. clock generation logic, block diagram. signal description: txclk transmitter clock (internal signal). rxclk recei v er base clock (internal signal). xcki input from xck pin (internal signal). used for synchronous sla v e operation. xcko clock output to xck pin (internal signal). used for synchronous master operation. f osc xtal pin frequency (system clock). prescaling down-counter /2 ubrr /4 /2 fosc ubrr+1 sync register osc xck pin txclk u2x umsel ddr_xck 0 1 0 1 xcki xcko ddr_xck rxclk 0 1 1 0 edge detector ucpol 179 7593l?avr?09/12 at90usb64/128 19.2.1 internal clock generation ? the baud rate generator internal clock generation is used for the as ynchronous and the synchronous master modes of operation. the description in this section refers to figure 19-2 on page 178 . the usart baud rate register (ubrrn) and the do w n-counter connected to it function as a programmable prescaler or baud rate generator. the do w n-counter, running at system clock (f osc ), is loaded w ith the ubrrn v alue each time the counter has counted do w n to zero or w hen the ubrrln register is w ritten. a clock is generated each ti me the counter reaches zero. this clock is the baud rate generator clock output (= f osc /(ubrrn+1)). the transmitter di v ides the baud rate generator clock output by 2, 8, or 16 depending on mode. the baud rate generator output is used directly by the recei v er?s clock and data reco v ery units. ho w e v er, the reco v ery units use a state machine that uses 2, 8, or 16 states depending on mode set by the state of the umseln, u2xn and ddr_xckn bits. table 19-1 contains equations for calculating the baud rate (in bits per second) and for calculat- ing the ubrrn v alue for each mode of operation using an internally generated clock source. note: 1. the baud rate is defined to be the transfer rate in bit per second (bps). baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrhn and ubrrln registers, (0-4095) some examples of ubrrn v alues for some system clock frequencies are found in table 19-9 on page 198 . 19.2.2 double speed operation (u2xn) the transfer rate can be doubled by setting the u2xn bit in ucsrna. setting this bit only has effect for the asynchronous operation. set this bit to zero w hen using synchronous operation. setting this bit w ill reduce the di v isor of the baud rate di v ider from 16 to 8, effecti v ely doubling the transfer rate for asynchronous communication. note ho w e v er that the recei v er w ill in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock reco v ery, and therefore a more accurate baud rate setting and system clock are required w hen this mode is used. for the transmitter, there are no do w nsides. table 19-1. equations for calculating baud rate register setting. operating mode equation for calculating baud rate (1) equation for calculating ubrr value asynchronous normal mode (u2xn = 0) asynchronous double speed mode (u2xn = 1) synchronous master mode baud f osc 16 ubrr n 1 + () ----------------------------------------- - = ubrr n f osc 16 baud ----------------------- - 1 ? = baud f osc 8 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 8 baud -------------------- 1 ? = baud f osc 2 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = 180 7593l?avr?09/12 at90usb64/128 19.2.3 external clock external clocking is used by the synchronous sla v e modes of operation. the description in this section refers to figure 19-2 on page 178 for details. external clock input from the xckn pin is sample d by a synchronization register to minimize the chance of meta-stability. the output from the synchronization register must then pass through an edge detector before it can be used by the transmitter and recei v er. this process intro- duces a t w o cpu clock period delay and therefore the maximum external xckn clock frequency is limited by the follo w ing equation: note that f osc depends on the stability of the system clock source. it is therefore recommended to add some margin to a v oid possible loss of data due to frequency v ariations. 19.2.4 synchronous clock operation when synchronous mode is used (umseln = 1), the xckn pin w ill be used as either clock input (sla v e) or clock output (master). the dependency bet w een the clock edges and data sampling or data change is the same. the basic principle is that data input (on rxdn) is sampled at the opposite xckn clock edge of the edge the data output (txdn) is changed. figure 19-3. synchronous mode xckn timing. the ucpoln bit ucrsc selects w hich xckn clock edge is used for data sampling and w hich is used for data change. as figure 19-3 sho w s, w hen ucpoln is zero the data w ill be changed at rising xckn edge and sampled at falling xckn edge. if ucpoln is set, the data w ill be changed at falling xckn edge and samp led at rising xckn edge. 19.3 frame formats a serial frame is defined to be one character of data bits w ith synchronization bits (start and stop bits), and optionally a parity bi t for error checking. the usart accepts all 30 combinations of the follo w ing as v alid frame formats: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ?no, e v en or odd parity bit ? 1 or 2 stop bits f xck f osc 4 ----------- < rxd / txd xck rxd / txd xck ucpol = 0 ucpol = 1 sample sample 181 7593l?avr?09/12 at90usb64/128 a frame starts w ith the start bit follo w ed by the least significant data bit. then the next data bits, up to a total of nine, are succeeding, ending w ith the most significant bit. if enabled, the parity bit is inserted after the data bits, before the stop bits. when a complete frame is transmitted, it can be directly follo w ed by a ne w frame, or the communication line can be set to an idle (high) state. figure 19-4 illustrates the possible combinations of th e frame formats. bits inside brackets are optional. figure 19-4. frame formats. st start bit, al w ays lo w (n) data bits (0 to 8) p parity bit. can be odd or e v en sp stop bit, al w ays high idle no transfers on the communication line (rxdn or txdn). an idle line must be high the frame format used by th e usart is set by the ucszn2:0, upmn1:0 and usbsn bits in ucsrnb and ucsrnc. the recei v er and transmitter use the same setting. note that changing the setting of any of these bits w ill corrupt all ongoing commun ication for both the recei v er and transmitter. the usart character size (ucszn2:0) bits select the number of data bits in the frame. the usart parity mode (upmn1:0) bits enable and set the type of parity bit. the selection bet w een one or t w o stop bits is done by the usart stop bit sele ct (usbsn) bit. the recei v er ignores the second stop bit. an fe (frame error) w ill therefore only be dete cted in the cases w here the first stop bit is zero. 19.3.1 parity bit calculation the parity bit is calculated by doing an exclusi v e-or of all the data bits. if odd parity is used, the result of the exclusi v e or is in v erted. the relation bet w een the parity bit and data bits is as follo w s: p even parity bit using e v en parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is located bet w een the last data bit and first stop bit of a serial frame. 19.4 usart initialization the usart has to be initialized before any communication can take place. the initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame p even d n 1 ? d 3 d 2 d 1 d 0 0 p odd d n 1 ? d 3 d 2 d 1 d 0 1 = = 182 7593l?avr?09/12 at90usb64/128 transmitter or the recei v er depending on the usage. for interrupt dri v en usart operation, the global interrupt flag should be cleared (and interrupts globally disabled) w hen doing the initialization. before doing a re-initialization w ith changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxc flag can be used to check that there are no unread data in the recei v e buffer. note that the txcn flag must be cleared before each transmission (before udrn is w ritten) if it is used for this purpose. the follo w ing simple usart initialization code examples sho w one assembly and one c func- tion that are equal in functionality. the exampl es assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. the baud rate is gi v en as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. note: 1. see ?about code examples? on page 10. more ad v anced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. ho w e v er, many applications use a fixed setting of the baud and control registers, and for these types of applicati ons the initialization code can be placed directly in the main routin e, or be combined w ith initialization code for other i/o modules. 19.5 data transmission ? the usart transmitter the usart transmitter is enabled by setting the transmit enable (txen) bit in the ucsrnb register. when the transmitter is enabled, the normal port operation of the txdn pin is o v errid- assembly code example (1) usart_init: ; set baud rate out ubrrhn, r17 out ubrrln, r16 ; enable receiver and transmitter ldi r16, (1< 186 7593l?avr?09/12 at90usb64/128 bits of the data read from the udrn w ill be masked to zero. the usar t has to be initialized before the function can be used. note: 1. see ?about code examples? on page 10. the function simply w aits for data to be present in the recei v e buffer by checking the rxcn flag, before reading the buffer and returning the v alue. 19.6.2 receiving frames with 9 data bits if 9-bit characters are used (ucszn=7) the ninth bit must be read from the rxb8n bit in ucs- rnb before reading the lo w bits from the udrn. this rule ap plies to the fen, dorn and upen status flags as w ell. read status from ucsrna, then data from udrn. reading the udrn i/o location w ill change the stat e of the recei v e buffer fifo and consequently the txb8n, fen, dorn and upen bits, w hich all are stored in the fifo, w ill change. the follo w ing code example sho w s a simple usart recei v e function that handles both nine bit characters and the status bits. assembly code example (1) usart_receive: ; wait for data to be received sbis ucsrna, rxcn rjmp usart_receive ; get and return received data from buffer in r16, udrn ret c code example (1) unsigned char usart_receive( void ) { /* wait for data to be received */ while ( !(ucsrna & (1< 188 7593l?avr?09/12 at90usb64/128 the recei v e complete (rxcn) flag indicates if there are unread data present in the recei v e buf- fer. this flag is one w hen unread data exist in the recei v e buffer, and zero w hen the recei v e buffer is empty (that is, does not contain any unread data). if the recei v er is disabled (rxenn = 0), the recei v e buffer w ill be flushed and cons equently the rxcn bit w ill become zero. when the recei v e complete interrupt enable (rxcien) in ucsrnb is set, the usart recei v e complete interrupt w ill be executed as long as the rxcn flag is set (pro v ided that global inter- rupts are enabled). when interrupt-dri v en data reception is used, the recei v e complete routine must read the recei v ed data from udrn in order to clear the rxcn flag, other w ise a ne w inter- rupt w ill occur once the interrup t routine terminates. 19.6.4 receiver error flags the usart recei v er has three error flags: frame error (fen), data o v errun (dorn) and par- ity error (upen). all can be accessed by reading ucsrna. common for the error flags is that they are located in the recei v e buffer together w ith the frame for w hich they indicate the error status. due to the buffering of the error flags, the ucsrna must be read before the recei v e buf- fer (udrn), since reading the udrn i/o location changes the buffer re ad location. another equality for the error flags is that they can not be altered by soft w are doing a w rite to the flag location. ho w e v er, all flags must be set to zero w hen the ucsrna is w ritten for up w ard compat- ibility of future usart implemen tations. none of the error fl ags can generate interrupts. the frame error (fen) flag indicates the state of the first stop bit of the next readable frame stored in the recei v e buffer. the fen flag is zero w hen the stop bit w as correctly read (as one), and the fen flag w ill be one w hen the stop bit w as incorrect (zero). this flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. the fen flag is not affected by the setting of the usbsn bit in ucsrnc since the recei v er ignores all, except for the first, stop bits. for compatibility w ith future de v ices, al w ays set this bit to zero w hen w riting to ucsrna. the data o v errun (dorn) flag indicates data loss due to a recei v er buffer full condition. a data o v errun occurs w hen the recei v e buffer is full (t w o characters), it is a ne w character w ait- ing in the recei v e shift register, and a ne w start bit is detected. if the dorn flag is set there w as one or more serial frame lost bet w een the frame last read from udrn, and the next frame read from udrn. for compatibility w ith future de v ices, al w ays w rite this bit to zero w hen w riting to ucsrna. the dorn flag is cleared w hen the frame recei v ed w as successfully mo v ed from the shift register to the recei v e buffer. the parity error (upen) flag indicates that the next frame in the recei v e buffer had a parity error w hen recei v ed. if parity check is not enabled the upen bit w ill al w ays be read zero. for compatibility w ith future de v ices, al w ays set this bit to zero w hen w riting to ucsrna. for more details see ?parity bit calculation? on page 181 and ?parity checker? on page 188 . 19.6.5 parity checker the parity checker is acti v e w hen the high usart parity mode (upmn1) bit is set. type of par- ity check to be performed (odd or e v en) is selected by the upmn0 bit. when enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result w ith the parity bit from the serial frame. the result of the check is stored in the recei v e buffer together w ith the recei v ed data and stop bits. the parity error (upen) flag can then be read by soft w are to check if the frame had a parity error. 189 7593l?avr?09/12 at90usb64/128 the upen bit is set if the next character that can be read from the recei v e buffer had a parity error w hen recei v ed and the parity checking w as enabled at that point (upmn1 = 1). this bit is v alid until the recei v e buffer (udrn) is read. 19.6.6 disabling the receiver in contrast to the transmitter, disabling of the recei v er w ill be immediate. data from ongoing receptions w ill therefore be lost. when di sabled (that is, the rxenn is set to zero) the recei v er w ill no longer o v erride the normal function of the rxdn port pin. the recei v er buffer fifo w ill be flushed w hen the recei v er is disabled. remaining data in the buffer w ill be lost 19.6.7 flushing the receive buffer the recei v er buffer fifo w ill be flushed w hen the recei v er is disabled, that is, the buffer w ill be emptied of its contents. unread data w ill be lost. if the buffer has to be flushed during normal operation, due to for in stance an error conditi on, read the udrn i/o location until the rxcn flag is cleared. the follo w ing code example sho w s ho w to flush the recei v e buffer. note: 1. see ?about code examples? on page 10. 19.7 asynchronous data reception the usart includes a clock reco v ery and a data reco v ery unit for handling asynchronous data reception. the clock reco v ery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the rxdn pin. the data reco v ery logic sam- ples and lo w pass filters each incoming bit, thereby impro v ing the noise immunity of the recei v er. the asynchronous reception operational range depends on the accuracy of the inter- nal baud rate clock, the rate of the incoming frames, and the frame size in number of bits. 19.7.1 asynchronous clock recovery the clock reco v ery logic synchronizes internal clock to the incoming serial frames. figure 19-5 on page 190 illustrates the sampling process of the start bit of an incoming frame. the sample rate is 16 times the baud rate for normal mode, and eight times the baud rate for double speed mode. the horizontal arro w s illustrate the synchronization v ariation due to the sampling pro- cess. note the larger time v ariation w hen using the double speed mode (u2xn = 1) of operation. samples denoted zero are samples done w hen the rxdn line is id le (that is, no com- munication acti v ity). assembly code example (1) usart_flush: sbis ucsrna, rxcn ret in r16, udrn rjmp usart_flush c code example (1) void usart_flush( void ) { unsigned char dummy; while ( ucsrna & (1< 191 7593l?avr?09/12 at90usb64/128 figure 19-7. stop bit sampling and next start bit sampling. the same majority v oting is done to the stop bit as done for the other bits in the frame. if the stop bit is registered to ha v e a logic 0 v alue, the frame error (fen) flag w ill be set. a ne w high to lo w transition indicating the start bit of a ne w frame can come right after the last of the bits used for majority v oting. for normal speed mode, the first lo w le v el sample can be at point marked (a) in figure 19-7 . for double speed mode the first lo w le v el must be delayed to (b). (c) marks a stop bit of full length. the ear ly start bit detection influences the operational range of the recei v er. 19.7.3 asynchronous operational range the operational range of the recei v er is dependent on the mismatch bet w een the recei v ed bit rate and the internally generated baud rate. if the transmitter is sending frames at too fast or too slo w bit rates, or the internally generated baud rate of the recei v er does not ha v e a similar (see table 19-2 on page 192 ) base frequency, the recei v er w ill not be able to synchronize the frames to the start bit. the follo w ing equations can be used to calculate the ratio of the incoming data rate and internal recei v er baud rate. d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode s f first sample number used for majority v oting. s f = 8 for normal speed and s f = 4 for double speed mode s m middle sample number used for majority v oting. s m = 9 for normal speed and s m = 5 for double speed mode r slow is the ratio of the slo w est incoming data rate that can be accepted in relation to the recei v er baud rate. r fast is the ratio of the fastest incoming data rate that can be accepted in relation to the recei v er baud rate table 19-2 on page 192 and table 19-3 on page 192 list the maximum recei v er baud rate error that can be tolerated. note that normal speed mode has higher toleration of baud rate v ariations. 1234567 8 9 10 0/1 0/1 0/1 stop 1 123 4 5 60/1 rxd sample (u2x = 0) sample (u2x = 1) (a) (b) (c) r slow d 1 + () s s 1 ? ds ? s f ++ ------------------------------------------ - = r fast d 2 + () s d 1 + () ss m + ----------------------------------- = 192 7593l?avr?09/12 at90usb64/128 the recommendations of the maximum recei v er baud rate error w as made under the assump- tion that the recei v er and transmitter equally di v ides the maximum total error. there are t w o possible sources for the recei v ers baud rate error. the recei v er?s system clock (xtal) w ill al w ays ha v e some minor instability o v er the supply v oltage range and the tempera- ture range. when using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. the second source for the error is more controllable. the baud rate generator can not al w ays do an exact di v ision of the system frequency to get the baud rate w anted. in this case an ubrr v alue that gi v es an acceptable lo w error can be used if possible. 19.8 multi-processor communication mode setting the multi-processor communication m ode (mpcmn) bit in ucsrna enables a filtering function of incoming frames recei v ed by the usart recei v er. frames that do not contain address information w ill be ignored and not put into the recei v e buffer. this effecti v ely reduces the number of incoming frames that has to be handled by the cpu, in a system w ith multiple mcus that communicate v ia the same serial bus. the transmitter is unaffected by the mpcmn setting, but has to be used differently w hen it is a part of a system utilizing the multi-processor communication mode. if the recei v er is set up to recei v e frames that contain fi v e to eight data bits, then the first stop bit indicates if the frame contains data or address information. if the recei v er is set up for frames table 19-2. recommended maximum recei v er baud rate error for normal speed mode (u2xn = 0). d # (data+parity bit) r slow [%] r fast [%] max. total error [%] recommended max. receiver error [%] 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 table 19-3. recommended maximum recei v er baud rate error for double speed mode (u2xn = 1). d # (data+parity bit) r slow [%] r fast [%] max. total error [%] recommended max. receiver error [%] 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 193 7593l?avr?09/12 at90usb64/128 w ith nine data bits, then the ninth bit (rxb8n) is used for identifying address and data frames. when the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. when the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables se v eral sla v e mcus to recei v e data from a master mcu. this is done by first decoding an address frame to find out w hich mcu has been addressed. if a particular sla v e mcu has been addressed, it w ill recei v e the follo w ing data frames as normal, w hile the other sla v e mcus w ill ignore the recei v ed frames until another address frame is recei v ed. 19.8.1 using mpcmn for an mcu to act as a master mcu, it can us e a 9-bit character frame format (ucszn = 7). the ninth bit (txb8n) must be set w hen an address frame (txb8n = 1) or cleared w hen a data frame (txb = 0) is being transmitted. the sla v e mcus must in this case be set to use a 9-bit character frame format. the follo w ing procedure should be used to exchange data in multi-processor communication mode: 1. all sla v e mcus are in multi-processor commun ication mode (mpcmn in ucsrna is set). 2. the master mcu sends an address frame, and all sla v es recei v e and read this frame. in the sla v e mcus, the rxcn flag in ucsrna w ill be set as normal. 3. each sla v e mcu reads the udrn register and determines if it has been selected. if so, it clears the mpcmn bit in ucsrna, other w ise it w aits for the next address byte and keeps the mpcmn setting. 4. the addressed mcu w ill recei v e all data frames until a ne w address frame is recei v ed. the other sla v e mcus, w hich still ha v e the mpcmn bit set, w ill ignore the data frames. 5. when the last data frame is recei v ed by the addressed mcu, the addressed mcu sets the mpcmn bit and w aits for a ne w address frame from master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possible, but impractical since the recei v er must change bet w een using n and n+1 character frame formats. this makes full- duplex operation difficult since the transmitter and recei v er uses the same character size set- ting. if 5- to 8-bit character frames are used, the transmitter must be set to use t w o stop bit (usbsn = 1) since the first stop bit is used for indicating the frame type. do not use read-modify-write in structions (sbi and cbi) to set or clear the mpcmn bit. the mpcmn bit shares the same i/o location as the txcn flag and this might accidentally be cleared w hen using sbi or cbi instructions. 19.9 usart register description 19.9.1 udrn ? usart i/o data register n the usart transmit data buffer register and usart recei v e data buffer registers share the same i/o address re ferred to as usart data register or udrn. the transmit data buffer reg- bit 76543210 rxb[7:0] udrn (read) txb[7:0] udrn (write) read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 194 7593l?avr?09/12 at90usb64/128 ister (txb) w ill be the destination for data w ritten to the udrn register location. reading the udrn register location w ill return the conten ts of the recei v e data buffer register (rxb). for 5-, 6-, or 7-bit characters the upper unused bits w ill be ignored by the transmitter and set to zero by the recei v er. the transmit buffer can only be w ritten w hen the udren flag in the ucsrna register is set. data w ritten to udrn w hen the udren flag is not set, w ill be ignored by th e usart transmit- ter. when data is w ritten to the transmit buffer, and the transmitter is enabled, the transmitter w ill load the data into the transmit shift register w hen the shift register is empty. then the data w ill be serially transmitted on the txdn pin. the recei v e buffer consists of a t w o le v el fifo. the fifo w ill change its state w hene v er the recei v e buffer is accessed. due to this beha v ior of the recei v e buffer, do not use read-modify- write instructions (sbi and cbi) on this location. be careful w hen using bit test instructions (sbic and sbis), since these also w ill change the state of the fifo. 19.9.2 ucsrna ? usart contro l and status register a ? bit 7 ? rxcn: usart receive complete this flag bit is set w hen there are unread data in the recei v e buffer and cleared w hen the recei v e buffer is empty (that is, does not contain any unread data). if the recei v er is disabled, the recei v e buffer w ill be flushed and cons equently the rxcn bit w ill become zero. the rxcn flag can be used to generate a recei v e complete interrupt (see description of the rxcien bit). ? bit 6 ? txcn: usart transmit complete this flag bit is set w hen the entire frame in the transmit shift register has been shifted out and there are no ne w data currently present in the transmit buffer (udrn). the txcn flag bit is auto- matically cleared w hen a transmit complete interrupt is executed, or it can be cleared by w riting a one to its bit location. the txcn flag can generate a transmit complete interrupt (see description of the txcien bit). ? bit 5 ? udren: usart data register empty the udren flag indicates if the transm it buffer (udrn) is ready to recei v e ne w data. if udren is one, the buffer is empty, and therefore ready to be w ritten. the udren flag can generate a data register empty interrupt (see description of the udrien bit). udren is set after a reset to indicate that the transmitter is ready. ? bit 4 ? fen: frame error this bit is set if the next character in the recei v e buffer had a frame error w hen recei v ed. i.e., w hen the first stop bit of the next character in the recei v e buffer is zero. this bit is v alid until the recei v e buffer (udrn) is read. the fen bit is zero w hen the stop bit of recei v ed data is one. al w ays set this bit to zero w hen w riting to ucsrna. ? bit 3 ? dorn: data overrun this bit is set if a data o v errun condition is detected. a data o v errun occurs w hen the recei v e buffer is full (t w o characters), it is a ne w character w aiting in the recei v e shift register, and a bit 76543210 rxcn txcn udren fen dorn upen u2xn mpcmn ucsrna read/ w riterr/wrrrrr/wr/w initial v alue00100000 195 7593l?avr?09/12 at90usb64/128 ne w start bit is detected. this bit is v alid until the recei v e buffer (udrn) is read. al w ays set this bit to zero w hen w riting to ucsrna. ? bit 2 ? upen: usart parity error this bit is set if the next character in the recei v e buffer had a parity error w hen recei v ed and the parity checking w as enabled at that point (upmn1 = 1). this bit is v alid until the recei v e buffer (udrn) is read. al w ays set this bit to zero w hen w riting to ucsrna. ? bit 1 ? u2xn: double the usart transmission speed this bit only has effect for the asynchronous operation. write this bit to zero w hen using syn- chronous operation. writing this bit to one w ill reduce the di v isor of the baud rate di v ider from 16 to 8 effecti v ely dou- bling the transfer rate for asynchronous communication. ? bit 0 ? mpcmn: multi-processor communication mode this bit enables the multi-processor comm unication mode. when the mpcmn bit is w ritten to one, all the incoming frames recei v ed by the usart recei v er that do not contain address infor- mation w ill be ignored. the transmitter is unaffected by the mpcmn setting. for more detailed information see ?multi-processor communication mode? on page 192 . 19.9.3 ucsrnb ? usart control and status register n b ? bit 7 ? rxcien: rx comp lete interrupt enable n writing this bit to one enables inte rrupt on the rxcn flag. a usart recei v e complete interrupt w ill be generated only if the rxcien bit is w ritten to one, the global interrupt flag in sreg is w ritten to one and the rxcn bit in ucsrna is set. ? bit 6 ? txcien: tx complete interrupt enable n writing this bit to one enables interrupt on the txcn flag. a usart trans mit complete interrupt w ill be generated only if the txcien bit is w ritten to one, the global interrupt flag in sreg is w ritten to one and the txcn bit in ucsrna is set. ? bit 5 ? udrien: usart data register empty interrupt enable n writing this bit to one enables interrupt on the udre n flag. a data regist er empty interrupt w ill be generated only if the udrien bit is w ritten to one, the global interrupt flag in sreg is w ritten to one and the udren bit in ucsrna is set. ? bit 4 ? rxenn: receiver enable n writing this bit to one enables the usart recei v er. the recei v er w ill o v erride normal port oper- ation for the rxdn pin w hen enabled. disabling the recei v er w ill flush the recei v e buffer in v alidating the fen, dorn, and upen flags. ? bit 3 ? txenn: transmitter enable n writing this bit to one enables the usart transmitter. the transmitter w ill o v erride normal port operation for the txdn pin w hen enabled. the disabling of the transmitter ( w riting txenn to bit 7 6 5 4 3 2 1 0 rxcien txcien udrien rxenn txenn ucszn2 rxb8n txb8n ucsrnb read/ w rite r/w r/w r/w r/w r/w r/w r r/w initial v alue 0 0 0 0 0 0 0 0 196 7593l?avr?09/12 at90usb64/128 zero) w ill not become effecti v e until ongoing and pending transmissions are completed, that is, w hen the transmit shift register and transmit buffer register do not contain data to be trans- mitted. when disabled, the transmitter w ill no longer o v erride the txdn port. ? bit 2 ? ucszn2: character size n the ucszn2 bits combined w ith the ucszn1:0 bit in ucsrnc sets the number of data bits (character size) in a frame the recei v er and transmitter use. ? bit 1 ? rxb8n: receive data bit 8 n rxb8n is the ninth data bit of the recei v ed character w hen operating w ith serial frames w ith nine data bits. must be read before reading the lo w bits from udrn. ? bit 0 ? txb8n: transmit data bit 8 n txb8n is the ninth data bit in the character to be transmitted w hen operating w ith serial frames w ith nine data bits. must be w ritten before w riting the lo w bits to udrn. 19.9.4 ucsrnc ? usart control and status register n c ? bits 7:6 ? umseln1:0 usart mode select these bits select the mode of operation of the usartn as sho w n in table 19-4 . note: 1. see ?usart in spi mode? on page 202 for full description of the master spi mode (mspim) operation ? bits 5:4 ? upmn1:0: parity mode these bits enable and set type of parity generation and check. if enabled, the transmitter w ill automatically generate and send the parity of the transmitted data bits w ithin each frame. the recei v er w ill generate a parity v alue for the incoming data and compare it to the upmn setting. if a mismatch is detected, the upen flag in ucsrna w ill be set. bit 7 6 5432 1 0 umseln1 umseln0 upmn1 upmn0 us bsn ucszn1 ucszn0 ucpoln ucsrnc read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue 0 0 0 0 0 1 1 0 table 19-4. umseln bits settings. umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 10(reser v ed) 1 1 master spi (mspim) (1) table 19-5. upmn bits settings. upmn1 upmn0 parity mode 0 0 disabled 0 1 reser v ed 1 0 enabled, e v en parity 1 1 enabled, odd parity 197 7593l?avr?09/12 at90usb64/128 ? bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be inserted by the transmitter. the recei v er ignores this setting. ? bit 2:1 ? ucszn1:0: character size the ucszn1:0 bits combined w ith the ucszn2 bit in ucsrnb sets the number of data bits (character size) in a frame the recei v er and transmitter use. ? bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. write this bit to zero w hen asynchronous mode is used. the ucpoln bit sets the relationship bet w een data output change and data input sample, and the synchronous clock (xckn). 19.9.5 ubrrln and ubrrhn ? us art baud rate registers table 19-6. usbs bit settings. usbsn stop bit(s) 01-bit 12-bit table 19-7. ucszn bits settings. ucszn2 ucszn1 ucszn0 character size 0 0 0 5-bit 0 0 1 6-bit 0 1 0 7-bit 0 1 1 8-bit 100reser v ed 101reser v ed 110reser v ed 1 1 1 9-bit table 19-8. ucpoln bit settings. ucpoln transmitted data changed (output of txdn pin) received data sampled (input on rxdn pin) 0 rising xckn edge falling xckn edge 1 falling xckn edge rising xckn edge bit 1514131211109 8 ? ? ? ? ubrr[11:8] ubrrhn ubrr[7:0] ubrrln 76543210 read/ w riterrrrr/wr/wr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 00000000 198 7593l?avr?09/12 at90usb64/128 ? bit 15:12 ? reserved bits these bits are reser v ed for future use. for compatibility w ith future de v ices, these bit must be w ritten to zero w hen ubrrh is w ritten. ? bit 11:0 ? ubrr11:0: usart baud rate register this is a 12-bit register w hich contains the usart baud rate. the ubrrh contains the four most significant bits, and the ubrrl contains th e eight least significant bits of the usart baud rate. ongoing transmissions by the transmitter and recei v er w ill be corrupted if the baud rate is changed. writing ubrrl w ill trigger an immediate update of the baud rate prescaler. 19.10 examples of bau d rate setting for standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the ubrr settings in table 19-9 to table 19-12 on page 201 . ubrr v alues w hich yield an actual baud rate differing less than 0.5% from the tar- get baud rate, are bold in the table. higher error ratings are acceptable, but the recei v er w ill ha v e less noise resistance w hen the error ratings are high, especially for large serial frames (see ?asynchronous operational range? on page 191 ). the error v alues are calculated using the fol- lo w ing equation: error[%] baudrate closest match baudrate -------------------------------------------------------- 1 ? ?? ?? 100% ? = table 19-9. examples of ubrrn settings for comm only used oscilla tor frequencies. baud rate [bps] f osc = 1.0000mhz f osc = 1.8432mhz f osc = 2.0000mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 250.2%510.2%470.0%950.0%510.2%1030.2% 4800 120.2%250.2%230.0%470.0%250.2%510.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k??????00.0%???? 250k??????????00.0% max. (1) 62.5kbps 125kbps 115.2kbps 230.4kbps 125kbps 250kbps 1. ubrr = 0, error = 0.0%. 199 7593l?avr?09/12 at90usb64/128 table 19-10. examples of ubrrn settings for comm only used oscilla tor frequencies. baud rate [bps] f osc = 3.6864mhz f osc = 4.0000mhz f osc = 7.3728mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 230.0%470.0%250.2%510.2%470.0%950.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 11 0.0% 23 0.0% 12 0. 2% 25 0.2% 23 0.0% 47 0.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 0.5m ? ? 0 -7.8% ? ? 0 0.0% 0 -7.8% 1 -7.8% 1m ??????????0-7.8% max. (1) 230.4kbps 460.8kbps 250kbps 0.5mbps 460.8kbps 921.6kbps 1. ubrr = 0, error = 0.0%. 200 7593l?avr?09/12 at90usb64/128 table 19-11. examples of ubrrn settings for comm only used oscilla tor frequencies. baud rate [bps] f osc = 8.0000mhz f osc = 11.0592mhz f osc = 14.7456mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 25 0.2% 51 0.2% 35 0. 0% 71 0.0% 47 0.0% 95 0.0% 28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 12 0.2% 25 0.2% 17 0. 0% 35 0.0% 23 0.0% 47 0.0% 57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 0.5m 0 0.0% 1 0.0% ? ? 2 -7.8% 1 -7.8% 3 -7.8% 1m ? ? 0 0.0% ? ? ? ? 0 -7.8% 1 -7.8% max. (1) 0.5mbps 1mbps 691.2kbps 1.3824mbps 921.6kbps 1.8432mbps 1. ubrr = 0, error = 0.0%. 201 7593l?avr?09/12 at90usb64/128 table 19-12. examples of ubrrn settings for comm only used oscilla tor frequencies. baud rate [bps] f osc = 16.0000mhz f osc = 18.4320mhz f osc = 20.0000mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrr error ubrr error ubrr error ubrr error ubrr error ubrr error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2% 57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9% 76.8k 12 0.2% 25 0.2% 14 0.0% 29 0.0% 15 1.7% 32 -1.4% 115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4% 230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5m 1 0.0% 3 0.0% ? ? 4 -7.8% ? ? 4 0.0% 1m 0 0.0% 1 0.0% ? ? ? ? ? ? ? ? max. (1) 1mbps 2mbps 1.152mbps 2.304mbps 1.25mbps 2.5mbps 1. ubrr = 0, error = 0.0%. 202 7593l?avr?09/12 at90usb64/128 20. usart in spi mode the uni v ersal synchronous and asynchronous serial recei v er and transmitter (usart) can be set to a master spi compliant mode of operation. the master spi mode (mspim) has the follo w - ing features: ? full duplex, three-wire synchronous data transfer ? master operation ? supports all four spi modes of operation (mode 0, 1, 2, and 3) ? lsb first or msb first data tran sfer (configurable data order) ? queued operation (double buffered) ? high resolution baud rate generator ? high speed operation (fxckmax = fck/2) ? flexible interrupt generation 20.1 overview setting both umseln1:0 bits to one enables the usart in mspim logic. in this mode of opera- tion the spi master control logic takes direct control o v er the usart resources. these resources include the transmitter and recei v er shift register and buffers, and the baud rate gen- erator. the parity generator and checker, the data and clock reco v ery logic, and the rx and tx control logic is disabled. the usart rx and tx control logic is replaced by a common spi transfer control logic. ho w e v er, the pin control logic and interrupt generation logic is identical in both modes of operation. the i/o register locations are the same in both modes. ho w e v er, some of the functionality of the control registers changes w hen using mspim. 20.2 clock generation the clock generation logic generates the base clock for the transmitter and recei v er. for usart mspim mode of operation only internal cl ock generation (that is, master operation) is supported. the data direction register for the xckn pin (ddr_xckn) must therefore be set to one (that is, as output) for the usart in mspim to operate correctly. preferably the ddr_xckn should be set up before the usart in mspim is enabled (that is, txenn and rxenn bit set to one). the internal clock generation used in mspim mode is identical to the usart synchronous mas- ter mode. the baud rate or ubrrn setting can therefore be calculated using the same equations, see table 20-1 . note: 1. the baud rate is defined to be the transfer rate in bit per second (bps). table 20-1. equations for calculating baud rate register setting. operating mode equation for calculating baud rate (1) equation for calculating ubrrn value synchronous master mode baud f osc 2 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = 203 7593l?avr?09/12 at90usb64/128 baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095) 20.3 spi data modes and timing there are four combinations of xckn (sck) phase and polarity w ith respect to serial data, w hich are determined by control bits ucphan and ucpoln. the data transfer timing diagrams are sho w n in figure 20-1 . data bits are shifted out and latched in on opposite edges of the xckn signal, ensuring sufficient time for data sign als to stabilize. the ucpoln and ucphan function- ality is summarized in table 20-2 . note that changing the setting of any of these bits w ill corrupt all ongoing communication for both the recei v er and transmitter. figure 20-1. ucphan and ucpoln data transfer timing diagrams. 20.4 frame formats a serial frame for the mspim is defined to be one character of 8 data bits. the usart in mspim mode has t w o v alid frame formats: ? 8-bit data w ith msb first ? 8-bit data w ith lsb first a frame starts w ith the least or most significant data bit. then the next data bits, up to a total of eight, are succeeding, ending w ith the most or least significant bit accordingly. when a complete frame is transmitted, a ne w frame can directly follo w it, or the communication line can be set to an idle (high) state. the udordn bit in ucsrnc sets the frame form at used by the usart in mspim mode. the recei v er and transmitter use the same setting. note that changing the setting of any of these bits w ill corrupt all ongoin g communication fo r both the recei v er and transmitter. table 20-2. ucpoln and ucphan functionality. ucpoln ucphan spi mode leading edge trailing edge 0 0 0 sample (rising) setup (falling) 0 1 1 setup (rising) sample (falling) 1 0 2 sample (falling) setup (rising) 1 1 3 setup (falling) sample (rising) xck d a t a s et u p (txd) d a t a sa mple (rxd) xck d a t a s et u p (txd) d a t a sa mple (rxd) xck d a t a s et u p (txd) d a t a sa mple (rxd) xck d a t a s et u p (txd) d a t a sa mple (rxd) ucpol=0 ucpol=1 ucpha=0 ucpha=1 204 7593l?avr?09/12 at90usb64/128 16-bit data transfer can be achie v ed by w riting t w o data bytes to udrn. a uart transmit com- plete interrupt w ill then signal th at the 16-bit v alue has been shifted out. 20.4.1 usart mspim initialization the usart in mspim mode has to be initialized before any communication can take place. the initialization process normally consists of setting the baud rate, setting master mode of operation (by setting ddr_xckn to one), setting frame format and enabling the transmitter and the recei v er. only the transmitter can operate independently. for interrupt dri v en usart opera- tion, the global interrupt flag should be clea red (and thus interrupts globally disabled) w hen doing the initialization. note: to ensure immediate initialization of the xckn output the baud-rate register (ubrrn) must be zero at the time the transmitter is enabled. contrary to the normal mode usart operation the ubrrn must then be w ritten to the desired v alue after the transmitter is enabled, but before the first transmission is started. setting ubrrn to ze ro before enabling the transmitter is not neces- sary if the initialization is done immediatel y after a reset since ubrrn is reset to zero. before doing a re-initialization w ith changed baud rate, data mode, or frame format, be sure that there is no ongoing transmissions during the per iod the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxcn flag can be used to check that there are no unread data in the recei v e buffer. note that the txcn flag must be cleared befor e each transmission (before udrn is w ritten) if it is used for this purpose. the follo w ing simple usart initialization code examples sho w one assembly and one c func- tion that are equal in functionality. the examples assume polling (no interrupts enabled). the baud rate is gi v en as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. 205 7593l?avr?09/12 at90usb64/128 note: 1. see ?about code examples? on page 10. 20.5 data transfer using the usart in mspi mode requires the transmitter to be enabled, that is, the txenn bit in the ucsrnb register is set to one. when the transmitter is enabled, the normal port operation of the txdn pin is o v erridden and gi v en the function as the transmitter's serial output. enabling the recei v er is optional and is done by setting the rxenn bit in the ucsrnb register to one. when the recei v er is enabled, the normal pin operation of the rxdn pin is o v erridden and gi v en the function as the recei v er's serial input. the xckn w ill in both cases be used as the transfer clock. assembly code example (1) usart_init: clr r18 out ubrrnh,r18 out ubrrnl,r18 ; setting the xckn port pin as output, enables master mode. sbi xckn_ddr, xckn ; set mspi mode of operation and spi data mode 0. ldi r18, (1< 208 7593l?avr?09/12 at90usb64/128 20.6.3 ucsrnb ? usart mspim control and status register n b ? bit 7 - rxcien: rx complete interrupt enable writing this bit to one enables inte rrupt on the rxcn flag. a usart recei v e complete interrupt w ill be generated only if the rxcien bit is w ritten to one, the global interrupt flag in sreg is w ritten to one and the rxcn bit in ucsrna is set. ? bit 6 - txcien: tx complete interrupt enable writing this bit to one enables interrupt on the txcn flag. a usart trans mit complete interrupt w ill be generated only if the txcien bit is w ritten to one, the global interrupt flag in sreg is w ritten to one and the txcn bit in ucsrna is set. ? bit 5 - udrie: usart data re gister empty interrupt enable writing this bit to one enables interrupt on the udre n flag. a data regist er empty interrupt w ill be generated only if the udrie bit is w ritten to one, the global interrupt flag in sreg is w ritten to one and the udren bit in ucsrna is set. ? bit 4 - rxenn: receiver enable writing this bit to one enables the usart recei v er in mspim mode. the recei v er w ill o v erride normal port operation for the rxdn pin w hen enabled. disabling the recei v er w ill flush the recei v e buffer. only enabling the recei v er in mspi mode (that is, setting rxenn=1 and txenn=0) has no meaning since it is the transmit ter that controls the transfer clock and since only master mode is supported. ? bit 3 - txenn: transmitter enable writing this bit to one enables the usart transmitter. the transmitter w ill o v erride normal port operation for the txdn pin w hen enabled. the disabling of the transmitter ( w riting txenn to zero) w ill not become effecti v e until ongoing and pending transmissions are completed, that is, w hen the transmit shift register and transmit buffer register do not contain data to be trans- mitted. when disabled, the transmitter w ill no longer o v erride the txdn port. ? bit 2:0 - reserved bits in mspi mode when in mspi mode, these bits are reser v ed for future use. for compatibility w ith future de v ices, these bits must be w ritten to zero w hen ucsrnb is w ritten. 20.6.4 ucsrnc ? usart mspim control and status register n c ? bit 7:6 - umseln1:0: usart mode select these bits select the mode of operation of the usart as sho w n in table 20-3 on page 209 . see ?ucsrnc ? usart control and status register n c? on page 196 for full description of the nor- bit 7 6 5 4 3 2 1 0 rxcien txcien udrie rxenn txenn - - - ucsrnb read/ w rite r/w r/w r/w r/w r/w r r r initial v alue 0 0 0 0 0 1 1 0 bit 7 6 5432 1 0 umseln1 umseln0 - - - udordn ucphan ucpoln ucsrnc read/ w rite r/w r/w r r r r/w r/w r/w initial v alue 0 0 0 0 0 1 1 0 209 7593l?avr?09/12 at90usb64/128 mal usart operation. the mspim is enabled w hen both umseln bits are set to one. the udordn, ucphan, and ucpoln can be set in the same w rite operation w here the mspim is enabled. ? bit 5:3 - reserved bits in mspi mode when in mspi mode, these bits are reser v ed for future use. for compatibility w ith future de v ices, these bits must be w ritten to zero w hen ucsrnc is w ritten. ? bit 2 - udordn: data order when set to one the lsb of the data w ord is transmitted first. when set to zero the msb of the data w ord is transmitted first. refer to the frame formats section page 4 for details. ? bit 1 - ucphan: clock phase the ucphan bit setting determine if data is sampled on the leasing edge (first) or tailing (last) edge of xckn. refer to the spi data modes and timing section page 4 for details. ? bit 0 - ucpoln: clock polarity the ucpoln bit sets the polarity of the xc kn clock. the combination of the ucpoln and ucphan bit settings determine the timing of the data transfer. refer to the spi data modes and timing section page 4 for details. 20.6.5 ubrrnl and ubrrnh ? usart mspim baud rate registers the function and bit description of the baud rate registers in mspi mode is identical to normal usart operation. see ?ubrrln and ubrrhn ? usart baud rate registers? on page 197. 20.7 avr usart mspim vs. avr spi the usart in mspim mode is fully compatible w ith the avr spi regarding: ? master mode timing diagram. ? the ucpoln bit functionality is identical to the spi cpol bit ? the ucphan bit functionality is identical to the spi cpha bit ? the udordn bit functionality is identical to the spi dord bit ho w e v er, since the usart in mspim mode reuses the usart resources, the use of the usart in mspim mode is some w hat different compared to the spi. in addition to differences of the control register bits, and that only master operation is supported by the usart in mspim mode, the follo w ing features differ bet w een the t w o modules: ? the usart in mspim mode includes (double) buffering of the transmitter. the spi has no buffer ? the usart in mspim mode recei v er includes an additional buffer le v el ? the spi wcol (write collision) bit is not included in usart in mspim mode table 20-3. umseln bits settings. umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reser v ed) 1 1 master spi (mspim) 210 7593l?avr?09/12 at90usb64/128 ? the spi double speed mode (spi2x) bit is not included. ho w e v er, the same effect is achie v ed by setting ubrrn accordingly ? interrupt timing is not compatible ? pin control differs due to the master only operation of the usart in mspim mode a comparison of the usart in mspim mode and the spi pins is sho w n in table 20-4 on page 210 . table 20-4. comparison of usart in mspim mode and spi pins. usart_mspim spi comment txdn mosi master out only rxdn miso master in only xckn sck (functionally identical) (n/a) ss not supported by usart in mspim 211 7593l?avr?09/12 at90usb64/128 21. 2-wire serial interface 21.1 features ? simple yet powerful and flexible communication interface, only two bus lines needed ? both master and sla ve operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slave addresses ? multi-master arbitration support ? up to 400khz data transfer speed ? slew-rate limited output drivers ? noise suppression circuitry rejects spikes on bus lines ? fully programmable slave address with general call support ? address recognition causes wake-u p when avr is in sleep mode 21.2 2-wire serial in terface bus definition the 2- w ire serial interface (twi) is ideally suited for typical mi crocontroller app lications. the twi protocol allo w s the systems designer to interconnect up to 128 different de v ices using only t w o bi-directional bus lines, one for clock (scl) a nd one for data (sda). the only external hard- w are needed to implement the bus is a single pull-up resistor for each of the twi bus lines. all de v ices connected to the bus ha v e indi v idual addresses, and mechanisms for resol v ing bus contention are inherent in the twi protocol. figure 21-1. twi bus interconnection. 21.2.1 twi terminology the follo w ing definitions are frequently encountered in this section. the po w er reduction twi bit, prtwi bit in ?prr0 ? po w er reduction register 0? on page 54 must be w ritten to zero to enable the 2- w ire serial interface. device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc table 21-1. twi terminology. term description master the de v ice that initiates and terminates a transmission. the master also generates the scl clock. sla v e the de v ice addressed by a master. transmitter the de v ice placing data on the bus. recei v er the de v ice reading data from the bus. 212 7593l?avr?09/12 at90usb64/128 21.2.2 electrical interconnection as depicted in figure 21-1 on page 211 , both bus lines are connected to the positi v e supply v olt- age through pull-up resistors. the bus dri v ers of all twi-compliant de v ices are open-drain or open-collector. this implements a w ired-and function w hich is essential to the operation of the interface. a lo w le v el on a twi bus line is generated w hen one or more twi de v ices output a zero. a high le v el is output w hen all twi de v ices trim-state their outputs, allo w ing the pull-up resistors to pull the line hi gh. note that all avr de v ices connected to the twi bus must be po w - ered in order to allo w any bus operation. the number of de v ices that can be connected to the bus is only limited by the bus capacitance limit of 400pf and the 7-bit sla v e address space. a detailed specific ation of the electrical charac- teristics of the twi is gi v en in ?spi timing characteristics? on page 395 . t w o different sets of specifications are presented there, one rele v ant for bus speeds belo w 100khz, and one v alid for bus speeds up to 400khz. 21.3 data transfer and frame format 21.3.1 transferring bits each data bit transferred on the twi bus is accompanied by a pulse on the clock line. the le v el of the data line must be stable w hen the clock line is high. the only exception to this rule is for generating start and stop conditions. figure 21-2. data v alidity. 21.3.2 start and stop conditions the master initiates and terminates a data tr ansmission. the transmission is initiated w hen the master issues a start condition on the bus, and it is terminated w hen the master issues a stop condition. bet w een a start and a stop condition, the bus is considered busy, and no other master should try to seize control of the bus. a special case occurs w hen a ne w start condition is issued bet w een a start and stop condition. th is is referred to as a repeated start condition, and is used w hen the master w ishes to initiate a ne w transfer w ithout relin- quishing control of the bus. after a repeated start, the bus is considered busy until the next stop. this is identical to the start beha v ior, and therefore start is used to describe both start and repeated start for the remainder of this datasheet, unless other w ise noted. as depicted belo w , start and stop conditions are signalled by changing the le v el of the sda line w hen the scl line is high. sda scl d a t a s t ab le d a t a s t ab le d a t a ch a nge 213 7593l?avr?09/12 at90usb64/128 figure 21-3. start, repeated start and stop conditions. 21.3.3 address packet format all address packets transmitted on the twi bus are nine bits long, consisting of se v en address bits, one read/write control bit and an ackno w ledge bit. if the read/write bit is set, a read operation is to be performed, other w ise a w rite operation should be performed. when a sla v e recognizes that it is being addressed, it should ackno w ledge by pulling sda lo w in the ninth scl (ack) cycle. if the addressed sla v e is busy, or for some other reason can not ser v ice the mas- ter?s request, the sda line should be left high in the ack clock cycle. the master can then transmit a stop condition, or a repeat ed start condition to initiate a ne w transmission. an address packet consisting of a sla v e address and a read or a write bit is called sla+r or sla+w, respecti v ely. the msb of the address byte is transmitted first. sla v e addresses can freely be allocated by the designer, but the address 0000 000 is reser v ed for a general call. when a general call is issued, all sla v es should respond by pulling the sda line lo w in the ack cycle. a general call is used w hen a master w ishes to transmit the same message to se v eral sla v es in the system. when the general call address follo w ed by a write bit is transmitted on the bus, all sla v es set up to ackno w ledge the general call w ill pull the sda line lo w in the ack cycle. the follo w ing data packets w ill then be recei v ed by all the sla v es that ackno w ledged the general call. note that transmitting the general call address follo w ed by a read bit is meaningless, as this w ould cause contention if se v eral sla v es started transmitting different data. all addresses of the format 1111 xxx should be reser v ed for future purposes. figure 21-4. address packet format. 21.3.4 data packet format all data packets transmitted on the twi bus are nine bits long, consisting of one data byte and an ackno w ledge bit. during a data transfer, the master generates the clock and the start and sda scl start stop repeated start stop start sda scl start 12 789 addr msb addr lsb r/w ack 214 7593l?avr?09/12 at90usb64/128 stop conditions, w hile the recei v er is responsible for ackno w ledging the reception. an ackno w ledge (ack) is signalled by the recei v er pulling the sda line lo w during the ninth scl cycle. if the recei v er lea v es the sda line high, a nack is signalled. when the recei v er has recei v ed the last byte, or for some reason cannot recei v e any more bytes, it should inform the transmitter by sending a nack after the final byte. the msb of the data byte is transmitted first. figure 21-5. data packet format. 21.3.5 combining address and data packets into a transmission a transmission basically consists of a start co ndition, a sla+r/w, one or more data packets and a stop condition. an empty message, consisting of a start follo w ed by a stop condi- tion, is illegal. note that the wired-an ding of the scl line can be used to implement handshaking bet w een the master and the sla v e. the sla v e can extend the scl lo w period by pulling the scl line lo w . this is useful if the clock speed set up by the master is too fast for the sla v e, or the sla v e needs extra time for processing bet w een the data transmissions. the sla v e extending the scl lo w period w ill not affect the scl high period, w hich is determined by the master. as a consequence, the sla v e can reduce the twi data transfer speed by prolonging the scl duty cycle. figure 21-6 sho w s a typical data transmission. note that se v eral data bytes can be transmitted bet w een the sla+r/w and the stop condition, depending on the soft w are protocol imple- mented by the application soft w are. figure 21-6. typical data transmission. 12 789 d a t a msb d a t a lsb ack aggreg a te sda sda from tr a n s mitter sda from receiver scl from m as ter sla+r/w d a t a b yte stop, repeated start or next d a t a b yte 12 789 d a t a b yte d a t a msb d a t a lsb ack sda scl start 12 789 addr msb addr lsb r/w ack sla+r/w stop 215 7593l?avr?09/12 at90usb64/128 21.4 multi-master bus systems, ar bitration and synchronization the twi protocol allo w s bus systems w ith se v eral masters. special concerns ha v e been taken in order to ensure that transmissions w ill proceed as normal, e v en if t w o or more masters initiate a transmission at the same time. t w o problems arise in multi-master systems: ? an algorithm must be implemented allo w ing only one of the masters to complete the transmission. all other masters should cease transmission w hen they disco v er that they ha v e lost the selection process. this selection proc ess is called arbitration. when a contending master disco v ers that it has lost the arbitration process, it should immediately s w itch to sla v e mode to check w hether it is being addressed by the w inning master. the fact that multiple masters ha v e started transmission at the same time should not be detectable to the sla v es, i.e. the data being transferred on the bus must not be corrupted ? different masters may use different scl frequencies. a scheme must be de v ised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. this w ill facilitate the arbitration process the w ired-anding of the bus lines is used to sol v e both these problems. the serial clocks from all masters w ill be w ired-anded, yielding a combined clock w ith a high period equal to the one from the master w ith the shortest high period. the lo w period of the combined clock is equal to the lo w period of the master w ith the longest lo w period. note that all masters listen to the scl line, effecti v ely starting to count their scl high and lo w time-out periods w hen the combined scl line goes high or lo w , respecti v ely. figure 21-7. scl synchronization bet w een multiple masters. arbitration is carried out by all masters cont inuously monitoring the sda line after outputting data. if the v alue read from the sda line does not match the v alue the master had output, it has lost the arbitration. note that a master can only lose arbitration w hen it outputs a high sda v alue w hile another master outputs a lo w v alue. the losing master should immediately go to sla v e mode, checking if it is being addressed by the w inning master. the sda line should be left high, but losing masters are allo w ed to generate a clock signal until the end of the current data or address packet. arbitration w ill continue until only one master remains, and this may take many ta low ta high scl from m as ter a scl from m as ter b scl bus line tb low tb high m as ter s s t a rt co u nting low period m as ter s s t a rt co u nting high period 216 7593l?avr?09/12 at90usb64/128 bits. if se v eral masters are trying to address the same sla v e, arbitration w ill continue into the data packet. figure 21-8. arbitration bet w een t w o masters. note that arbitration is not allo w ed bet w een: ? a repeated start cond ition and a data bit ? a stop condition and a data bit ? a repeated start and a stop condition it is the user soft w are?s responsibility to ensure that t hese illegal arbitration conditions ne v er occur. this implies that in multi-master systems, all data transfers must use the same composi- tion of sla+r/w and data packets. in other w ords: all transmissions must contain the same number of data packets, other w ise the result of the arbitration is undefined. 21.5 overview of the twi module the twi module is comprised of se v eral submodules, as sho w n in figure 21-9 on page 217 . all registers dra w n in a thick line are accessible through the avr data bus. sda from m as ter a sda from m as ter b sda line synchronized scl line start m as ter a lo s e s a r b itr a tion, sda a sda 217 7593l?avr?09/12 at90usb64/128 figure 21-9. o v er v ie w of the twi module. 21.5.1 scl and sda pins these pins interface the avr twi w ith the rest of the mcu system. the output dri v ers contain a sle w -rate limiter in order to conform to the twi s pecification. the input stages contain a spike suppression unit remo v ing spikes shorter than 50ns. note that the internal pull-ups in the avr pads can be enabled by setting the port bits corresponding to the scl and sda pins, as explained in the i/o port section. the internal pull-ups can in some systems eliminate the need for external ones. 21.5.2 bit rate generator unit this unit controls the period of scl w hen operating in a master mode. the scl period is con- trolled by settings in the twi bit rate register (twbr) and the prescaler bits in the twi status register (twsr). sla v e operation does not depend on bit rate or prescaler settings, but the cpu clock frequency in the sla v e must be at least 16 times higher than the scl frequency. note that sla v es may prolong the scl lo w period, thereby reducing the a v erage twi bus clock period. the scl frequency is generated according to the follo w ing equation: ? twbr = value of the twi bit rate register ? twps = value of the prescaler bits in the twi status register twi u nit addre ss regi s ter (twar) addre ss m a tch u nit addre ss comp a r a tor control u nit control regi s ter (twcr) st a t us regi s ter (twsr) st a te m a chine a nd s t a t us control scl slew-r a te control spike filter sda slew-r a te control spike filter bit r a te gener a tor bit r a te regi s ter (twbr) pre s c a ler b us interf a ce u nit start / stop control ar b itr a tion detection ack spike su ppre ss ion addre ss /d a t a s hift regi s ter (twdr) scl frequency cpu clock frequency 16 2(twbr) 4 twps ? + ----------------------------------------------------------- = 218 7593l?avr?09/12 at90usb64/128 note: twbr should be 10 or higher if the twi operates in master mode. if twbr is lo w er than 10, the master may produce an incorrect output on sda and scl for the reminder of the byte. the prob- lem occurs w hen operating the twi in master mode, sending start + sla + r/w to a sla v e (a sla v e does not need to be connected to the bus for the condition to happen). 21.5.3 bus interface unit this unit contains the data and address shif t register (twdr), a start/stop controller and arbitration detection hard w are. the twdr contains the address or data bytes to be transmitted, or the address or data bytes recei v ed. in addition to the 8-bit twdr, the bus interface unit also contains a register containing the (n)ack bit to be transmitted or recei v ed. this (n)ack regis- ter is not directly accessible by the application soft w are. ho w e v er, w hen recei v ing, it can be set or cleared by manipulating the twi control r egister (twcr). when in transmitter mode, the v alue of the recei v ed (n)ack bit can be determined by the v alue in the twsr. the start/stop controller is responsible for gene ration and detection of start, repeated start, and stop conditions. the start/stop controller is able to detect start and stop conditions e v en w hen the avr mcu is in one of the sleep modes, enabling the mcu to w ake up if addressed by a master. if the twi has initiated a transmission as master, the arbitration detection hard w are continu- ously monitors the transmission trying to determine if arbitration is in process. if the twi has lost an arbitration, the control unit is informed. correct action can then be taken and appropriate status codes generated. 21.5.4 address match unit the address match unit checks if recei v ed address bytes match the se v en-bit address in the twi address register (twar). if the twi general call recognition enable (twgce) bit in the twar is w ritten to one, all incoming address bits w ill also be compared a gainst the general call address. upon an address match, the control unit is informed, allo w ing correct action to be taken. the twi may or may not ackno w ledge its address, depending on settings in the twcr. the address match unit is able to compare addresses e v en w hen the avr mcu is in sleep mode, enabling the mcu to w ake up if addressed by a master. if another interrupt (e.g., int0) occurs during twi po w er-do w n address match and w akes up the cpu, the twi aborts opera- tion and return to it?s idle state. if this cause any problems, ensure that twi address match is the only enabled interrupt w hen entering po w er-do w n. 21.5.5 control unit the control unit monitors the twi bus and generates responses corresponding to settings in the twi control register (twcr). when an e v ent requiring the attention of the application occurs on the twi bus, the twi interrupt flag (twint) is asserted. in the next clock cycle, the twi sta- tus register (twsr) is updated w ith a status code identifying the e v ent. the twsr only contains rele v ant status information w hen the twi interrupt flag is asserted. at all other times, the twsr contains a special st atus code indicating that no rele v ant status information is a v ail- able. as long as the twint flag is set, the scl line is held lo w . this allo w s the application soft w are to complete its tasks before allo w ing the twi transmission to continue. the twint flag is set in the follo w ing situations: ? after the twi has transmitted a start/repeated start condition ? after the twi has transmitted sla+r/w ? after the twi has transmitted an address byte ? after the twi has lost arbitration 219 7593l?avr?09/12 at90usb64/128 ? after the twi has been addressed by o w n sla v e address or general call ? after the twi has recei v ed a data byte ? after a stop or repeated start has been recei v ed w hile still addressed as a sla v e ? when a bus error has occurred due to an illegal start or stop condition 21.6 twi register description 21.6.1 twbr ? twi bit rate register ? bits 7..0 ? twi bit rate register twbr selects the di v ision factor for the bit rate generator. the bit rate generator is a frequency di v ider w hich generates the scl clock frequency in the master modes. see ?bit rate generator unit? on page 217 for calculating bit rates. 21.6.2 twcr ? twi control register the twcr is used to control the operation of the twi. it is used to enable the twi, to initiate a master access by applying a start condition to the bus, to generate a recei v er ackno w ledge, to generate a stop condition, and to control halting of the bus w hile the data to be w ritten to the bus are w ritten to the twdr. it also indicates a w rite collision if da ta is attempted w ritten to twdr w hile the register is inaccessible. ? bit 7 ? twint: twi interrupt flag this bit is set by hard w are w hen the twi has finished its curre nt job and expects application soft w are response. if the i-bit in sreg and twie in twcr are set, the mcu w ill jump to the twi interrupt vector. while the twint flag is set, the scl lo w period is stretched. the twint flag must be cleared by soft w are by w riting a logic one to it. note that this flag is not automati- cally cleared by hard w are w hen executing the interrupt routine. also note that clearing this flag starts the operation of the twi, so all accesses to the twi address register (twar), twi sta- tus register (twsr), and twi data register (twdr) must be complete before clearing this flag. ? bit 6 ? twea: twi enable acknowledge bit the twea bit controls the generation of the ackno w ledge pulse. if the twea bit is w ritten to one, the ack pulse is generated on the twi bus if the follo w ing conditions are met: 1. the de v ice?s o w n sla v e address has been recei v ed. 2. a general call has been recei v ed, w hile the twgce bit in the twar is set. 3. a data byte has been recei v ed in master recei v er or sla v e recei v er mode. by w riting the twea bit to zero, the de v ice can be v irtually disconnected from the 2- w ire serial bus temporarily. address rec ognition can then be resumed by w riting the twea bit to one again. bit 76543210 twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 twbr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 twint twea twsta twsto twwc twen ? twie twcr read/write r/w r/w r/w r/w r r/w r r/w initial value 0 0 0 0 0 0 0 0 220 7593l?avr?09/12 at90usb64/128 ? bit 5 ? twsta: twi start condition bit the application w rites the twsta bit to one w hen it desires to become a master on the 2- w ire serial bus. the twi hard w are checks if the bus is a v ailable, and generates a start condition on the bus if it is free. ho w e v er, if the bus is not free, the twi w aits until a stop condition is detected, and then generates a ne w start condition to claim the bus master status. twsta must be cleared by soft w are w hen the start condition has been transmitted. ? bit 4 ? twsto: twi stop condition bit writing the twsto bit to one in master mode w ill generate a stop condition on the 2- w ire serial bus. when the stop condition is exec uted on the bus, the twsto bit is cleared auto- matically. in sla v e mode, setting the twsto bit can be used to reco v er from an error condition. this w ill not generate a stop conditio n, but the twi returns to a w ell-defined unaddressed sla v e mode and releases the scl and sda lines to a high impedance state. ? bit 3 ? twwc: twi write collision flag the twwc bit is set w hen attempting to w rite to the twi data register ? twdr w hen twint is lo w . this flag is cleared by w riting the twdr register w hen twint is high. ? bit 2 ? twen: twi enable bit the twen bit enables twi operation and acti v ates the twi interface. when twen is w ritten to one, the twi takes control o v er the i/o pins connected to the scl and sda pins, enabling the sle w -rate limiters and spike f ilters. if this bit is w ritten to zero, the twi is s w itched off and all twi transmissions are terminated, regardless of any ongoing operation. ? bit 1 ? res: reserved bit this bit is a reser v ed bit and w ill al w ays read as zero. ? bit 0 ? twie: twi interrupt enable when this bit is w ritten to one, and the i-bit in sreg is set, the twi interrupt request w ill be acti- v ated for as long as the twint flag is high. 21.6.3 twsr ? twi status register ? bits 7..3 ? tws: twi status these 5 bits reflect the status of the twi logic and the 2- w ire serial bus. the different status codes are described later in th is section. note that the v alue read from twsr contains both the 5-bit status v alue and the 2-bit prescaler v alue. the application designer should mask the pres- caler bits to zero w hen checking the status bits. this makes status checking independent of prescaler setting. this approach is used in this datasheet, unless other w ise noted. ? bit 2 ? res: reserved bit this bit is reser v ed and w ill al w ays read as zero. ? bits 1..0 ? twps: twi prescaler bits these bits can be read and w ritten, and control the bit rate prescaler. bit 76543210 tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 twsr read/write r r r r r r r/w r/w initial value 1 1 1 1 1 0 0 0 221 7593l?avr?09/12 at90usb64/128 to calculate bit rates, see ?bit rate generator unit? on page 217 . the v alue of twps1..0 is used in the equation. 21.6.4 twdr ? twi data register in transmit mode, twdr contains the next byte to be transmitted. in recei v e mode, the twdr contains the last byte recei v ed. it is w ritable w hile the twi is not in the process of shifting a byte. this occurs w hen the twi interrupt flag (twint) is set by hard w are. note that the data regis- ter cannot be initialized by the user before the first interrupt occurs. the data in twdr remains stable as long as twint is se t. while data is shifted out, data on the bus is simultaneously shifted in. twdr al w ays contains the last byte present on the bus, except after a w ake up from a sleep mode by the twi interrupt. in this case, the contents of twdr is undefined. in the case of a lost bus arbitration, no data is lost in the transition from master to sla v e. handling of the ack bit is controlled automatically by the twi logic, the cpu cannot access the ack bit directly. ? bits 7..0 ? twd: twi data register these eight bits constitute the next data byte to be transmitted, or the latest data byte recei v ed on the 2- w ire serial bus. 21.6.5 twar ? twi (slave) address register the twar should be loaded w ith the 7-bit sla v e address (in the se v en most significant bits of twar) to w hich the twi w ill respond w hen programmed as a sla v e transmitter or recei v er, and not needed in the master modes. in multimaster systems, twar must be set in masters w hich can be addressed as sla v es by other masters. the lsb of twar is used to enable recognition of the general call address (0x00). there is an associated address comparator that looks for the sla v e address (or general call address if enabled) in the recei v ed serial address. if a match is found, an interrupt request is generated. ? bits 7..1 ? twa: twi (slave) address register these se v en bits constitute the sla v e address of the twi unit. table 21-2. twi bit rate prescaler. twps1 twps0 prescaler value 001 014 1016 1164 bit 76543210 twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 1 bit 76543210 twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 1 1 1 1 1 1 1 0 222 7593l?avr?09/12 at90usb64/128 ? bit 0 ? twgce: twi general call recognition enable bit if set, this bit enables the recognition of a general call gi v en o v er the 2- w ire serial bus. 21.6.6 twamr ? twi (slave) address mask register ? bits 7..1 ? twam: twi address mask the twamr can be loaded w ith a 7-bit sla v e address mask. each of the bits in twamr can mask (disable) the corresponding address bit in the twi address register (twar). if the mask bit is set to one then the address match logic ignores the compare bet w een the incoming address bit and the corresponding bit in twar. figure 21-10 sho w s the address match logic in detail. figure 21-10. twi address match logic, block diagram. ? bit 0 ? res: reserved bit this bit is reser v ed and w ill al w ays read as zero. 21.7 using the twi the avr twi is byte-oriented and interrupt based. interrupts are issued after all bus e v ents, like reception of a byte or transmission of a start condition. because the twi is interrupt-based, the application soft w are is free to carry on other operations during a twi byte transfer. note that the twi interrupt enable (twie) bit in twcr together w ith the global interrupt enable bit in sreg allo w the application to decide w hether or not assertion of the twint flag should gener- ate an interrupt request. if the twie bit is clear ed, the application must poll the twint flag in order to detect actions on the twi bus. when the twint flag is asserted, the twi has finished an operation and a w aits application response. in this case, the twi status register (twsr) contains a v alue indicating the current state of the twi bus. the application soft w are can then decide ho w the twi should beha v e in the next twi bus cycle by manipulating the twcr and twdr registers. figure 21-11 on page 223 is a simple example of ho w the application can interface to the twi hard w are. in this example, a master w ishes to transmit a single data byte to a sla v e. this description is quite abstract, a more detailed explanation follo w s later in this section. a simple code example implementing the desired beha v ior is also presented. bit 76543210 twam[6:0] ? twamr read/write r/w r/w r/w r/w r/w r/w r/w r initial value 0 0 0 0 0 0 0 0 address match address bit comparator 0 address bit comparator 6..1 twar0 twamr0 address bit 0 223 7593l?avr?09/12 at90usb64/128 figure 21-11. interfacing the application to the twi in a typical transmission. 1. the first step in a twi transmission is to transmit a start condition. this is done by w riting a specific v alue into twcr, instructing the twi hard w are to transmit a start condition. which v alue to w rite is described later on. ho w e v er, it is important that the twint bit is set in the v alue w ritten. writing a one to twint clears the flag. the twi w ill not start any operation as long as the tw int bit in twcr is set. immediately after the application has cleared twint, the twi w ill initiate transmission of the start condition. 2. when the start condition has been transmitted, the twint flag in twcr is set, and twsr is updated w ith a status code indicating that the start condition has success- fully been sent. 3. the application soft w are should no w examine the v alue of twsr, to make sure that the start condition w as successfully transmitted. if twsr indicates other w ise, the appli- cation soft w are might take some special action, lik e calling an error routine. assuming that the status code is as expected, the application must load sla+w into twdr. remember that twdr is used both for address and data. after twdr has been loaded w ith the desired sla+w, a specific v alue must be w ritten to twcr, instructing the twi hard w are to transmit the sla+w present in twdr. which v alue to w rite is described later on. ho w e v er, it is important that the twint bit is set in the v alue w ritten. writing a one to twint clears the flag. the twi w ill not start any operation as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi w ill initiate transmission of the address packet. 4. when the address packet has been transmitted, the twint flag in twcr is set, and twsr is updated w ith a status code indicating that the address packet has success- fully been sent. the status code w ill also reflect w hether a sla v e ackno w ledged the packet or not. 5. the application soft w are should no w examine the v alue of twsr, to make sure that the address packet w as successfully transmitted, and that the v alue of the ack bit w as as expected. if twsr indicates other w ise, the application soft w are might take some spe- cial action, like calling an error routine. assu ming that the status code is as expected, the application must load a data packet into twdr. subsequently, a specific v alue must be w ritten to twcr, instructing the twi hard w are to transmit the data packet present in twdr. which v alue to w rite is described later on. ho w e v er, it is important that the twint bit is set in the v alue w ritten. writing a one to twint clears the flag. start sla+w a d a t a a stop 1. applic a tion write s to twcr to initi a te tr a n s mi ss ion of start 2. twint s et. st a t us code indic a te s start condition s ent 4. twint s et. st a t us code indic a te s sla+w s ent, ack received 6. twint s et. st a t us code indic a te s d a t a s ent, ack received 3 . check twsr to s ee if start w as s ent. applic a tion lo a d s sla+w into twdr, a nd lo a d s a ppropri a te control s ign a l s into twcr, m a kin su re th a t twint i s written to one, a nd twsta i s written to zero. 5. check twsr to s ee if sla+w w as s ent a nd ack received. applic a tion lo a d s d a t a into twdr, a nd lo a d s a ppropri a te control s ign a l s into twcr, m a king su re th a t twint i s written to one 7. check twsr to s ee if d a t a w as s ent a nd ack received. applic a tion lo a d s a ppropri a te control s ign a l s to s end stop into twcr, m a king su re th a t twint i s written to one twi bus indic a te s twint s et applic a tion action twi h a rdw a re action 224 7593l?avr?09/12 at90usb64/128 the twi w ill not start any operation as long as th e twint bit in twcr is set. immedi- ately after the application has cleared twint, the twi w ill initiate transmission of the data packet. 6. when the data packet has been transmitted, the twint flag in twcr is set, and twsr is updated w ith a status code indicating that the data packet has successfully been sent. the status code w ill also reflect w hether a sla v e ackno w ledged the packet or not. 7. the application soft w are should no w examine the v alue of twsr, to make sure that the data packet w as successfully transmitted, and that the v alue of the ack bit w as as expected. if twsr indicates other w ise, the application soft w are might take some spe- cial action, like calling an error routine. assu ming that the status code is as expected, the application must w rite a specific v alue to twcr, instructing the twi hard w are to transmit a stop condition. which v alue to w rite is described later on. ho w e v er, it is important that the twint bit is set in the v alue w ritten. writing a one to twint clears the flag. the twi w ill not start any operation as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi w ill initiate transmission of the stop condition. note that twint is not set after a stop condition has been sent. e v en though this example is simple, it sho w s the principles in v ol v ed in all twi transmissions. these can be summarized as follo w s: ? when the twi has finished an operation and expects application response, the twint flag is set. the scl line is pulled lo w until twint is cleared ? when the twint flag is set, the user must update all twi registers w ith the v alue rele v ant for the next twi bus cycle. as an example, twdr must be loaded w ith the v alue to be transmitted in the next bus cycle ? after all twi register updates and other pending application soft w are tasks ha v e been completed, twcr is w ritten. when w riting twcr, the twint bit should be set. writing a one to twint clears the flag. the twi w ill then commence executing w hate v er operation w as specified by the twcr setting in the follo w ing an assembly and c implemen tation of the example is gi v en. note that the code belo w assumes that se v eral definitions ha v e been made, for example by using include-files. assembly code example c example comments 1 ldi r16, (1< 227 7593l?avr?09/12 at90usb64/128 twen must be set to enable the 2- w ire serial interface, twsta must be w ritten to one to trans- mit a start condition and twint must be w ritten to one to clear the twint flag. the twi w ill then test the 2- w ire serial bus and generate a start c ondition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hard w are, and the status code in twsr w ill be 0x08 (see table 21-3 ). in order to enter mt mode, sla+w must be transmitted. this is done by w riting sla+w to twdr. thereafter the twint bit should be cleared (by w riting it to one) to continue the transfer. this is accomplished by w riting the follo w - ing v alue to twcr: when sla+w ha v e been transmitted and an ackno w ledgement bit has been recei v ed, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x18, 0x20, or 0x38. the appropriate action to be taken for each of these status codes is detailed in table 21-3 . when sla+w has been successfully transmitted, a data packet should be transmitted. this is done by w riting the data byte to twdr. twdr must only be w ritten w hen twint is high. if not, the access w ill be discarded, and the write collision bit (twwc) w ill be set in the twcr regis- ter. after updating twdr, the twint bit should be cleared (by w riting it to one) to continue the transfer. this is accomplished by w riting the follo w ing v alue to twcr: this scheme is repeated until the last byte has been sent and the transfer is ended by generat- ing a stop condition or a repeated start condition. a stop condition is generated by w riting the follo w ing v alue to twcr: a repeated start condition is generated by w riting the follo w ing v alue to twcr: after a repeated start condition (state 0x10) the 2- w ire serial interface can access the same sla v e again, or a ne w sla v e w ithout transmitting a stop condition. repeated start enables the master to s w itch bet w een sla v es, master transmitter mode and master recei v er mode w ith- out losing control of the bus. twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x table 21-3. status codes for master transmitter mode. status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+w 0 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r 0 0 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 228 7593l?avr?09/12 at90usb64/128 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x28 data byte has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x30 data byte has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode entered a start condition will be transmitted when the bus becomes free table 21-3. status codes for master transmitter mode. (continued) 229 7593l?avr?09/12 at90usb64/128 figure 21-13. formats and states in the master transmitter mode. 21.8.2 master receiver mode in the master recei v er mode, a number of data bytes are recei v ed from a sla v e transmitter (sla v e see figure 21-14 on page 230 ). in order to enter a master mode, a start condition must be transmitted. the format of the follo w ing address packet determines w hether master transmitter or master recei v er mode is to be entered. if sla+w is transmitted, mt mode is entered, if sla+r is transmitte d, mr mode is entered. all the status codes mentioned in this section assume that the prescaler bi ts are zero or are masked to zero. s sla w a data a p $08 $18 $28 r sla w $10 ap $20 p $ 3 0 a or a $ 3 8 a other m as ter contin u e s a or a $ 3 8 other m as ter contin u e s r a $68 other m as ter contin u e s $78 $b0 to corre s ponding s t a te s in s l a ve mode mt mr s u cce ss f u ll tr a n s mi ss ion to a s l a ve receiver next tr a n s fer s t a rted with a repe a ted s t a rt condition not a cknowledge received a fter the s l a ve a ddre ss not a cknowledge received a fter a d a t a b yte ar b itr a tion lo s t in s l a ve a ddre ss or d a t a b yte ar b itr a tion lo s t a nd a ddre ss ed as s l a ve data a n from m as ter to s l a ve from s l a ve to m as ter any n u m b er of d a t a b yte s a nd their ass oci a ted a cknowledge b it s thi s n u m b er (cont a ined in twsr) corre s pond s to a defined s t a te of the two-wire seri a l b us . the pre s c a ler b it s a re zero or m as ked to zero s 230 7593l?avr?09/12 at90usb64/128 figure 21-14. data transfer in master recei v er mode. a start condition is sent by w riting the follo w ing v alue to twcr: twen must be w ritten to one to enable the 2- w ire serial interface, twsta must be w ritten to one to transmit a start condition and twint must be set to clear the twint flag. the twi w ill then test the 2- w ire serial bus and generate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hard- w are, and the status code in twsr w ill be 0x08 (see table 21-3 on page 227 ). in order to enter mr mode, sla+r must be transmitted. this is done by w riting sla+r to twdr. thereafter the twint bit should be cleared (by w riting it to one) to continue the transfer. this is accomplished by w riting the follo w ing v alue to twcr: when sla+r ha v e been transmitted and an ackno w ledgement bit has been recei v ed, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x38, 0x40, or 0x48. the appropriate action to be taken for each of these status codes is detailed in table 21-4 on page 231 . recei v ed data can be read from the twdr register w hen the twint flag is set high by hard w are. this scheme is repeated until the last byte has been recei v ed. after the last byte has been recei v ed, the mr should inform the st by sending a nack after the last recei v ed data byte. the transfer is ended by generating a stop condition or a repeated start condition. a stop condition is generated by w riting the follo w ing v alue to twcr: a repeated start condition is generated by w riting the follo w ing v alue to twcr: after a repeated start condition (state 0x10) the 2- w ire serial interface can access the same sla v e again, or a ne w sla v e w ithout transmitting a stop condition. repeated start enables the master to s w itch bet w een sla v es, master transmitter mode and master recei v er mode w ith- out losing control o v er the bus twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 master receiver device 2 slave transmitter device 3 device n sda scl ........ r1 r2 v cc 231 7593l?avr?09/12 at90usb64/128 table 21-4. status codes for master recei v er mode. status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+r 0 0 1 x sla+r will be transmitted ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w 0 0 0 0 1 1 x x sla+r will be transmitted ack or not ack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus be- comes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returne 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 232 7593l?avr?09/12 at90usb64/128 figure 21-15. formats and states in the master recei v er mode. 21.8.3 slave receiver mode in the sla v e recei v er mode, a number of data bytes are recei v ed from a master transmitter (see figure 21-16 ). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 21-16. data transfer in sla v e recei v er mode. to initiate the sla v e recei v er mode, twar and twcr mu st be initialized as follo w s: s sla r a data a $08 $40 $50 sla r $10 ap $48 a or a $ 3 8 other m as ter contin u e s $ 3 8 other m as ter contin u e s w a $68 other m as ter contin u e s $78 $b0 to corre s ponding s t a te s in s l a ve mode mr mt s u cce ss f u ll reception from a s l a ve receiver next tr a n s fer s t a rted with a repe a ted s t a rt condition not a cknowledge received a fter the s l a ve a ddre ss ar b itr a tion lo s t in s l a ve a ddre ss or d a t a b yte ar b itr a tion lo s t a nd a ddre ss ed as s l a ve data a n from m as ter to s l a ve from s l a ve to m as ter any n u m b er of d a t a b yte s a nd their ass oci a ted a cknowledge b it s thi s n u m b er (cont a ined in twsr) corre s pond s to a defined s t a te of the two-wire seri a l b us . the pre s c a ler b it s a re zero or m as ked to zero p data a $58 a r s twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address device 3 device n sda scl ........ r1 r2 v cc device 2 master transmitter device 1 slave receiver 233 7593l?avr?09/12 at90usb64/128 the upper se v en bits are the address to w hich the 2- w ire serial interface w ill respond w hen addressed by a master. if the lsb is set, the twi w ill respond to the general call address (0x00), other w ise it w ill ignore the gener al call address. twen must be w ritten to one to enable the twi. the twea bit must be w ritten to one to enable the ackno w ledgement of the de v ice?s o w n sla v e address or the general call address. twsta and twsto must be w ritten to zero. when twar and twcr ha v e been initialized, the twi w aits until it is addressed by its o w n sla v e address (or the general call address if enabled) follo w ed by the data direction bit. if the direction bit is ?0? ( w rite), the twi w ill operate in sr mode, other w ise st mode is entered. after its o w n sla v e address and the w rite bit ha v e been recei v ed, the twint flag is set and a v alid status code can be read from twsr. the status c ode is used to determine the appropriate soft- w are action. the appropriate action to be taken for each status code is detailed in table 21-5 on page 234 . the sla v e recei v er mode may also be entered if arbitration is lost w hile the twi is in the master mode (see states 0x68 and 0x78). if the twea bit is reset during a transfer, the twi w ill return a ?not ackno w ledge? (?1?) to sda after the next recei v ed data byte. this can be used to indicate that the sla v e is not able to recei v e any more bytes. while twea is zero, the twi does not ackno w ledge its o w n sla v e address. ho w e v er, the 2- w ire serial bus is still monitored and address recogn ition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the 2- w ire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the inte rface can still ackno w ledge its o w n sla v e address or the general call address by using the 2- w ire serial bus clock as a clock source. the part w ill then w ake up from sleep and the twi w ill hold the scl clock lo w during the w ake up and until the twint flag is cleared (by w riting it to one). further data reception w ill be carried out as normal, w ith the avr clocks run- ning as normal. obser v e that if the avr is set up w ith a long start-up time, the scl line may be held lo w for a long time, blocking other data transmissions. note that the 2- w ire serial interface data register ? twdr does not reflect the last byte present on the bus w hen w aking up from these sleep modes. twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 234 7593l?avr?09/12 at90usb64/128 table 21-5. status codes for sla v e recei v er mode. status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hard- ware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be re- turned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be re- turned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be re- turned data byte will be received and ack will be returned 0x78 arbitration lost in sla+r/w as master; general call address has been received; ack has been re- turned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be re- turned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be re- turned data byte will be received and ack will be returned 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0x90 previously addressed with gener- al call; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be re- turned data byte will be received and ack will be returned 0x98 previously addressed with gener- al call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xa0 a stop condition or repeated start condition has been re- ceived while still addressed as slave no action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 235 7593l?avr?09/12 at90usb64/128 figure 21-17. formats and states in the sla v e recei v er mode. 21.8.4 slave transmitter mode in the sla v e transmitter mode, a number of data bytes are transmitted to a master recei v er (see figure 21-18 ). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 21-18. data transfer in sla v e transmitter mode. s sla w a data a $60 $80 $88 a $68 reception of the own s l a ve a ddre ss a nd one or more d a t a b yte s . all a re a cknowledged l as t d a t a b yte received i s not a cknowledged ar b itr a tion lo s t as m as ter a nd a ddre ss ed as s l a ve reception of the gener a l c a ll a ddre ss a nd one or more d a t a b yte s l as t d a t a b yte received i s not a cknowledged n from m as ter to s l a ve from s l a ve to m as ter any n u m b er of d a t a b yte s a nd their ass oci a ted a cknowledge b it s thi s n u m b er (cont a ined in twsr) corre s pond s to a defined s t a te of the two-wire seri a l b us . the pre s c a ler b it s a re zero or m as ked to zero p or s data a $80 $a0 p or s a a data a $70 $90 $98 a $78 p or s data a $90 $a0 p or s a gener a l c a ll ar b itr a tion lo s t as m as ter a nd a ddre ss ed as s l a ve b y gener a l c a ll data a device 3 device n sda scl ........ r1 r2 v cc device 2 master receiver device 1 slave transmitter 236 7593l?avr?09/12 at90usb64/128 to initiate the sla v e transmitter mode, twar and twcr must be initialized as follo w s: the upper se v en bits are the address to w hich the 2- w ire serial interface w ill respond w hen addressed by a master. if the lsb is set, the twi w ill respond to the general call address (0x00), other w ise it w ill ignore the gener al call address. twen must be w ritten to one to enable the twi. the twea bit must be w ritten to one to enable the ackno w ledgement of the de v ice?s o w n sla v e address or the general call address. twsta and twsto must be w ritten to zero. when twar and twcr ha v e been initialized, the twi w aits until it is addressed by its o w n sla v e address (or the general call address if enabled) follo w ed by the data direction bit. if the direction bit is ?1? (read), the twi w ill operate in st mode, other w ise sr mode is entered. after its o w n sla v e address and the w rite bit ha v e been recei v ed, the twint flag is set and a v alid status code can be read from twsr. the status c ode is used to determine the appropriate soft- w are action. the appropriate action to be taken for each status code is detailed in table 21-6 on page 237 . the sla v e transmitter mode may also be entered if arbitration is lost w hile the twi is in the master mode (see state 0xb0). if the twea bit is w ritten to zero during a transfer, the twi w ill transmit the last byte of the trans- fer. state 0xc0 or state 0xc8 w ill be entered, depending on w hether the master recei v er transmits a nack or ack after the final byte. the twi is s w itched to the not addressed sla v e mode, and w ill ignore the master if it continues the transfer. thus the master recei v er recei v es all ?1? as serial data. state 0xc8 is entered if the master demands additional data bytes (by transmitting ack), e v en though the sla v e has transmitted the last byte (twea zero and expect- ing nack from the master). while twea is zero, the twi does not respond to its o w n sla v e address. ho w e v er, the 2- w ire serial bus is still monitored an d address recognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the 2- w ire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the inte rface can still ackno w ledge its o w n sla v e address or the general call address by using the 2- w ire serial bus clock as a clock source. the part w ill then w ake up from sleep and the twi w ill hold the scl clock w ill lo w during the w ake up and until the twint flag is cleared (by w riting it to one). further data transmission w ill be carried out as normal, w ith the avr clocks running as normal. obser v e that if the avr is set up w ith a long start-up time, the scl line may be held lo w for a long time, blocking other data transmissions. note that the 2- w ire serial interface data register ? twdr does not reflect the last byte present on the bus w hen w aking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 237 7593l?avr?09/12 at90usb64/128 table 21-6. status codes for sla v e transmitter mode. status code (twsr) pr- escaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb0 arbitration lost in sla+r/w as master; own sla+r has been re- ceived; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xb8 data byte in twdr has been transmitted; ack has been re- ceived load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be re- ceived 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus be- comes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus be- comes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus be- comes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus be- comes free 238 7593l?avr?09/12 at90usb64/128 figure 21-19. formats and states in the sla v e transmitter mode. 21.8.5 miscellaneous states there are t w o status codes that do not correspond to a defined twi state, see table 21-7 . status 0xf8 indicates that no rele v ant information is a v ailable because the twint flag is not set. this occurs bet w een other states, and w hen the twi is not in v ol v ed in a serial transfer. status 0x00 indicates that a bus error has occurred during a 2- w ire serial bus transfer. a bus error occurs w hen a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an ackno w ledge bit. when a bus error occurs, twint is set. to reco v er from a bus error, the twsto flag must set and twint must be cleared by w riting a logic one to it. this causes the twi to enter the not addressed sla v e mode and to clear the twsto flag (no other bits in twcr are affected). the sda and scl lines are released, and no stop condition is transmitted. 21.8.6 combining several twi modes in some cases, se v eral twi modes must be combined in order to complete the desired action. consider for example reading data from a seri al eeprom. typically, such a transfer in v ol v es the follo w ing steps: 1. the transfer must be initiated. 2. the eeprom must be instructed w hat location should be read. 3. the reading must be performed. 4. the transfer must be finished. s sla r a data a $a8 $b8 a $b0 reception of the own s l a ve a ddre ss a nd one or more d a t a b yte s l as t d a t a b yte tr a n s mitted. switched to not a ddre ss ed s l a ve (twea = '0') ar b itr a tion lo s t as m as ter a nd a ddre ss ed as s l a ve n from m as ter to s l a ve from s l a ve to m as ter any n u m b er of d a t a b yte s a nd their ass oci a ted a cknowledge b it s thi s n u m b er (cont a ined in twsr) corre s pond s to a defined s t a te of the two-wire seri a l b us . the pre s c a ler b it s a re zero or m as ked to zero p or s data $c0 data a a $c8 p or s all 1' s a table 21-7. miscellaneous states. status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xf8 no relevant state information available; twint = ?0? no twdr action no twcr action wait or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal hardware is affected, no stop con- dition is sent on the bus. in all cases, the bus is re- leased and twsto is cleared. 239 7593l?avr?09/12 at90usb64/128 note that data is transmitted both from master to sla v e and v ice v ersa. the master must instruct the sla v e w hat location it w ants to read, requiring the use of the mt mode. subsequently, data must be read from the sla v e, implying the use of the mr mode. thus, the transfer direction must be changed. the master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. if this principle is v iolated in a multimaster sys- tem, another master can alter the data pointer in the eeprom bet w een steps 2 and 3, and the master w ill read the w rong data location. such a change in transfer direction is accomplished by transmitting a repeated start bet w een the transmission of the address byte and reception of the data. after a repeated start, the master keeps o w nership of the bus. the follo w ing figure sho w s the flo w in this transfer. figure 21-20. combining se v eral twi modes to access a serial eeprom. 21.9 multi-master system s and arbitration if multiple masters are connected to the same bus, transmissions may be initiated simultane- ously by one or more of them. the twi standar d ensures that such situations are handled in such a w ay that one of the masters w ill be allo w ed to proceed w ith the transfer, and that no data w ill be lost in the process. an example of an arbitration situation is depicted belo w , w here t w o masters are trying to transmit data to a sla v e recei v er. figure 21-21. an arbitration example. se v eral different scenarios may arise during arbitration, as described belo w : ?t w o or more masters are performing identical communication w ith the same sla v e. in this case, neither the sla v e nor any of the masters w ill kno w about the bus contention ?t w o or more masters are accessing the same sla v e w ith different data or direction bit. in this case, arbitration w ill occur, either in the read/write bi t or in the data bits. the masters trying to output a one on sda w hile another master outputs a zero w ill lose the arbitration. losing masters w ill s w itch to not addressed sla v e mode or w ait until the bus is free and transmit a ne w start condition, depending on application soft w are action m as ter tr a n s mitter m as ter receiver s = start r s = repeated start p = stop tr a n s mitted from m as ter to s l a ve tr a n s mitted from s l a ve to m as ter s sla+w a address a r s sla+r a data a p device 1 master transmitter device 2 master transmitter device 3 slave receiver device n sda scl ........ r1 r2 v cc 240 7593l?avr?09/12 at90usb64/128 ?t w o or more masters are accessing different sla v es. in this case, arbitration w ill occur in the sla bits. masters trying to output a one on sda w hile another master outputs a zero w ill lose the arbitration. masters losing arbitration in sla w ill s w itch to sla v e mode to check if they are being addressed by the w inning master. if addressed, they w ill s w itch to sr or st mode, depending on the v alue of the read/write bit. if they are not being addressed, they w ill s w itch to not addressed sla v e mode or w ait until the bus is free and transmit a ne w start condition, depending on application soft w are action this is summarized in figure 21-22 . possible status v alues are gi v en in circles. figure 21-22. possible status codes caused by arbitration. own addre ss / gener a l c a ll received ar b itr a tion lo s t in sla twi bus will b e rele as ed a nd not a ddre ss ed s l a ve mode will b e entered a start condition will b e tr a n s mitted when the bus b ecome s free no ar b itr a tion lo s t in d a t a direction ye s write d a t a b yte will b e received a nd not ack will b e ret u rned d a t a b yte will b e received a nd ack will b e ret u rned l as t d a t a b yte will b e tr a n s mitted a nd not ack s ho u ld b e received d a t a b yte will b e tr a n s mitted a nd ack s ho u ld b e received re a d b0 68/78 3 8 sla start d a t a stop 241 7593l?avr?09/12 at90usb64/128 22. usb controller 22.1 features ? support full-speed and low-speed ? support ping-pong mode (dual bank) ? 832 bytes of dpram: ? one endpoint 64 bytes maximu m (default cont rol endpoint) ? one endpoint of 256 bytes maximum (one or two banks) ? five endpoints of 64 bytes maximum (one or two banks) 22.2 block diagram the usb controller pro v ides the hard w are to interface a usb link to a data flo w stored in a dou- ble port memory (dpram). the usb controller requires a 48mhz 0.25% reference clock (for full-speed operation), w hich is the output of an internal pll. the pll generates the internal high frequency (48mhz) clock for usb interface, the pll input is generated from an external lo w er frequency (the crystal oscil- lator or external clock input pin from xtal1; to satisfy the usb frequency accuracy and jitter, only this clock source allo w s proper functionnality of the usb controller). the 48mhz clock is used to generate a 12mhz full-speed (or 1.5mhz lo w -speed) bit clock from the recei v ed usb differential data and to transmit data according to full or lo w speed usb de v ice tolerance. clock reco v ery is done by a digital phase locked loop (dpll) block, w hich is compliant w ith the jitter specific ation of the usb bus. to comply w ith the usb electrical specification, usb pads (d+ or d-) should be po w ered w ithin the 3.0 to 3.6v range. as atmel at90usb64/128 can be po w ered up to 5.5v, an internal regula- tor pro v ides the usb pads po w er supply. figure 22-1. usb controller block diagram o v er v ie w . cpu usb reg u l a tor usb interf a ce pll 24x clk 2mhz clk 48mhz pll clock pre s c a ler on-chip usb dpram dpll clock recovery ucap d- d+ vbu s uid uvcc avcc xtal1 242 7593l?avr?09/12 at90usb64/128 22.3 typical application implementation depending on the usb operating mode (de v ice only, reduced host or otg mode) and on the target application po w er supply, the atmel at90usb64/128 require different hard w are typical implementations. figure 22-2. operating modes v ersus frequency and po w er-supply. 22.3.1 device mode 22.3.1.1 bus powered device figure 22-3. typical bus po w ered application w ith 5v i/o. vcc (v) vcc min 0 3 .0 3 .4 5.5 u s b not operational u s b compliant, without internal re g ulator u s b compliant, with internal re g ulator 4.5 2.7 maximum operatin g frequency [mhz] 8 mhz 16mhz 2mhz 3 .6 1f udp udm vbus uvss uid ucap d- d+ vbu s uid ugnd uvcc avcc vcc xtal1 xtal2 gnd gnd r s = 22 r s = 22 243 7593l?avr?09/12 at90usb64/128 figure 22-4. typical bus po w ered application w ith 3v i/o. 22.3.1.2 self powered device figure 22-5. typical self po w ered application w ith 3.4v to 5.5v i/o. 1f uv ss external 3 v re g ulator udp udm vbus uvss uid ucap d- d+ vbu s uid ugnd uvcc avcc vcc xtal1 xtal2 gnd gnd r s = 22 r s = 22 1f external 3 .4v - 5.5v power s upply udp udm vbus uvss uid ucap d- d+ vbu s uid ugnd uvcc avcc vcc xtal1 xtal2 gnd gnd r s = 22 r s = 22 244 7593l?avr?09/12 at90usb64/128 figure 22-6. typical self po w ered application w ith 3.0v to 3.6 i/o. 22.3.2 host / otg mode figure 22-7. host/otg application w ith 3.0v to 3.6 i/o. 1f external 3 .0v - 3 .6v power s upply udp udm vbus uvss uid ucap d- d+ vbu s uid ugnd uvcc avcc vcc xtal1 xtal2 gnd gnd r s = 22 r s = 22 udm udp vbus uvss uid d- d+ vbu s uid ugnd 1f external 3 .0v - 3 .4v power s upply ucap uvcc avcc vcc xtal1 xtal2 gnd gnd uvcon 5v dc/dc g enerator 5v r s = 22 r s = 22 245 7593l?avr?09/12 at90usb64/128 figure 22-8. host/otg application w ith 5v i/o. 22.3.3 design guidelines ? serial resistors on usb data lines must ha v e 22 v alue (5%) ? traces from the input usb receptable (or from the cable connection in the case of a tethered de v ice) to the usb microcontroller pads should be as short as possible, and follo w differential traces routing rules (same length, as near as possible, a v oid v ias accumulation) ? voltage transient / esd suppressors may also be used to pre v ent usb pads to be damaged by external disturbances ?u cap capacitor should be 1f (10%) for correct operation ? a 10f capacitor is highly recommended on vbus line udp udm vbus uvss uid d- d+ vbu s uid ugnd 1f external 5.0v power s upply ucap uvcc avcc vcc xtal1 xtal2 gnd gnd uvcon 5v r s = 22 r s = 22 246 7593l?avr?09/12 at90usb64/128 22.4 general operating modes 22.4.1 introduction after a hard w are reset, the usb controller is disabled. when enabled, the usb controller has to run the de v ice controller or the host controller. this is performed using the usb id detection. ? if the id pin is not connected to ground, the usb id bit is set by hard w are (internal pull up on the uid pad) and the usb de v ice controller is selected ? the id bit is cleared by hard w are w hen a lo w le v el has been detected on the id pin. the de v ice controller is then disabled and the host controller enabled the soft w are any w ay has to select the mode (host, de v ice) in order to access to the de v ice controller registers or to the host controller registers, w hich are multiplexed. for example, e v en if the usb controller has detected a de v ice mode (pin id high), the soft w are shall select the de v ice mode (bit host cleared), other w ise it w ill access to the host registers. this is also true for the host mode. note: for the atmel at90usb646/1286 products the host mode is not included in the usb controller, and the id pin is not used and should be configured and used as a general i/o. 22.4.2 power-on and reset the next diagram explains the usb controller main states on po w er-on: figure 22-9. usb controller states after reset. usb controller state after an hard w are reset is ?reset?. in this state: ? usbe is not set ? the usb controller clock is stopped in order to minimize the po w er consumption (frzclk=1) ? the usb controller is disabled ? the usb pad is in the suspend mode ? the host and de v ice usb controllers internal states are reset after setting usbe, the u sb controller enters in the host or in the de v ice state (according to the usb id pin). the selected controller is ?idle?. the usb controller can at any time be ?stopped? by clearing usbe. in fact, clearing usbe acts as an hard w are reset. device r eset usbe=0 < any other state> usbe=1 id=1 c lock stopped frzclk=1 macro off usbe=0 usbe=0 host usbe=0 hw reset usbe=1 id=0 at 90usb647/1287 only at 90usb646/ 1286 forced mode 247 7593l?avr?09/12 at90usb64/128 22.4.3 interrupts t w o interrupts v ectors are assigned to usb interface. figure 22-10. usb interrupt system. see section 23.17, page 272 and section 24.15, page 291 for more details on the host and de v ice interrupts. usb general & otg interrupt usb device interrupt usb host interrupt usb general interrupt vector endpoint interrupt pipe interrupt usb endpoint/pipe interrupt vector 248 7593l?avr?09/12 at90usb64/128 figure 22-11. usb general interrupt v ector sources. idte usbcon.1 idti usbint.1 vbusti usbint.0 vbuste usbcon.0 stoi otgint.5 stoe otgien.5 hnperri otgint.4 hnperre otgien.4 roleexi otgint.3 roleexe otgien.3 bcerri otgint.2 bcerre otgien.2 vberri otgint.1 vberre otgien.1 srpi otgint.0 srpe otgien.0 usb general interrupt vector uprsmi udint.6 uprsme udien.6 eorsmi udint.5 eorsme udien.5 wakeupi udint.4 wakeupe udien.4 eorsti udint.3 eorste udien.3 sofi udint.2 sofe udien.2 suspi udint.0 suspe udien.0 hwupe uhien.6 hwupi uhint.6 hsofi uhint.5 hsofe uhien.5 rxrsmi uhint.4 rxrsme uhien.4 rsmedi uhint.3 rsmede uhien.3 rsti uhint.2 rste uhien.2 ddisci uhint.1 ddisce uhien.1 dconni uhint.0 dconne uhien.0 usb device interrupt usb host interrupt usb general interrupt vector asynchronous interrupt source (allows the cpu to wake up from power down mode) 249 7593l?avr?09/12 at90usb64/128 figure 22-12. usb endpoint/pipe interrupt v ector sources. flerre ueienx.7 overfi uestax.6 underfi uestax.5 nakini ueintx.6 nakine ueienx.6 nakouti ueintx.4 txstpe ueienx.4 rxstpi ueintx.3 rxstpe ueienx.3 rxouti ueintx.2 rxoute ueienx.2 stalledi ueintx.1 stallede ueienx.1 epint ueint.x endpoint 0 endpoint 1 endpoint 2 endpoint 3 endpoint 4 endpoint 5 endpoint interrupt txini ueintx.0 txine ueienx.0 flerre upien.7 underfi upstax.5 overfi upstax.6 nakedi upintx.6 nakede upien.6 perri upintx.4 perre upien.4 txstpi upintx.3 txstpe upien.3 txouti upintx.2 txoute upien.2 rxstalli upintx.1 rxstalle upien.1 rxini upintx.0 rxine upien.0 flerre upien.x pipe 0 pipe 1 pipe 2 pipe 3 pipe 4 pipe 5 pipe interrupt usb endpoint/pipe interrupt vector endpoint 6 pipe 6 250 7593l?avr?09/12 at90usb64/128 figure 22-13. usb general and otg controller interrupt system. there are t w o kinds of interrupts: processing (that is, their generation are part of the normal pro- cessing) and exception (errors). processing interrupts are generated w hen such e v ents occur: ? usb id pad change detection (insert, remo v e)( idti) ? vbus plug-in detection (insert, remo v e) ( vbusti ) ? srp detected( srpi ) ? role exchanged( roleexi ) exception interrupts are generated w ith the follo w ing e v ents: ? drop on vbus detected( vberri ) ? error during the b-connection( bcerri ) ? hnp error( hnperri ) ? time-out detected during suspend mode( stoii ) 22.5 power modes 22.5.1 idle mode in this mode, the cpu core is halted (cpu clock stopped). the idle mode is taken w ether the usb controller is runnin g or not. the cpu ? w akes up? on any usb interrupts. 22.5.2 power down in this mode, the oscillator is stopped and halts all the clocks (cpu and peripherals). the usb controller ? w akes up? w hen: ? the wakeupi interrupt is triggered in the peripheral mode (host cleared) idte usbcon.1 idti usbint.1 vbusti usbint.0 vbuste usbcon.0 stoi otgint.5 stoe otgien.5 hnperri otgint.4 hnperre otgien.4 roleexi otgint.3 roleexe otgien.3 bcerri otgint.2 bcerre otgien.2 vberri otgint.1 vberre otgien.1 srpi otgint.0 srpe otgien.0 usb general & otg interrupt vector asynchronous interrupt source (allows the cpu to wake up from power down mode 251 7593l?avr?09/12 at90usb64/128 ? the hwupi interrupt is triggered in the host mode (host set) ? the idti interrupt is triggered ? the vbusti interrupt is triggered 22.5.3 freeze clock the firm w are has the ability to reduce the po w er consumption by setting the frzclk bit, w hich freeze the clock of usb controller. when frzclk is set, it is still possible to access to the fol- lo w ing registers: ? usbcon, usbsta, usbint ? udcon (detach, ...) ?udint ?udien ?uhcon ?uhint ?uhien moreo v er, w hen frzclk is set, only the follo w ing interrupts ma y be triggered: ? wakeupi ?idti ?vbusti ?hwupi 22.6 speed control 22.6.1 device mode when the usb interface is configured in de v ice mode, the speed selection (full speed or lo w speed) depends on the udp/udm pull-up. th e lsm bit in udcon register allo w s to select an internal pull up on udm (lo w speed mode) or udp (full speed mode) data lines. figure 22-14. de v ice mode speed selection. r pu detach udcon.0 udp udm r pu lsm udcon.2 ucap usb regulator 252 7593l?avr?09/12 at90usb64/128 22.6.2 host mode when the usb interface is configured in host mode, internal pull do w n resistors are acti v ated on both udp udm lines and the interface detects the type of connected de v ice. 22.7 memory management the controller does only support the follo w ing memory allocation management. the reser v ation of a pipe or an endpoint can only be made in the increasing order (pipe/end- point 0 to the last pipe/endpoint). the firm w are shall thus configure them in the same order. the reser v ation of a pipe or an endpoint ?k i ? is done w hen its alloc bit is set. then, the hard- w are allocates the memory and inserts it bet w een the pipe/endpoints ?k i-1 ? and ?k i+1 ?. the ?k i+1 ? pipe/endpoint memory ?slides? up and its data is lost. note that the ?k i+2 ? and upper pipe/end- point memory does not slide. clearing a pipe enable (pen) or an endpoint enable (epen) does no t clear either its alloc bit, or its configuration (epsi ze/psize, epbk/pbk). to free its memory, the firm w are should clear alloc. then, the ?k i+1 ? pipe/endpoint memory automatically ?slides? do w n. note that the ?k i+2 ? and upper pipe/endpoint memory does not slide. the follo w ing figure illustrates the allocation and reorganization of the usb memory in a typical example: table 22-1. allocation and reorganization usb memory flo w . ? first, pipe/endpoint 0 to pipe/endpoint 5 are configured, in the gro w ing order. the memory of each is reser v ed in the dpram ? then, the pipe/endpoint 3 is disabled (epen=0), but its memory reser v ation is internally kept by the controller ? its alloc bit is cleared: the pipe/endpoint 4 ?slides? do w n, but the pipe/endpoint 5 does not ?slide? ? finally, if the firm w are chooses to reconfigure the pipe/endpoint 3, w ith a bigger size. the controller reser v ed the memory after the endpoint 2 memory and automatically ?slide? the pipe/endpoint 4. the pipe/endpoint 5 does not mo v e and a memory conflict appear, in that free memory 0 1 2 3 4 5 epen=1 alloc=1 free memory 0 1 2 4 5 epen=0 (alloc=1) free memory 0 1 2 4 5 pipe/endpoints activation pipe/endpoint disable free its memory (alloc=0) free memory 0 1 2 3 (bigger size) 5 pipe/endpoint activatation lost memory 4 conflict 253 7593l?avr?09/12 at90usb64/128 both pipe/endpoint 4 and 5 use a common area. the data of those endpoints are potentially lost note that: ? the data of pipe/endpoint 0 are ne v er lost w hate v er the acti v ation or deacti v ation of the higher pipe/endpoint. its data is lost if it is deacti v ated ? deacti v ate and reacti v ate the same pipe/endpoint w ith the same parameters does not lead to a ?slide? of the higher endpoints. for those endpoints, the data are preser v ed ? cfgok is set by hard w are e v en in the case w here there is a ?conflict? in the memory allocation 22.8 pad suspend the next figures illustrates the pad beha v iour: ? in the ?idle? mode, the pad is put in lo w po w er consumption mode ? in the ?acti v e? mode, the pad is w orking figure 22-15. pad beha v iour. the suspi flag indicated that a suspend state has been detected on the usb bus. this flag automatically put the usb pad in idle. the detection of a non-idle e v ent sets the wakeupi flag and w akes-up the usb pad. moreo v er, the pad can also be put in the ?idle? mode if the detach bit is set. it come back in the acti v e mode w hen the detach bit is cleared. idle mode active mode usbe=1 & detach=0 & suspend usbe=0 | detach=1 | suspend suspi suspend detected = usb pad power down clear suspend by software resume = usb pad wake-up clear resume by software wakeupi pad status active power down active 254 7593l?avr?09/12 at90usb64/128 22.9 otg timers customizing it is possible to refine some otg timers thanks to the otgtcon register that contains the page bits to select the timer and the value bits to adjust the v alue. user should refer to lastest releases of the otg specification to select compliant timings. ? page=00b: awaitvrise time-out. [otg]. in host mode, once vbusreq has been set to ?1?, if no vbus is detected on vbus pin after this awaitvrise delay then the vberri error flag is set. ? value=00btime-out is set to 20ms ? value=01btime-out is set to 50ms ? value=10btime-out is set to 70ms ? value=11btime-out is set to 100ms ? page=01b: vbbuspulsing . [otg]. in de v ice mode, this delay corresponds to the pulse duration on vbus during a srp. ? value=00btime-out is set to 15ms ? value=01btime-out is set to 23ms ? value=10btime-out is set to 31ms ? value=11btime-out is set to 40ms ? page=10b: pdtmoutcnt . [otg]. in de v ice mode, w hen a srp has been requested to be sent by the firm w are, this delay is w aited by the hard w are after vbus has gone belo w the ?session_ v alid? threshold v oltage and before initiating the first pulse. this delay should be considered as an approximation of usb lines discharge (pull-do w n resistors v s. line capacitance) in order to w ait that vbus has gone belo w the ?b_session_end? threshold v oltae, as defined in the otg specification. ? value=00btime-out is set to 93ms ? value=01btime-out is set to 105ms ? value=10btime-out is set to 118ms ? value=11btime-out is set to 131ms ? page=11b: srpdettmout . [otg]. in host mode, this delay is the minimum pulse duration required to detect and accept a v alid srp from a de v ice. ? value=00btime-out is set to 1s ? value=01btime-out is set to 100s ? value=10btime-out is set to 1ms ? value=11btime-out is set to 11ms 255 7593l?avr?09/12 at90usb64/128 22.10 plug-in detection the usb connection is detected by the vbus pad, thanks to the follo w ing architecture: figure 22-16. plug-in detection input block diagram. the control logic of the vbus pad outputs a signal regarding the vbus v oltage le v el: ? the ?session_ v alid? signal is acti v e high w hen the v oltage on the vbus pad is higher or equal to 1.4v. if lo w er than 1.4v, the signal is not acti v e ?the ?vbus_ v alid? signal is acti v e high w hen the v oltage on the vbus pad is higher or equal to 4.4v. if lo w er than 4.4v, the signal is not acti v e ? the vbus status bit is set w hen vbus is greater than ?vbus_ v alid?. the vbus status bit is cleared w hen vbus falls belo w ?session_ v alid? (hysteresis beha v ior) ? the vbusti flag is set each time the vbus bit state changes 22.10.1 peripheral mode the usb peripheral cannot attach to the bus w hile vbus bit is not set. 22.10.2 host mode the host must use the uvcon pin to dri v e an external po w er s w itch or regulator that po w ers the vbus line. the uvcon pin is automatically asserted and set high by hard w are w hen uvcone and vbusreq bits are set by firm w are. if a de v ice connects (pull-up on dp or dm) w ithin 300ms of vbus deli v ery, the dconni flag w ill rise. but, once vbusreq bit has been set, if no peripheral connection is detected w ithin 300ms, the bcerri flag (and interrupt) w ill rise and vbus deli v ery w ill be stopped (uvcon cleared). if that beha v ior represents a limitation for th e host application, the follo w ing w ork-around may be used : 1. uvcone and vbusreq must be cleared. 2. vbushwc must be set (to disable hard w are control of uvcon pin). 3. porte,7 pin (alternate function of uvcon pin) must be set by firm w are. 4. a de v ice connection w ill be detected thanks to the srpi flag (that may usually be used to detect a dp/dm pulse sent by an otg b-de v ice that requests a ne w session). vbusti usbint.0 vbus vbus usbsta.0 vss vdd pad logic logic session_ v alid r pu r pu vbus_pulsing vbus_discharge vbus_ v alid 256 7593l?avr?09/12 at90usb64/128 22.11 id detection the id pin transition is detected thanks to the follo w ing architecture: figure 22-17. id detection input block diagram. the id pin can be used to detect the usb mode (peripheral or host) or soft w are selected. this allo w s the uid pin to be used has general purpose i/o e v en w hen usb interface is enable. when the uid pin is selected, by default, (no a- plug or b-plug), the macro is in the peripheral mode (internal pull-up). the idti interrupt is triggered w hen a a-plug (host) is plugged or unplugged. the interrupt is not triggered w hen a b-plug (periph) is plugged or unplugged. id detection is independent of usb global interface enable. 22.12 registers description 22.12.1 usb general registers ? 7 ? uimod: usb mode bit this bit has no effect w hen the uide bit is set (external uid pin acti v ated). set to enable the usb de v ice mode. clear to enable the usb host mode ? 6 ? uide: uid pin enable set to enable the usb mode selection (peripheral/host) through the uid pin. clear to enable the usb mode selection (peripheral/host) w ith uimod bit register. uide should be modified only w hen the usb interface is disabled (usbe bit cleared). ? 5 ? reserved the v alue read from this bit is al w ays 0. do not set this bit. ? 4 ? uvcone: uvcon pin enable set to enable the uvcon pin control. clear to disable the uvcon pin control. this bit should be set only w hen the usb interface is enable. r pu uimod uhwcon.7 uid id usbsta.1 internal pull up vdd uide uhwcon.6 1 0 bit 7 6 5 4 321 0 uimod uide uvcone uvrege uhwcon read/ w rite r/w r/w r r/w r r r r/w initial v alue 1 0 0 0 0 0 0 0 257 7593l?avr?09/12 at90usb64/128 ? 3-1 ? reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 0 ? uvrege: usb pad regulator enable set to enable the usb pad regulator. clear to disable the usb pad regulator. ? 7 ? usbe: usb macro enable bit set to enable the usb controller. clear to disabl e and reset the usb controller, to disable the usb transcei v er and to disable the usb controller clock inputs. ? 6 ? host: host bit set to enable the host mode. clear to enable the de v ice mode. ? 5 ? frzclk: freeze usb clock bit set to disable the clock inputs (t he ?resume detection? is still acti v e). this reduces the po w er consumption. clear to enable the clock inputs. ? 4 ? otgpade: otg pad enable set to enable the otg pad. clear to disable t he otg pad. the otg pad is actually the vbus pad. note that this bit can be set/cleared e v en if usbe=0. that allo w s the vbus detection e v en if the usb macro is disabled. this pad must be enabled in both host and de v ice modes in order to allo w usb operation (attaching, transmitting...). ? 3-2 ? reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 1 ? idte: id transition interrupt enable bit set this bit to enable the id transition interrupt generation. clear this bit to disable the id transi- tion interrupt generation. ? 0 ? vbuste: vbus transition interrupt enable bit set this bit to enable the vbus transition interrupt generation. clear this bit to disable the vbus transition interrupt generation. ? 7-4 - reserved the v alue read from these bits is al w ays 0. do not set these bits. bit 7 6 5 4 321 0 usbe host frzclk otgpade - - idte vbuste usbcon read/ w rite r/w r/w r/w r/w r r r/w r/w initial v alue 0 0 1 0 0 0 0 0 bit 76543 2 1 0 ----speed idvbususbsta read/ w riterrrrrrrr initial v alue00001 0 1 0 258 7593l?avr?09/12 at90usb64/128 ? 3 ? speed: speed status flag this should be read only w hen the usb controller operates in host mode, in de v ice mode the v alue read from this bit is undeterminated. set by hard w are w hen the controller is in full -speed mode. cleared by hard w are w hen the controller is in low-speed mode. ? 2 ? reserved the v alue read from this bit is al w ays 0. do not set this bit. ? 1 ? id: iud pin flag the v alue read from this bit indicates the state of the uid pin. ? 0 ? vbus: vbus flag the v alue read from this bit indicates the state of the vbus pin. this bit can be used in de v ice mode to monitor the usb bus connection state of the application. see section 22.10, page 255 for more details. 7-2 - reserved the v alue read from these bits is al w ays 0. do not set these bits. 1 ? idti: d transition interrupt flag set by hard w are w hen a transition (high to lo w , lo w to high) has been detected on the uid pin. shall be cleared by soft w are. ? 0 ? vbusti: ivbus transition interrupt flag set by hard w are w hen a transition (high to lo w , lo w to high) has been detected on the vbus pad. shall be cleared by soft w are. ? 7-6 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 5 ? hnpreq: hnp request bit set to initiate the hnp w hen the controller is in the de v ice mode (b). set to accept the hnp w hen the controller is in the host mode (a). clear other w ise. bit 76543210 ------idtivbustiusbint read/ w riterrrrrrr/wr/w initial v alue00000000 bit 7 6 5 4 3 2 1 0 - - hnpreq srpreq srpsel vbushwc vbusreq vbusrqc otgcon read/ w rite r r r/w r/w r/w r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 259 7593l?avr?09/12 at90usb64/128 ? 4 ? srpreq: srp request bit set to initiate the srp w hen the controller is in de v ice mode. cleared by hard w are w hen the controller is initiating a srp. ? 3 ? srpsel: srp selection bit set to choose vbus pulsing as srp method. clear to choose data line pulsing as srp method. ? 2 ? vbushwc: vbus hardware control bit set to disable the hard w are control o v er the uvcon pin. clear to enable the hard w are control o v er the uvcon pin. see for more details ? 1 ? vbusreq: vbus request bit set to assert the uvcon pin in order to enable the vbus po w er supply generation. this bit shall be used w hen the controller is in the host mode. cleared by hard w are w hen vbusrqc is set. ? 0 ? vbusrqc: vbus request clear bit set to deassert the uvcon pin in order to enable the vbus po w er supply generation. this bit shall be used w hen the controller is in the host mode. cleared by hard w are immediately after the set. ? 7 ? reserved this bit is reser v ed and al w ays set. ? 6-5 ? page: timer page access bit set/clear to access a special timer register. see section 22.9, page 254 for more details. ? 4-3 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 1-0 ? value: value bit set to initialize the ne w v alue of the timer. see section 22.9, page 254 for more details. bit 7 6 5 4 3 2 1 0 - page - - - value otgtcon read/ w rite r r/w r/w r r r/w r/w r/w initial v alue 1 0 0 0 0 0 0 0 260 7593l?avr?09/12 at90usb64/128 ? 7-6 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 5 ? stoe: suspend time-out error interrupt enable bit set to enable the stoi interrupt. clear to disable the stoi interrupt. ? 4 ? hnperre: hnp error interrupt enable bit set to enable the hnperri interrupt. clear to disa ble the hnperri interrupt. ? 3 ? roleexe: role exchange interrupt enable bit set to enable the roleexi interrupt. cle ar to disable the roleexi interrupt. ? 2 ? bcerre: b-connection error interrupt enable bit set to enable the bcerri interrupt. clear to disable the bcerri interrupt. ? 1 ? vberre: vbus error interrupt enable bit set to enable the vberri interrupt. cle ar to disable the vberri interrupt. ? 0 ? srpe: srp interrupt enable bit set to enable the srpi interrupt. clear to disable the srpi interrupt. ? 7-6 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 5 ? stoi: suspend time-out error interrupt flag set by hard w are w hen a time-out error (more than 150ms) has been detected after a suspend. shall be cleared by soft w are. ? 4 ? hnperri: hnp error interrupt flag set by hard w are w hen an error has been detected during the protocol. shall be cleared by soft w are. ? 3 ? roleexi: role exchange interrupt flag set by hard w are w hen the usb controller has successfully s w apped its mode, due to an hnp negotiation: host to de v ice or de v ice to host. ho w e v er the mode selection bit (host/de v ice) is unchanged and must be changed by firm w are in order to reach the correct ram locations and e v ents bits. shall be cleared by soft w are. bit 7 6 5 4 3 2 1 0 - - stoe hnperre roleexe bcerre vberre srpe otgien read/ w rite r r r/w r/w r/w r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 bit 7654 3 210 - - stoi hnperri roleexi bcerri vberri srpi otgint read/ w rite r r r/w r/w r/w r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 261 7593l?avr?09/12 at90usb64/128 ? 2 ? bcerri: b-connection error interrupt flag set by hard w are w hen an error occur during the b-connecti on (that is, if peripheral has not con- nected after 300ms of vbus deli v ery request). shall be cleared by soft w are. ? 1 ? vberri: v-bus error interrupt flag set by hard w are w hen a drop on vbus has been detected. shall be cleared by soft w are. ? 0 ? srpi: srp interrupt flag set by hard w are w hen a srp has been detected. shall be used in the host mode only. shall be cleared by soft w are. 22.13 usb software operating modes depending on the usb operating mode, the soft w are should perform some the follo w ing operations: power on the usb interface ?po w er-on usb pads regulator ? configure pll interface ? enable pll and w ait pll lock ? enable usb interface ? configure usb interface (usb speed, endpoints configuration...) ? wait for usb vbus information connection ? attach usb de v ice power off the usb interface ? detach usb interface ? disable usb interface ? disable pll ? disable usb pad regulator suspending the usb interface ? clear suspend bit ? freeze usb clock ? disable pll ? be sure to ha v e interrupts enable to exit sleep mode ? make the mcu enter sleep mode resuming the usb interface ?enable pll ? wait pll lock ? unfreeze usb clock ? clear resume information 262 7593l?avr?09/12 at90usb64/128 23. usb device operating modes 23.1 introduction the usb de v ice controller supports full speed and lo w speed data transfers. in addition to the default control endpoint, it pro v ides six other endpoints, w hich can be configured in control, bulk, interrupt or isochronous modes: ? endpoint 0:programmable size fifo up to 64 bytes, default control endpoint ? endpoints 1 programmable size fifo up to 256 bytes in ping-pong mode ? endpoints 2 to 6: programmable size fifo up to 64 bytes in ping-pong mode the controller starts in the ?idle? mode. in this mode, the pad consumption is reduced to the minimum. 23.2 power-on and reset the next diagram explains the usb de v ice controller main states on po w er-on: figure 23-1. usb de v ice controller states after reset. the reset state of the de v ice controller is: ? the macro clock is stopped in order to minimize the po w er consumption (frzclk set) ? the usb de v ice controller internal state is reset (all the registers are reset to their default v alue. note that detach is set.) ? the endpoint banks are reset ? the d+ or d- pull up are not acti v ated (mode detach) the d+ or d- pull-up w ill be acti v ated as soon as the detach bit is cleared and vbus is present. the macro is in the ?idle? state after reset with a minimum power consumption and does not need to ha v e the pll acti v ated to enter in this state. the usb de v ice controller can at any time be reset by clearing usbe (disable usb interface). 23.3 endpoint reset an endpoint can be reset at any time by setting in the uerst register the bit corresponding to the endpoint (eprstx). this resets: ? the internal state machine on that endpoint ? the rx and tx banks are cleared and their internal pointers are restored reset idle hw reset usbe=0 263 7593l?avr?09/12 at90usb64/128 ? the ueintx, uesta0x and uesta1x are restored to their reset v alue the data toggle field remains unchanged. the other registers remain unchanged. the endpoint configuration remains acti v e and the endpoint is still enabled. the endpoint reset may be associated w ith a clear of the data toggle command (rstdt bit) as an ans w er to the clear_feature usb command. 23.4 usb reset when an usb reset is detected on the usb line, the next operations are performed by the controller: ? all the endpoints are disabled ? the default control endpoint remains configured (see section 23.3, page 262 for more details) 23.5 endpoint selection prior to any operation performed by the cpu, the endpoint must first be selected. this is done by setting the epnum2:0 bits (uenum register) w ith the endpoint number w hich w ill be man- aged by the cpu. the cpu can then access to the v arious endpoint registers and data. 23.6 endpoint activation the endpoint is maintained under reset as long as the epen bit is not set. the follo w ing flo w must be respected in order to acti v ate an endpoint: 264 7593l?avr?09/12 at90usb64/128 figure 23-2. endpoint acti v ation flo w . as long as the endpoint is not correct ly configured (cfgok cleared), the hard w are does not ackno w ledge the packets sent by the host. cfgok is w ill not be sent if the endpoint size parameter is bigger than the dpram size. a clear of epen acts as an endpoint reset (see section 23.3, page 262 for more details). it also performs the next operation: ? the configuration of the endpoint is kept (epsize, epbk, alloc kept) ? it resets the data toggle field ? the dpram memory associated to the endpoint is still reser v ed see section 22.7, page 252 for more details about the memory allocation/reorganization. 23.7 address setup the usb de v ice address is set up according to the usb protocol: ? the usb de v ice, after po w er-up, responds at address 0 ? the host sends a setup command (set_address(addr)) ? the firm w are records that address in uadd, but keep adden cleared ? the usb de v ice sends an in command of 0 bytes (in 0 zero length packet) ? then, the firm w are can enable the usb de v ice address by setting adden. the only accepted address by the controller is the one stored in uadd adden and uadd shall not be w ritten at the same time. uadd contains the default address 00h after a po w er-up or usb reset. endpoint activation cfgok=1 error no yes endpoint activated activate the endpoint select the endpoint epen=1 uenum epnum=x test the correct endpoint configuration uecfg1x alloc epsize epbk configure: - the endpoint size - the bank parametrization allocation and reorganization of the memory is made on-the-fly uecfg0x epdir eptype ... configure: - the endpoint direction - the endpoint type 265 7593l?avr?09/12 at90usb64/128 adden is cleared by hard w are: ? after a po w er-up reset ? w hen an usb reset is recei v ed ?or w hen the macro is disabled (usbe cleared) when this bit is cleared, the default de v ice address 00h is used. 23.8 suspend, w ake-up and resume after a period of 3ms during w hich the usb line w as inacti v e, the controller s w itches to the full- speed mode and triggers (if enabled) the suspi (suspend) interrupt. the firm w are may then set the frzclk bit. the cpu can also, depending on soft w are architecture, enter in the idle mode to lo w er again the po w er consumption. there are t w o w ays to reco v er from the ?suspend? mode: ? first one is to clear the frzclk bit. this is possible if the cpu is not in the idle mode ? second w ay, if the cpu is ?idle?, is to enable the wakeupi interrupt (wakeupe set). then, as soon as an non-idle signal is seen by the controller, the wakeupi interrupt is triggered. the firm w are shall then clear the frzclk bit to restart the transfer there are no relationship bet w een the suspi interrupt and th e wakeupi interrupt: the wake- upi interrupt is triggered as soon as there are non-idle patterns on the data lines. thus, the wakeupi interrupt can occurs e v en if the controller is not in the ?suspend? mode. when the wakeupi interrupt is tri ggered, if the su spi interrupt bit w as already set, it is cleared by hard w are. when the suspi interrupt is trigge red, if the wakeupi interrupt bit w as already set, it is cleared by hard w are. 23.9 detach the reset v alue of the detach bit is 1. it is possible to re-enumerate a de v ice, simply by setting and clearing the detach bit. ? setting detach w ill disconnect the pull-up on the d+ or d- pad (depending on full or lo w speed mode selected). then, clearing detach w ill connect the pull-up on the d+ or d- pad figure 23-3. detach a de v ice in full-speed. en=1 d + uvref d - detach, then attach en=1 d + uvref d - 266 7593l?avr?09/12 at90usb64/128 23.10 remote wake-up the ?remote wake-up? (or ?upstream resume?) request is the only operation allo w ed to be sent by the de v ice on its o w n initiati v e. any w ay, to do that, the de v ice should first ha v e recei v ed a device_remote_wakeup re quest from the host. ? first, the usb controller must ha v e detected the ?suspend? state of the line: the remote w ake- up can only be sent w hen a suspi flag is set ?the firm w are has then the ability to set rmwkup to send the ?upstr eam resume? stream. this w ill automatically be done by the controller after 5ms of inacti v ity on the usb line ? when the controller starts to send the ?upstream resume?, the uprsmi interrupt is triggered (if enabled). suspi is cleared by hard w are ? rmwkup is cleared by hard w are at the end of the ?upstream resume? ? if the controller detects a good ?end of resume? signal from the host, an eorsmi interrupt is triggered (if enabled) 23.11 stall request for each endpoint, the stall management is performed using t w o bits: ? stallrq (enable stall request) ? stallrqc (disable stall request) ? stalledi (stall sent interrupt) to send a stall handshake at the next request, the stallrq request bit has to be set. all fol- lo w ing requests w ill be handshak?ed w ith a stall until the stallrqc bit is set. setting stallrqc automatically clears the st allrq bit. the stallrqc bit is also immedi- ately cleared by hard w are after being set by soft w are. thus, the firm w are w ill ne v er read this bit as set. each time the stall handshake is sent, the stal ledi flag is set by the usb controller and the epintx interrupt w ill be triggered (if enabled). the incoming packets w ill be discarded (rxouti and rwal w ill not be set). the host w ill then send a command to reset the stall: the firm w are just has to set the stall- rqc bit and to reset the endpoint. 23.11.1 special considerat ion for control endpoints a setup request is al w ays ack?ed. if a stall request is set for a control endpoint and if a setup request occurs, the setup request has to be ack?ed and the stallrq request and stalledi sent flags are automati- cally reset (rxsetupi set, txin cleared, stalled cleared, txini cleared...). this management simplifies the enumeration process management. if a command is not sup- ported or contains an error, the firm w are set the stall request flag and can return to the main task, w aiting for the next setup request. this function is compliant w ith the chapter 8 test that may send extra status for a get_descriptor. the firm w are sets the stall request just after recei v ing the status. all extra status w ill be automatically stall?ed until the next setup request. 267 7593l?avr?09/12 at90usb64/128 23.11.2 stall handshake and retry mechanism the retry mechanism has priority o v er the stall handshake. a stall handshake is sent if the stallrq request bit is set and if there is no retry required. 23.12 control endpoint management a setup request is al w ays ack?ed. when a ne w setup packet is recei v ed, the rxstpi inter- rupt is triggered (if enabled). the rxouti interrupt is not triggered. the fifocon and rwal fields are irrele v ant w ith control endpoints. the firm w are shall thus ne v er use them on that endpoints. when read, their v alue is al w ays 0. control endpoints are managed by the follo w ing bits: ? rxstpi is set w hen a ne w setup is recei v ed. it shall be cleared by firm w are to ackno w ledge the packet and to clear the endpoint bank ? rxouti is set w hen a ne w out data is recei v ed. it shall be cleared by firm w are to ackno w ledge the packet and to clear the endpoint bank ? txini is set w hen the bank is ready to accept a ne w in packet. it shall be cleared by firm w are to send the packet and to clear the endpoint bank 23.12.1 control write figure 23-4 sho w s a control w rite transaction. during the status stage, the controller w ill not nec- essary send a nak at the first in token: ? if the firm w are kno w s the exact number of descriptor bytes that must be read, it can then anticipate on the status stage and send a zlp for the next in token ? or it can read the bytes and poll nakini, w hich tells that all the bytes ha v e been sent by the host, and the transaction is no w in the status stage figure 23-4. control w rite transaction. 23.12.2 control read figure 23-5 on page 268 sho w s a control read transaction. the usb controller has to manage the simultaneous w rite requests from the cpu and the usb host. setup rxstpi rxouti txini usb line hw sw out hw sw out hw sw in in nak sw data setup status 268 7593l?avr?09/12 at90usb64/128 figure 23-5. control read transaction. a nak handshake is al w ays generated at the first status stage command. when the controller detect the status stage, all the data w riten by the cpu are erased, and clearing txini has no effects. the firm w are checks if the transmission is complete or if the reception is complete. the out retry is al w ays ack?ed. this reception: - set the rxouti flag (recei v ed out data) - set the txini flag (data sent, ready to accept ne w data) soft w are algorithm: set transmit ready wait (transmit complete or receive complete) if receive complete, clear flag and return if transmit complete, continue once the out status stage has been recei v ed, the usb controller w aits for a setup request. the setup request ha v e priority o v er any other request and has to be ack?ed. this means that any other flag should be cleared and the fifo reset w hen a setup is recei v ed. warning: the byte counter is reset w hen the out zero length packet is recei v ed. the firm- w are has to take care of this. 23.13 out endpoint management out packets are sent by the host. all the data can be read by the cpu, w hich ackno w ledges or not the bank w hen it is empty. 23.13.1 overview the endpoint must be configured first. each time the current bank is full, the rxouti and the fifocon bits are set. this triggers an interrupt if the rxoute bit is set. the firm w are can ackno w ledge the usb interrupt by clearing the rxouti bit. the firm w are read the data and clear the fifocon bit in order to free the cur- rent bank. if the out endpoint is composed of multiple banks, clearing the fifocon bit w ill s w itch to the next bank. the rxouti and fifocon bits are then updated by hard w are in accor- dance w ith the status of the ne w bank. setup rxstpi rxouti txini usb line hw sw in hw sw in out out nak sw sw hw wr enable host wr enable cpu data setup status 269 7593l?avr?09/12 at90usb64/128 rxouti shall al w ays be cleared before clearing fifocon. the rwal bit al w ays reflects the state of the current bank. this bit is set if the firm w are can read data from the bank, and cleared by hard w are w hen the bank is empty. figure 23-6. example w ith 1 and 2 out data bank. 23.13.2 detailed description the data are read by the cpu, follo w ing the next flo w : ? when the bank is filled by the ho st, an endpoint interrupt (epint x) is triggered, if enabled (rxoute set) and rxouti is set. the cpu can also poll rxouti or fifocon, depending on the soft w are architecture ? the cpu ackno w ledges the interrupt by clearing rxouti ? the cpu can read the number of byte (n) in the current bank (n=byct) ? the cpu can read the data from the current bank (?n? read of uedatx) ? the cpu can free the bank by clearing fifocon w hen all the data is read, that is: ? after ?n? read of uedatx ? as soon as rwal is cleared by hard w are if the endpoint uses t w o banks, the second one ca n be filled by the host w hile the current one is being read by the cpu. then, w hen the cpu clear fifocon, the next bank may be already ready and rxouti is set immediately. 23.14 in endpoint management in packets are sent by the usb de v ice controller, upon an in request from the host. all the data can be w ritten by the cpu, w hich ackno w ledge or not the bank w hen it is full. out data (to bank 0) ack rxouti fifocon hw out data (to bank 0) ack hw sw sw sw read data from cpu bank 0 out data (to bank 0) ack rxouti fifocon hw out data (to bank 1) ack sw sw example with 2 out data banks read data from cpu bank 0 hw sw read data from cpu bank 0 read data from cpu bank 1 nak 270 7593l?avr?09/12 at90usb64/128 23.14.1 overview the endpoint must be configured first. the txini bit is set by hard w are w hen the current bank becomes free. this triggers an interrupt if the txine bit is set. the fifocon bit is set at the same time. the cpu w rites into the fifo and clears the fifocon bit to allo w the usb controller to send the data. if the in endpoint is composed of multiple banks, this also s w itches to the next data bank. the txini and fifocon bits are automatically updated by hard w are regarding the status of the next bank. txini shall al w ays be cleared before clearing fifocon. the rwal bit al w ays reflects the state of the current bank. this bit is set if the firm w are can w rite data to the bank, and cleared by hard w are w hen the bank is full. figure 23-7. example w ith 1 and 2 in data bank. 23.14.2 detailed description the data are w ritten by the cpu, follo w ing the next flo w : ? when the bank is empty, an endpoint interrupt (epintx) is triggered, if enabled (txine set) and txini is set. the cpu can also poll txini or fifocon, depending the soft w are architecture choice ? the cpu ackno w ledges the interrupt by clearing txini ?the cpu can w rite the data into the current bank ( w rite in uedatx) ? the cpu can free the bank by clearing fifocon w hen all the data are w ritten, that is: ? after ?n? w rite into uedatx ? as soon as rwal is cleared by hard w are in data (bank 0) ack txini fifocon hw write data from cpu bank 0 example with 2 in data banks sw sw sw sw in in data (bank 0) ack txini fifocon write data from cpu bank 0 sw sw sw sw in data (bank 1) ack write data from cpu bank 0 write data from cpu bank 1 sw hw write data from cpu bank0 nak 271 7593l?avr?09/12 at90usb64/128 if the endpoint uses t w o banks, the second one can be read by the host w hile the current is being w ritten by the cpu. then, w hen the cpu clears fifocon, the next bank may be already ready (free) and txini is set immediately. 23.14.2.1 abort an ?abort? stage can be produced by the host in some situations: ? in a control transaction: zlp data out recei v ed during a in stage ? in an isochronous in transaction: zlp data out recei v ed on the out endpoint during a in stage on the in endpoint ?... the killbk bit is used to kill the last ? w ritten? bank. the best w ay to manage this abort is to per- form the follo w ing operations: table 23-1. abort flo w . 23.15 isochronous mode 23.15.1 underflow an underflo w can occur during in stage if the host attempts to read a bank w hich is empty. in this situation, the underf i interrupt is triggered. an underflo w can also occur during out stage if the host send a packet w hile the banks are already full. typically, he cpu is not fast enough. the packet is lost. it is not possible to ha v e underflo w error during out stage, in the cpu side, since the cpu should read only if the bank is ready to gi v e data (rxouti=1 or rwal=1) 23.15.2 crc error a crc error can occur during out stage if the usb controller detects a bad recei v ed packet. in this situation, the stalledi interrupt is triggered. this does not pre v ent the rxouti interrupt from being triggered. endpoint abort abort done abort is based on the fact that no banks are busy, meaning that nothing has to be sent. disable the txini interrupt. endpoint reset nbusybk =0 yes clear ueienx. txine no killbk=1 killbk=1 yes kill the last written bank. wait for the end of the procedure. no 272 7593l?avr?09/12 at90usb64/128 23.16 overflow in control, isochronous, bulk or interrupt endpoint, an o v erflo w can occur during out stage, if the host attempts to w rite in a bank that is too small for the packet. in this situation, the overfi interrupt is triggered (if enabled). the packet is ackno w ledged and the rxouti interrupt is also triggered (if enabled) . the bank is filled w ith the first bytes of the packet. it is not possible to ha v e o v erflo w error during in stage, in the cpu side, since the cpu should w rite only if the bank is ready to access data (txini=1 or rwal=1). 23.17 interrupts figure 23-8 sho w s all the interr upts sources. figure 23-8. usb de v ice controller in terrupt system. there are t w o kinds of interrupts: processing (that is, their generation are part of the normal pro- cessing) and exception (errors). processing interrupts are generated w hen: ? vbus plug-in detection (insert, remo v e)( vbusti ) ? upstream resume( uprsmi ) ? end of resume( eorsmi ) ? wake up( wakeupi ) ? end of reset (speed initialization)( eorsti ) ? start of frame( sofi , if fncerr=0) ? suspend detected after 3ms of inacti v ity( suspi ) exception interrupts are generated w hen: ? crc error in frame number of sof( sofi , fncerr=1) uprsmi udint.6 uprsme udien.6 eorsmi udint.5 eorsme udien.5 wakeupi udint.4 wakeupe udien.4 eorsti udint.3 eorste udien.3 sofi udint.2 sofe udien.2 suspi udint.0 suspe udien.0 usb device interrupt 273 7593l?avr?09/12 at90usb64/128 figure 23-9. usb de v ice controller endpoint interrupt system. processing interrupts are generated w hen: ? ready to accept in data( epintx , txini=1) ? recei v ed out data( epintx , rxouti=1) ? recei v ed setup( epintx , rxstpi=1) exception interrupts are generated w hen: ? stalled packet( epintx , stalledi=1) ? crc error on out in isochronous mode( epintx , stalledi=1) ?o v erflo w in isochronous mode( epintx , overfi=1) ? underflo w in isochronous mode( epintx , underfi=1) ? nak in sent( epintx , nakini=1) ? nak out sent( epintx , nakouti=1) 23.18 registers 23.18.1 usb device general registers epint ueint.x endpoint 0 endpoint 1 endpoint 2 endpoint 3 endpoint 4 endpoint 5 endpoint interrupt endpoint 6 flerre ueienx.7 overfi uestax.6 underfi uestax.5 nakini ueintx.6 nakine ueienx.6 nakouti ueintx.4 txstpe ueienx.4 rxstpi ueintx.3 txoute ueienx.3 rxouti ueintx.2 rxoute ueienx.2 stalledi ueintx.1 stallede ueienx.1 txini ueintx.0 txine ueienx.0 bit 76543 2 1 0 ----- lsm rmwkup detach udcon read/ w riterrrrrr/wr/wr/w initial v alue00000 0 0 1 274 7593l?avr?09/12 at90usb64/128 ? 7-3 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 2 - lsm - usb device low speed mode selection when configured usb is configured in de v ice mode, this bit allo w s to select the usb the usb lo w speed or full speed mod. clear to select full speed mode (d+ internal pull-up w ill be acti v ate w ith the attach bit w ill be set) . set to select lo w speed mode (d- internal pull-up w ill be acti v ate w ith the attach bit w ill be set). this bit has no effect w hen the usb interface is configured in host mode. ? 1- rmwkup - remote wake-up bit set to send an ?upstream-resume? to the host for a remote w ake-up (the suspi bit must be set). cleared by hard w are w hen signalling finished. clearing by soft w are has no effect. see section 23.10, page 266 for more details. ? 0 - detach - detach bit set to physically detach de de v ice (disconnect internal pull-up on d+ or d-). clear to reconnect the de v ice. see section 23.9, page 265 for more details. ? 7 - reserved the v alue read from this bits is al w ays 0. do not set this bit. ? 6 - uprsmi - upstream resume interrupt flag set by hard w are w hen the usb controller is sending a resume signal called ?upstream resume?. this triggers an u sb interrupt if uprsme is set. shall be cleared by soft w are (usb clocks must be enabled before). setting by soft w are has no effect. ? 5 - eorsmi - end of resume interrupt flag set by hard w are w hen the usb controller detects a good ?end of resume? signal initiated by the host. this triggers an u sb interrupt if eorsme is set. shall be cleared by soft w are. setting by soft w are has no effect. ? 4 - wakeupi - wake-up cpu interrupt flag set by hard w are w hen the usb controller is re-acti v ated by a filtered non-idle signal from the lines (not by an upstream resume). this trigger s an interrupt if wakeupe is set. this interrupt should be enable only to w ake up the cpu core from po w er do w n mode. shall be cleared by soft w are (usb clock inputs must be enabled before). setting by soft w are has no effect. see section 23.8, page 265 for more details. bit 76543210 - uprsmi eorsmi wakeupi eorsti sofi - suspi udint read/ w rite initial v alue00000000 275 7593l?avr?09/12 at90usb64/128 ? 3 - eorsti - end of reset interrupt flag set by hard w are w hen an ?end of reset? has been detected by the usb controller. this triggers an usb interrupt if eorste is set. shall be cleared by soft w are. setting by soft w are has no effect. ? 2 - sofi - start of frame interrupt flag set by hard w are w hen an usb ?start of frame? pid (sof) has been detected (e v ery 1ms). this triggers an usb interrupt if sofe is set. ? 1 - reserved the v alue read from this bits is al w ays 0. do not set this bit ? 0 - suspi - suspend interrupt flag set by hard w are w hen an usb ?suspend? ?idle bus for three frame periods: a j state for 3ms) is detected. this triggers an u sb interrupt if suspe is set. shall be cleared by soft w are. setting by soft w are has no effect. see section 23.8, page 265 for more details. the interrupt bits are set e v en if their corresponding ?enable? bits is not set. ? 7 - reserved the v alue read from this bits is al w ays 0. do not set this bit. ? 6 - uprsme - upstream resume interrupt enable bit set to enable the uprsmi interrupt. clear to disable the uprsmi interrupt. ? 5 - eorsme - end of resume interrupt enable bit set to enable the eorsmi interrupt. clear to disable the eorsmi interrupt. ? 4 - wakeupe - wake-up cpu interrupt enable bit set to enable the wakeupi interrupt. for correct interrupt handle execution, this interrupt should be enable only before entering po w er-do w n mode. clear to disable the wakeupi interrupt. ? 3 - eorste - end of reset interrupt enable bit set to enable the eorsti interrupt. this bit is set after a reset. clear to disable the eorsti interrupt. ? 2 - sofe - start of frame interrupt enable bit set to enable the sofi interrupt. clear to disable the sofi interrupt. bit 76543210 - uprsme eorsme wakeupe eorste sofe - suspe udien read/ w rite initial v alue 0 0 0 0 0 0 0 0 276 7593l?avr?09/12 at90usb64/128 ? 1 - reserved the v alue read from this bits is al w ays 0. do not set this bit ? 0 - suspe - suspend interrupt enable bit set to enable the suspi interrupt. clear to disable the suspi interrupt. ? 7 - adden - address enable bit set to acti v ate the uadd (usb address). cleared by hard w are. clearing by soft w are has no effect. see section 23.7, page 264 for more details. ? 6-0 - uadd6:0 - usb address bits load by soft w are to configure the de v ice address. ? 7-3 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 2-0 - fnum10:8 - frame number upper value set by hard w are. these bits are the three msb of the 11-bits frame number information. they are pro v ided in the last recei v ed sof packet. fnum is updated if a corrupted sof is recei v ed. ? frame number lower value set by hard w are. these bits are the eight lsb of the 11-bits frame number information. ? 7-5 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 4 - fncerr -frame number crc error flag set by hard w are w hen a corrupted frame number in start of frame packet is recei v ed. this bit and the sofi interrupt are updated at the same time. bit 76543210 adden uadd6:0 udaddr read/ w rite w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543 2 1 0 ----- fnum10:8 udfnumh read/ w riterrrrrrrr initial v alue00000 0 0 0 bit 76543210 fnum7:0 udfnuml read/ w riterrrrrrrr initial v alue00000000 bit 76543210 - - - fncerr - - - - udmfn read/ w rite r initial v alue00000000 277 7593l?avr?09/12 at90usb64/128 ? 3-0 - reserved the v alue read from these bits is al w ays 0. do not set these bits. 23.18.2 usb device endpoint registers ? 7-3 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 2-0 - epnum2:0 endpoint number bits load by soft w are to select the number of the endpoint w hich shall be accessed by the cpu. see section 23.5, page 263 for more details. epnum = 111b is forbidden. ? 7 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 6-0 - eprst6:0 - endpoint fifo reset bits set to reset the selected endpoint fifo prior to any other operation, upon hard w are reset or w hen an usb bus reset has been recei v ed. see section 23.3, page 262 for more information then, clear by soft w are to complete the reset operation and start using the endpoint. ? 7-6 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 5 - stallrq - stall request handshake bit set to request a stall ans w er to the host for the next handshake. cleared by hard w are w hen a ne w setup is recei v ed. clearing by soft w are has no effect. see section 23.11, page 266 for more details. ? 4 - stallrqc - stall re quest clear handshake bit set to disable the stall handshake mechanism. cleared by hard w are immediately after the set. clearing by soft w are has no effect. see section 23.11, page 266 for more details. bit 76543210 - - - - - epnum2:0 uenum read/ w riterrrrrr/wr/wr/w initial v alue00000000 bit 76543210 - eprst6 eprst5 eprst4 eprst 3 eprst2 eprst1 eprst0 uerst read/ w rite r r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543210 - - stallrq stallrqc rstdt - - epen ueconx read/ w rite r r w w w r r r/w initial v alue 0 0 0 0 0 0 0 0 278 7593l?avr?09/12 at90usb64/128 ? rstdt - reset data toggle bit set to automatically clear the data toggle sequence: for out endpoint: the next recei v ed packet w ill ha v e the data toggle 0. for in endpoint: the next packet to be sent w ill ha v e the data toggle 0. cleared by hard w are instantaneously. the firm w are does not ha v e to w ait that the bit is cleared. clearing by soft w are has no effect. ? 2 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 1 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 0 - epen - endpoint enable bit set to enable the endpoint according to the de v ice configuration. endpoint 0 shall al w ays be enabled after a hard w are or usb reset and participate in the de v ice configuration. clear this bit to disable the endpoint. see section 23.6, page 263 for more details. ? 7-6 - eptype1:0 - endpoint type bits set this bit according to the endpoint configuration: 00b: control10b: bulk 01b: isochronous11b: interrupt ? 5-4 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 3-2 - reserved for test purpose the v alue read from these bits is al w ays 0. do not set these bits. ? 1 - reserved the v alue read from this bits is al w ays 0. do not set this bit. ? 0 - epdir - endpoint direction bit set to configure an in direction for bulk, interrupt or isochronous endpoints. clear to configure an out direction for bulk, interrupt, isochronous or control endpoints. bit 76543210 eptype1:0 - - - - - epdir uecfg0x read/ w riter/wr/wrrrrrr/w initial v alue00000000 279 7593l?avr?09/12 at90usb64/128 ? 7 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 6-4 - epsize2:0 - endpoint size bits set this bit according to the endpoint size: 000b: 8 bytes 100b: 128 bytes (only for endpoint 1) 001b: 16 bytes 101b: 256 bytes (only for endpoint 1) 010b: 32 bytes 110b: reser v ed. do not use this configuration 011b: 64 bytes 111b: reser v ed. do not use this configuration ? 3-2 - epbk1:0 - endpoint bank bits set this field according to the endpoint size: 00b: one bank 01b: double bank 1xb: reser v ed. do not use this configuration ? 1 - alloc - endpoint allocation bit set this bit to allocate the endpoint memory. clear to free the endpoint memory. see section 23.6, page 263 for more details. ? 0 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 7 - cfgok - configuration status flag set by hard w are w hen the endpoint x size parameter (epsize) and the bank parametrization (epbk) are correct compared to the max fifo capacity and the max number of allo w ed bank. this bit is updated w hen the bit alloc is set. if this bit is cleared, the user should reprogram the uecfg1x register w ith correct epsize and epbk v alues. bit 7 6 5 4 3 2 1 0 - epsize2:0 epbk1:0 alloc - uecfg1x read/ w rite r r/w r/w r/w r/w r/w r/w r initial v alue 0 0 0 0 0 0 0 0 bit 76543210 cfgok overfi underfi - dtseq1:0 nbusybk1:0 uesta0x read/ w rite r r/w r/w r/w r r r r initial v alue 0 0 0 0 0 0 0 0 280 7593l?avr?09/12 at90usb64/128 ? 6 - overfi - overflow error interrupt flag set by hard w are w hen an o v erflo w error occurs in an isochronous endpoint. an interrupt (epintx) is triggered (if enabled). see section 23.15, page 271 for more details. shall be cleared by soft w are. setting by soft w are has no effect. ? 5 - underfi - flow error interrupt flag set by hard w are w hen an underflo w error occurs in an isochronous endpoint. an interrupt (epintx) is triggered (if enabled). see section 23.15, page 271 for more details. shall be cleared by soft w are. setting by soft w are has no effect. ? 4 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 3-2 - dtseq1:0 - data toggle sequencing flag set by hard w are to indicate the pid data of the current bank: 00b data0 01b data1 1xb reser v ed for out transfer, this v alue indicates the last data toggle recei v ed on the current bank. for in transfer, it indicates the toggle that w ill be used for the next packet to be sent. this is not relati v e to the current bank. ? 1-0 - nbusybk1:0 - busy bank flag set by hard w are to indicate the number of busy bank. for in endpoint, it indicates the number of busy ba nk(s), filled by the user, ready for in transfer. for out endpoint, it indicates the number of busy bank(s) filled by out transaction from the host. 00b all banks are free 01b one busy bank 10b t w o busy banks 11b reser v ed ? 7-3 - reserved the v alue read from these bits is al w ays 0. do not set these bits. bit 76543 2 10 - - - - - ctrldir currbk1:0 uesta1x read/ w riterrrrr r rr initial v alue 0 0 0 0 0 0 0 0 281 7593l?avr?09/12 at90usb64/128 ? 2 - ctrldir - control direction (flag, and bit for debug purpose) set by hard w are after a setup packet, and gi v es the direction of the follo w ing packet: - 1 for in endpoint - 0 for out endpoint can not be set or cleared by soft w are. ? 1-0 - currbk1:0 - current bank (all endpoints except control endpoint) flag set by hard w are to indicate the number of the current bank: 00b bank0 01b bank1 1xb reser v ed can not be set or cleared by soft w are. ? 7 - fifocon - fifo control bit for out and setup endpoint: set by hard w are w hen a ne w out message is stored in the current bank, at the same time than rxout or rxstp. clear to free the current bank and to s w itch to the follo w ing bank. setting by soft w are has no effect. for in endpoint: set by hard w are w hen the current bank is free, at the same time than txin. clear to send the fifo data and to s w itch the bank. setting by soft w are has no effect. ? 6 - nakini - nak in received interrupt flag set by hard w are w hen a nak handshake has been sent in response of a in request from the host. this triggers an usb in terrupt if nakine is sent. shall be cleared by soft w are. setting by soft w are has no effect. ? 5 - rwal - read/write allowed flag set by hard w are to signal: - for an in endpoint: the current bank is not full, that is, the firm w are can push data into the fifo, - for an out endpoint: the current bank is not empty, that is, the firm w are can read data from the fifo. the bit is ne v er set if stallrq is set, or in case of error. cleared by hard w are other w ise. this bit shall not be used for the control endpoint. bit 76543210 fifocon nakini rwal nakouti rxstp i rxouti stalledi txini ueintx read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 282 7593l?avr?09/12 at90usb64/128 ? 4 - nakouti - nak out re ceived interrupt flag set by hard w are w hen a nak handshake has been sent in response of a out/ping request from the host. this triggers an u sb interrupt if nakoute is sent. shall be cleared by soft w are. setting by soft w are has no effect. ? 3 - rxstpi - received setup interrupt flag set by hard w are to signal that the current bank contains a ne w valid setup packet . an inter- rupt (epintx) is triggered (if enabled). shall be cleared by soft w are to handshake the interrupt. setting by soft w are has no effect. this bit is inacti v e (cleared) if the endpoint is an in endpoint. ? 2 - rxouti / killbk - received out data interrupt flag set by hard w are to signal that the current bank contains a ne w packet. an interrupt (epintx) is triggered (if enabled). shall be cleared by soft w are to handshake the interrupt. setting by soft w are has no effect. kill bank in bit set this bit to kill the last w ritten bank. cleared by hard w are w hen the bank is killed. clearing by soft w are has no effect. see page 271 for more details on the abort. ? 1 - stalledi - stalledi interrupt flag set by hard w are to signal that a stall handshake has been sent, or that a crc error has been detected in a out isochronous endpoint. shall be cleared by soft w are. setting by soft w are has no effect. ? 0 - txini - transmitter ready interrupt flag set by hard w are to signal that the curren t bank is free and can be fille d. an interrup t (epintx) is triggered (if enabled). shall be cleared by soft w are to handshake the interrupt. setting by soft w are has no effect. this bit is inacti v e (cleared) if the endpoint is an out endpoint. ? 7 - flerre - flow error interrupt enable flag set to enable an endpoint interrupt (epintx) w hen overfi or underfi are sent. clear to disable an endpoint interrupt (epintx) w hen overfi or underfi are sent. ? 6 - nakine - nak in interrupt enable bit set to enable an endpoint interrupt (epintx) w hen nakini is set. clear to disable an endpoint interrupt (epintx) w hen nakini is set. bit 76543210 flerre nakine - nakoute rxstpe rxoute stallede txine ueienx read/ w rite r/w r/w r r/w r/w r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 283 7593l?avr?09/12 at90usb64/128 ? 5 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 4 - nakoute - nak out interrupt enable bit set to enable an endpoint interrupt (epintx) w hen nakouti is set. clear to disable an endpoint interrupt (epintx) w hen nakouti is set. ? 3 - rxstpe - received set up interrupt enable flag set to enable an endpoint interrupt (epintx) w hen rxstpi is sent. clear to disable an endpoint interrupt (epintx) w hen rxstpi is sent. ? 2 - rxoute - received out data interrupt enable flag set to enable an endpoint interrupt (epintx) w hen rxouti is sent. clear to disable an endpoint interrupt (epintx) w hen rxouti is sent. ? 1 - stallede - stalled interrupt enable flag set to enable an endpoint interrupt (epintx) w hen stalledi is sent. clear to disable an endpoint interrupt (epintx) w hen stalledi is sent. ? 0 - txine - transmitter ready interrupt enable flag set to enable an endpoint interrupt (epintx) w hen txini is sent. clear to disable an endpoint interrupt (epintx) w hen txini is sent. ? 7-0 - dat7:0 -data bits set by the soft w are to read/ w rite a byte from/to the endpoint fifo selected by epnum. ? 7-3 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 2-0 - byct10:8 - byte count (high) bits set by hard w are. this field is the msb of the byte count of the fifo endpoint. the lsb part is pro v ided by the uebclx register. bit 76543210 dat d7 dat d6 dat d5 dat d4 dat d3 dat d2 dat d1 dat d0 uedatx read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 76543 2 1 0 - - - - - byct d10 byct d9 byct d8 uebchx read/ w riterrrrr r r r initial v alue00000 0 0 0 284 7593l?avr?09/12 at90usb64/128 ? 7-0 - byct7:0 - byte count (low) bits set by the hard w are. byct10:0 is: - (for in endpoint) increased after each w riting into the endpoint and decremented after each byte sent, - (for out endpoint) increased after each byte sent by the host, and decremented after each byte read by the soft w are. ? 7 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 6-0 - epint6:0 - endpoint interrupts bits set by hard w are w hen an interrupt is triggered by the ueintx register and if the corresponding endpoint interrupt enable bit is set. cleared by hard w are w hen the interrupt source is ser v ed. bit 76543210 byct d7 byct d6 byct d5 byct d4 byct d3 byct d2 byct d1 byct d0 uebclx read/ w riterrrrrrrr initial v alue00000000 bit 76543210 - epint d6 epint d5 epint d4 epint d3 epint d2 epint d1 epint d0 ueint read/ w riterrrrrrrr initial v alue00000000 285 7593l?avr?09/12 at90usb64/128 24. usb host operating modes this mode is a v ailable only on atmel at90usb647/1287 products. 24.1 pipe description for the usb host controller, the term of pipe is used instead of endpoint for the usb de v ice controller. a host pipe corresponds to a de v ice endpoint, as described in the usb specification. figure 24-1. pipes and endpoints in a usb system. in the usb host controller, a pipe w ill be associated to a de v ice endpoint, considering the de v ice configuration descriptors. 24.2 detach the reset v alue of the detach bit is 1. thus, the firm w are has the responsib ility of clearing this bit before s w itching to the host mode (host set). 24.3 power-on and reset figure 24-2 explains the usb host controller main states on po w er-on. figure 24-2. usb host controller states after reset. host ready host idle device disconnection 286 7593l?avr?09/12 at90usb64/128 usb host controller state after an hard w are reset is ?reset?. when the usb controller is enabled and the usb host controller is selected, the usb cont roller is in ?idle? state. in this state, the usb host controller w aits for the de v ice connection, with a minimum power consumption . the usb pad should be in idle mode. the macro does not need to ha v e the pll acti v ated to enter in ?host ready? state. the host controller ente rs in suspend state w hen the usb bus is in suspend state, that is, w hen the host controller doesn?t generate the start of frame. in this state, the usb consumption is minimum. the host controller exits to the suspend state w hen starting to generate the sof o v er the usb line. 24.4 device detection a de v ice is detected by the usb controller w hen the usb bus if different from d+ and d- lo w . in other w ords, w hen the usb host controller detects the de v ice pull-up on the d+ line. to enable this detection, the host controller has to pro v ide the vbus po w er supply to the de v ice. the de v ice disconnection is detected by the usb host controller w hen the usb idle correspond to d+ and d- lo w on the usb line. 24.5 pipe selection prior to any operation performed by the cpu, the pipe must first be selected. this is done by setting pnum2:0 bits (upnum register) w ith the pipe number w hich w ill be managed by the cpu. the cpu can then access to the v arious pipe registers and data. 24.6 pipe configuration the follo w ing flo w (see figure 24-3 on page 287 ) must be respected in order to acti v ate a pipe. 287 7593l?avr?09/12 at90usb64/128 figure 24-3. pipe acti v ation flo w . once the pipe is acti v ated (epen set) and, the hard w are is ready to send requests to the de v ice. when configured (cfgok = 1), only the pipe token (ptoken) and the polling inter v al for inter- rupt pipe can be modified. a control type pipe supports only one bank. any other v alue w ill lead to a configuration error (cfgok = 0). a clear of pen w ill reset the configuration of the pipe. all the corresponding pipe registers are reset to there reset v alues. please refer to ?memory management? on page 252 for more details. note: the firm w are has to configure the default control pipe w ith the follo w ing parameters: ? type: control ? token: setup ? data bank: 1 ? size: 64 bytes the firm w are asks for eight bytes of the de v ice descriptor sending a get_descriptor request. these bytes contains the maxpacketsize of the de v ice default control endpoint and the firm w are re-configures the size of the default control pipe w ith this size parameter. pipe activ ation upconx penable=1 upcfg0x ptype ptoken pepnum cfgok=1 error no yes upcfg2x intfrq (interrupt only) pipe activ ated and f reezed upcfg1x psize pbk cfgmem enable the pipe select the pipe type: * type (control, bulk, interrupt ) * token (in, out , setup) * endpoint number configure the pipe memory: * pipe size * number of banks configure the polling interval for interrupt pipe 288 7593l?avr?09/12 at90usb64/128 24.7 usb reset the usb controller sends a usb reset w hen the firm w are set the reset bit. the rsti bit is set by hard w are w hen the usb reset has been sent. this triggers an interrupt if the rste has been set. when a usb reset has been sent, all the pipe configuration and the memory allocation are reset. the general host interrupt enable register is left unchanged. if the bus w as pre v iously in suspend mode (sofen = 0), the usb controller automatically s w itches to the resume mode (hwupi is set) and the sofen bit is set by hard w are in order to generate sof immediately after the usb reset. 24.8 address setup once the de v ice has ans w er to the first host requests w ith the default address (0), the host assigns a ne w address to the de v ice. the host controller has to send a usb reset to the de v ice and perform a set addr ess control request, w ith the ne w address to be used by the de v ice. this control request ended, the firm w are w rite the ne w address into the uhaddr register. all follo w ing requests, on e v ery pipes, w ill be performed using this ne w address. when the host controller send a usb rese t, the uhaddr register is reset by hard w are and the follo w ing host requests w ill be performed using the default address (0). 24.9 remote wake-up detection the host controller enters in suspend mode w hen clearing the sofen bit. no more start of frame is sent on the usb bus and the usb de v ice enters in suspend mode 3ms later. the de v ice a w akes the host controller by sending an upstream resume (remote wake-up feature). the host controller detects a non-idle state on the usb bus and set the hwupi bit. if the non-idle correspond to an upstream resume (k state), the rxrsmi bit is set by hard w are. the firm w are has to generate a do w nstream resume w ithin 1ms and for at least 20ms by setting the resume bit. once the do w nstream resume has been generated, the sofen bit is automatically set by hard- w are in order to generate sof immediately after the usb resume. 24.10 usb pipe reset the firm w are can reset a pipe using the pipe reset r egister. the configuration of the pipe and the data toggle remains unchanged. only the bank management and the status bits are reset to their initial v alues. to completely reset a pipe, the firm w are has to disable and then enable the pipe. 24.11 pipe data access in order to read or to w rite into the pipe fifo, the cpu selects the pipe number w ith the upnum register and performs read or w rite action on the updatx register. host ready host suspend sofe=1 or hwup=1 sofe=0 289 7593l?avr?09/12 at90usb64/128 24.12 control pipe management a control transaction is composed of three phases: ? setup ? data (in or out) ? status (out or in) the firm w are has to change the token for each phase. the initial data toggle is set for the corresponding token (only for control pipe): ? setup: data0 ? out: data1 ? in: data1 (expected data toggle) 24.13 out pipe management the pipe must be configured and not frozen first. note: if the firm w are decides to s w itch to suspend mode (clear sofen) e v en if a bank is ready to be sent, the usb controller w ill automatically exit from suspend mode and the bank w ill be sent. the txout bit is set by hard w are w hen the current bank becomes free. this triggers an inter- rupt if the txoute bit is set. the fifocon bit is set at the same time. the cpu w rites into the fifo and clears the fifocon bit to allo w the usb controller to send the data. if the out pipe is composed of multiple banks, this also s w itches to the next data bank. the txout and fifocon bits are automatically updated by hard w are regarding the status of the next bank. 290 7593l?avr?09/12 at90usb64/128 figure 24-4. example w ith out data banks. 24.14 in pipe management the pipe must be configured first. when the host requires data from the de v ice, the firm w are has to determine first the in mode to use using the inmode bit: ? inmode = 0. the inrqx register is taken in account. the host controller w ill perform (inrqx+1) in requests on the selected pipe before freezing the pipe. this mode a v oids to ha v e extra in requests on a pipe ? inmode = 1. the usb controller w ill perform infinite in request until the firm w are freezes the pipe the in request generation w ill start w hen the firm w are clear the pfreeze bit. each time the current bank is full, the rxin and the fifocon bits are set. this triggers an inter- rupt if the rxine bit is set. the firm w are can ackno w ledge the usb interrupt by clearing the rxin bit. the firm w are read the data and clear the fifocon bit in order to free the current out data (bank 0) ack txout fifocon hw example with 1 out data bank write data from cpu bank 0 example with 2 out data banks sw sw sw sw out out data (bank 0) ack txout fifocon write data from cpu bank 0 sw sw sw sw out data (bank 1) ack write data from cpu bank 0 write data from cpu bank 1 sw hw write data from cpu bank0 example with 2 out data banks out data (bank 0) ack txout fifocon write data from cpu bank 0 sw sw sw sw write data from cpu bank 1 sw hw write data from cpu bank0 out data (bank 1) ack 291 7593l?avr?09/12 at90usb64/128 bank. if the in pipe is composed of multiple banks, clearing the fifocon bit w ill s w itch to the next bank. the rxin and fifocon bits are then updated by hard w are in accordance w ith the status of the ne w bank. figure 24-5. example w ith in data banks. 24.14.1 crc error (isochronous only) a crc error can occur during in stage if the usb controller detects a bad recei v ed packet. in this situation, the stalledi/crcerri interrupt is triggered. this does not pre v ent the rxini interrupt from being triggered. 24.15 interrupt system figure 24-6. usb host controlle r interrupt system. in data (to bank 0) ack rxin fifocon hw in data (to bank 0) ack hw sw sw sw example with 1 in data bank read data from cpu bank 0 in data (to bank 0) ack rxin fifocon hw in data (to bank 1) ack sw sw example with 2 in data banks read data from cpu bank 0 hw sw read data from cpu bank 0 read data from cpu bank 1 hwupe uhien.6 hwupi uhint.6 hsofi uhint.5 hsofe uhien.5 rxrsmi uhint.4 rxrsme uhien.4 rsmedi uhint.3 rsmede uhien.3 rsti uhint.2 rste uhien.2 ddisci uhint.1 ddisce uhien.1 dconni uhint.0 dconne uhien.0 usb host interrupt 292 7593l?avr?09/12 at90usb64/128 figure 24-7. usb de v ice controller pipe interrupt system. 24.16 registers 24.16.1 general usb host registers ? 7-3 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 2 - resume - send usb resume set this bit to generate a usb resume on the usb bus. cleared by hard w are w hen the usb resume has been sent. clearing by soft w are has no effect. this bit should be set only w hen the start of frame generation is enable (sofen bit set). ? 1 - reset - send usb reset set this bit to generate a usb reset on the usb bus. cleared by hard w are w hen the usb reset has been sent. clearing by soft w are has no effect. refer to the usb reset section for more details. ? 0 - sofen - start of frame generation enable set this bit to generate sof on the usb bus in full speed mode and keep-ali v e in lo w speed mode. clear this bit to disable the sof generation and to lea v e the usb bus in idle state. flerre upien.7 underfi upstax.5 overfi upstax.6 nakedi upintx.6 nakede upien.6 perri upintx.4 perre upien.4 txstpi upintx.3 txstpe upien.3 txouti upintx.2 txoute upien.2 rxstalli upintx.1 rxstalle upien.1 rxini upintx.0 rxine upien.0 flerre upien.7 pipe 0 pipe 1 pipe 2 pipe 3 pipe 4 pipe 5 pipe interrupt pipe 6 bit 76543210 ----- resume reset sofen uhcon read/ w riterrrrrr/wr/wr/w initial v alue00000000 293 7593l?avr?09/12 at90usb64/128 ? 7 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 6 - hwupi - host wake-up interrupt set by hard w are w hen a non-idle state is detected on the usb bus.this interrupt should be enable only to w ake up the cpu core from po w er do w n mode. shall be clear by soft w are to ackno w ledge the interrupt. setting by soft w are has no effect. ? 5 - hsofi - host start of frame interrupt set by hard w are w hen a sof is issued by the host controller. this triggers a usb interrupt w hen hsofe is set. when using the host controller in lo w speed mode, this bit is also set w hen a keep-ali v e is sent. shall be cleared by soft w are to ackno w ledge the interrupt. setting by soft w are has no effect. ? 4 - rxrsmi - upstream resume received interrupt set by hard w are w hen an upstream resume has been recei v ed from the de v ice. shall be cleared by soft w are. setting by soft w are has no effect. ? 3 - rsmedi - downstream resume sent interrupt set by hard w are w hen a do w nstream resume has been sent to the de v ice. shall be cleared by soft w are. setting by soft w are has no effect. ? 2 - rsti - usb reset sent interrupt set by hard w are w hen a usb reset has been sent to the de v ice. shall be cleared by soft w are. setting by soft w are has no effect. ? 1 - ddisci - device disconnection interrupt set by hard w are w hen the de v ice has been remo v ed from the usb bus. shall be cleared by soft w are. setting by soft w are has no effect. ? 0 - dconni - device connection interrupt set by hard w are w hen a ne w de v ice has been connected to the usb bus. shall be cleared by soft w are. setting by soft w are has no effect. ? 7 - reserved the v alue read from these bits is al w ays 0. do not set these bits. bit 76543210 - hwupi hsofi rxrsmi rsme di rsti ddisci dconni uhint read/ w rite r r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 bit 7654 321 0 hwupe hsofe rxrsme rsmede rste ddisce dconne uhien read/ w rite r r/w r/w r/w r/w r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 294 7593l?avr?09/12 at90usb64/128 ? 6 - hwupe - host wake-up interrupt enable set this bit to enable hwup interrupt.for correct interrupt handle execution, this interrupt should be enable only before entering po w er-do w n mode. clear this bit to disable hwup interrupt. ? 5 - hsofe - host start of frame interrupt enable set this bit to enable hsof interrupt. clear this bit to disable hsof interrupt. ? 4 - rxrsme -upstream resume received interrupt enable set this bit to enable the rxrsmi interrupt. clear this bit to disabl e the rxrsmi interrupt. ? 3 - rsmede - downstream resume sent interrupt enable set this bit to enable the rsmedi interrupt. clear this bit to disabl e the rsmedi interrupt. ? 2 - rste - usb reset sent interrupt enable set this bit to enable the rsti interrupt. clear this bit to disa ble the rsti interrupt. ? 1 - ddisce - device discon nection interrupt enable set this bit to enable the ddisci interrupt. clear this bit to disable the ddisci interrupt. ? 0 - dconne - device connection interrupt enable set this bit to enable the dconni interrupt. clear this bit to disable the dconni interrupt. ? 7 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 6-0 - haddr6:0 - usb host address these bits contain the address of the usb de v ice. bit 76543210 haddr6 haddr5 haddr4 haddr3 haddr2 haddr1 haddr0 haddr6 uhaddr read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 295 7593l?avr?09/12 at90usb64/128 ? 7-4 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 3-0 - fnum10:8 - frame number the v alue contained in this register is the current sof number. this v alue can be modified by soft w are. ? 7-0 - fnum7:0 - frame number the v alue contained in this register is the current sof number. this v alue can be modified by soft w are. ? 7-0 - flen7:0 - frame length the v alue contained the data frame length transmited. 24.16.2 usb host pipe registers ? 7-3 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 2-0 - pnum2:0 - pipe number select the pipe using this register. the usb host registers ended by a x correspond then to this number. this number is used for the usb controller follo w ing the v alue of the pnumd bit. bit 76543 2 1 0 - - - - - fnum10 fnum9 fnum8 uhfnumh read/ w riterrrrr r r r initial v alue00000 0 0 0 bit 76543210 fnum7 fnum6 fnum5 fnum4 fnum3 fnum2 fnum1 fnum0 uhfnuml read/ w riterrrrrrrr initial v alue00000000 bit 76543210 flen7 flen6 flen5 flen4 flen3 flen2 flen1 flen0 uhflen read/ w riterrrrrrrr initial v alue00000000 bit 76543 2 1 0 pnum2 pnum1 pnum0 upnum read/ w rite rw rw rw initial v alue00000 0 0 0 296 7593l?avr?09/12 at90usb64/128 ? 7 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 6 - p6rst - pipe 6 reset set this bit to 1 and reset this bit to 0 to reset the pipe 6. ? 5 - p5rst - pipe 5 reset set this bit to 1 and reset this bit to 0 to reset the pipe 5. ? 4 - p4rst - pipe 4 reset set this bit to 1 and reset this bit to 0 to reset the pipe 4. ? 3 - p3rst - pipe 3 reset set this bit to 1 and reset this bit to 0 to reset the pipe 3. ? 2 - p2rst - pipe 2 reset set this bit to 1 and reset this bit to 0 to reset the pipe 2. ? 1 - p1rst - pipe 1 reset set this bit to 1 and reset this bit to 0 to reset the pipe 1. ? 0 - p0rst - pipe 0 reset set this bit to 1 and reset this bit to 0 to reset the pipe 0. ? 7 - reserved the v alue read from this bit is al w ays 0. do not set this bit. ? 6 - pfreeze - pipe freeze set this bit to freeze the pipe requests generation. clear this bit to enable the pipe request generation. this bit is set by hard w are w hen: - the pipe is not configured - a stall handshake has been recei v ed on this pipe - an error occurs on the pipe (upintx. perri = 1) - (inrq+1) in requests ha v e been processed this bit is set at 1 by hard w are after a pipe reset or a pipe enable. bit 76543210 - p6rst p5rst p4rst p3rst p2rst p1rst p0rst uprst read/ w rite rw rw rw rw rw rw rw initial v alue00000000 bit 76543210 - pfreeze inmode - rstdt - - pen upconx read/ w rite rw rw rw rw initial v alue 0 0 0 0 0 0 0 0 297 7593l?avr?09/12 at90usb64/128 ? 5 - inmode - in request mode set this bit to allo w the usb controller to perform infinite in requests w hen the pipe is not frozen. clear this bit to perform a pre-defined number of in requests. this number is stored in the uin- rqx register. ? 4 - reserved the v alue read from this bit is al w ays 0. do not set this bit. ? 3 - rstdt - reset data toggle set this bit to reset the data toggle to its initial v alue for the current pipe. cleared by hard w are w hen proceed. clearing by soft w are has no effect. ? 2 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 1 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 0 - pen - pipe enable set to enable the pipe. clear to disable and set the pipe. ? 7-6 - ptype1:0 - pipe type select the type of the pipe: - 00: control - 01: isochronous - 10: bulk - 11: interrupt ? 5-4 - ptoken1:0 - pipe token select the token to associate to the pipe - 00: setup - 01: in - 10: out - 11: reser v ed ? 3-0 - pepnum3:0 - pipe endpoint number set this field according to the pipe configuration. set the number of the endpoint targeted by the pipe. this v alue is from 0 and 15. bit 76543210 ptype1 ptype0 ptoken1 ptoken0 pepnum3 pepnum2 pepnum1 pepnum0 upcfg0x read/ w rite rw rw rw rw rw rw rw rw initial v alue00000000 298 7593l?avr?09/12 at90usb64/128 ? 7 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 6-4 - psize2:0 - pipe size select the size of the pipe: - 000: 8 - 100: 128 (only for endpoint 1) - 001: 16 - 101: 256 (only for endpoint 1) - 010: 32 - 110: reser v ed. do not use this configuration. - 011: 64 - 111: reser v ed. do not use this configuration. ? 3-2 - pbk1:0 - pipe bank select the number of bank to declare for the current pipe. - 00: 1 bank - 01: 2 banks - 10: in v alid - 11: in v alid ? alloc - configure pipe memory set to configure the pipe memory w ith the characteristics. clear to update the memory allocation. refer to the memory management chapter for more details. 7 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 7 - intfrq7:0 - interrupt pipe request frequency these bits are the maximum v alue in millisecond of the polling period for an interrupt pipe. this v alue has no effect for a non-interrupt pipe. bit 7 6 5 4 3 2 1 0 - psize2:0 pbk1:0 alloc - upcfg1x read/ w rite r rw rw rw rw rw rw initial v alue 0 0 0 0 0 0 0 0 bit 76543210 intfrq7 intfrq6 intfrq5 intfrq4 intfrq3 intfrq2 intfrq1 intfrq0 upcfg2x read/ w rite rw rw rw rw rw rw rw rw initial v alue00000000 299 7593l?avr?09/12 at90usb64/128 ? 7 - cfgok - configure pipe memory ok set by hard w are if the required memory configuration has been successfully performed. cleared by hard w are w hen the pipe is disabled. the usb reset and the reset pipe ha v e no effect on the configuration of the pipe. ? 6 - overfi - overflow set by hard w are w hen a the current pipe has recei v ed more data than the maximum length of the current pipe. an interrupt is triggered if the flerre bit is set. shall be cleared by soft w are. setting by soft w are has no effect. ? 5 - underfi - underflow set by hard w are w hen a transaction underflo w occurs in the current isochronous or interrupt pipe. the pipe can?t send the data flo w required by the de v ice. a zlp w ill be sent instead. an interrupt is triggered if the flerre bit is set. shall be cleared by soft w are. setting by soft w are has no effect. note: the host controller has to send a out packet, but the bank is empty. a zlp w ill be sent and the underfi bit is set. ? 4 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 3-2 - dtseq1:0 - toggle sequencing flag set by hard w are to indicate the pid data of the current bank: 00b data0 01b data1 1xb reser v ed. for out pipe, this v alue indicates the next data toggle that w ill be sent. this is not relati v e to the current bank. for in pipe, this v alue indicates the last data toggle recei v ed on the current bank. ? 1-0 - nbusybk1:0 - busy bank flag set by hard w are to indicate the number of busy bank. for out pipe, it indicates the number of busy bank(s), filled by the user, ready for out transfer. for in pipe, it indicates the number of busy bank(s) filled by in transaction from the de v ice. 00b all banks are free 01b 1 busy bank 10b 2 busy banks 11b reser v ed. bit 76543210 cfgok overfi underfi - dtseq1:0 nbusybk upstax read/ w riterrwrw rrrr initial v alue00000000 300 7593l?avr?09/12 at90usb64/128 ? 7-0 - inrq7:0 - in request number before freeze enter the number of in transactions before the usb controller freezes the pipe. the usb con- troller w ill perform (inrq+1) in requests before to fr eeze the pipe. this co unter is automatically decreased by 1 each time a in request has been successfully performed. this register has no effect w hen the inmode bit is set (infinite in requests generation till the pipe is not frozen). ? 7-6 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 5 - counter1:0 - error counter this counter is increased by the usb controller each time an error occurs on the pipe. when this v alue reaches 3, the pipe is automatically frozen. clear these bits by soft w are. ? 4 - crc16 - crc16 error set by hard w are w hen a crc16 error has been detected. shall be cleared by soft w are. setting by soft w are has no effect. ? 3 - timeout - time-out error set by hard w are w hen a time-out error has been detected. shall be cleared by soft w are. setting by soft w are has no effect. ? 2 - pid - pid error set by hard w are w hen a pid error has been detected. shall be cleared by soft w are. setting by soft w are has no effect. ? 1 - datapid - data pid error set by hard w are w hen a data pid error has been detected. shall be cleared by soft w are. setting by soft w are has no effect. ? 0 - datatgl - bad data toggle set by hard w are w hen a data toggle error has been detected. shall be cleared by soft w are. setting by soft w are has no effect. bit 76543210 inrq7 inrq6 inrq5 inrq4 inrq 3 inrq2 inrq1 inrq0 upinrqx read/ w rite rw rw rw rw rw rw rw rw initial v alue00000000 bit 76543210 - counter1:0 crc16 timeout pid datapid datatgl uperrx read/ w rite rw rw rw rw rw rw rw initial v alue 0 0 0 0 0 0 0 0 301 7593l?avr?09/12 at90usb64/128 ? 7 - fifocon - fifo control for out and setup pipe: set by hard w are w hen the current bank is free, at the same time than txout or txstp. clear to send the fifo data and to s w itch the bank. setting by soft w are has no effect. for in pipe: set by hard w are w hen a ne w in message is stored in the current bank, at the same time than rxin. clear to free the current bank and to s w itch to the follo w ing bank. setting by soft w are has no effect. ? 6 - nakedi - nak handshake received set by hard w are w hen a nak has been recei v ed on the current bank of the pipe. this triggers an interrupt if the nakede bit is set in the upienx register. shall be clear to handshake the interrupt. setting by soft w are has no effect. ? 5 - rwal - read/write allowed out pipe: set by hard w are w hen the firm w are can w rite a ne w data into the pipe fifo. cleared by hard w are w hen the current pipe fifo is full. in pipe: set by hard w are w hen the firm w are can read a ne w data into the pipe fifo. cleared by hard w are w hen the current pipe fifo is empty. this bit is also cleared by hard w are w hen the rxstall or the perr bit is set ? 4 - perri -pipe error set by hard w are w hen an error occurs on the current bank of the pipe. this triggers an interrupt if the perre bit is set in the upienx register. refers to the uperrx register to determine the source of the error. automatically cleared by hard w are w hen the error source bit is cleared. ? 3 - txstpi - setup bank ready set by hard w are w hen the current setup bank is free and can be filled. this triggers an inter- rupt if the txstpe bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by soft w are has no effect. ? 2 - txouti -out bank ready set by hard w are w hen the current out bank is free and can be filled. this triggers an interrupt if the txoute bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by soft w are has no effect. bit 765432 1 0 fifocon nakedi rwal perri txstpi txouti rxstalli rxini upintx read/ w rite rw rw rw rw rw rw rw rw initial v alue 0 0 0 0 0 0 0 0 302 7593l?avr?09/12 at90usb64/128 ? 1 - rxstalli / crcerr - stall received / isochronous crc error set by hard w are w hen a stall handshake has been recei v ed on the current bank of the pipe. the pipe is automatically frozen. this triggers an interrupt if the rxstalle bit is set in the upi- enx register. shall be cleared to handshake the interrupt. setting by soft w are has no effect. for isochronous pipe: set by hard w are w hen a crc error occurs on the current bank of the pipe. this triggers an inter- rupt if the txstpe bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by soft w are has no effect. ? 0 - rxini - in data received set by hard w are w hen a ne w usb message is stored in the current bank of the pipe. this trig- gers an interrupt if the rxine bit is set in the upienx register. shall be cleared to handshake the interrupt. setting by soft w are has no effect. ? 7 - flerre - flow error interrupt enable set to enable the overfi and underfi interrupts. clear to disable the overfi and underfi interrupts. ? 6 - nakede -nak handshake received interrupt enable set to enable t he nakedi interrupt. clear to disable th e nakedi interrupt. ? 5 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 4 - perre -pipe error interrupt enable set to enable the perri interrupt. clear to disable the perri interrupt. ? 3 - txstpe - setup bank ready interrupt enable set to enable the txstpi interrupt. clear to disable the txstpi interrupt. ? 2 - txoute - out bank ready interrupt enable set to enable the txouti interrupt. clear to disable the txouti interrupt. ? 1 - rxstalle - stall received interrupt enable set to enable the rxstalli interrupt. clear to disable the rxstalli interrupt. bit 7 6 5 4 3 2 1 0 flerre nakede - perre txstpe txoute rxstalle rxine upienx read/ w rite rw rw rw rw rw rw rw initial v alue 0 0 0 0 0 0 0 0 303 7593l?avr?09/12 at90usb64/128 ? 0 - rxine - in data received interrupt enable set to enable the rxini interrupt. clear to disable the rxini interrupt. ? 7-0 - pdat7:0 - pipe data bits set by the soft w are to read/ w rite a byte from/to the pipe fifo selected by pnum. ? 7-3 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 2-0 - pbyct10:8 - byte count (high) bits set by hard w are. this field is the msb of the byte count of the fifo endpoint. the lsb part is pro v ided by the upbclx register. ? 7-0 - pbyct7:0 - byte count (low) bits set by the hard w are. pbyct10:0 is: - (for out pipe) increased after each w riting into the pipe and decremented after each byte sent, - (for in pipe) increased after each byte recei v ed by the host, and decremented after each byte read by the soft w are. ? 7 - reserved the v alue read from these bits is al w ays 0. do not set these bits. ? 6-0 - pint6:0 - pipe interrupts bits set by hard w are w hen an interrupt is triggered by the upintx register and if the corresponding endpoint interrupt enable bit is set. cleared by hard w are w hen the interrupt source is ser v ed. bit 76543210 pdat7 pdat6 pdat5 pdat4 pdat3 pdat2 pdat1 pdat0 updatx read/ w rite rw rw rw rw rw rw rw rw initial v alue00000000 bit 76543 2 1 0 - - - - - pbyct10 pbyct9 pbyct8 upbchx read/ w rite rrr initial v alue00000 0 0 0 bit 76543210 pbyct7 pbyct6 pbyct5 pbyct4 pbyct3 pbyct2 pbyct1 pbyct0 upbclx read/ w riterrrrrrrr initial v alue00000000 bit 76543210 - pint6 pint5 pint4 pint3 pint2 pint1 pint0 upint read/ w rite initial v alue00000000 304 7593l?avr?09/12 at90usb64/128 25. analog comparator the analog comparator compares the input v alues on the positi v e pin ain0 and negati v e pin ain1. when the v oltage on the positi v e pin ain0 is higher than the v oltage on the negati v e pin ain1, the analog comparator output, aco, is set. the comparator?s output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusi v e to the analog comparator. the user can select interrupt triggering on com- parator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is sho w n in figure 25-1 . the po w er reduction adc bit, pradc, in ?prr0 ? po w er reduction register 0? on page 54 must be disabled by w riting a logical zero to be able to use the adc input mux. figure 25-1. analog comparator block diagram (2) . notes: 1. see table 25-2 on page 306 . 2. refer to figure 1-1 on page 3 and table 11-6 on page 79 for analog comparator pin placement. 25.0.1 adcsrb ? adc control and status register b ? bit 6 ? acme: analog comparator multiplexer enable when this bit is w ritten logic one and the adc is s w itched off (aden in adcsra is zero), the adc multiplexer selects the negati v e input to the analog comparator. when this bit is w ritten logic zero, ain1 is applied to the negati v e input of the analog comparator. for a detailed description of this bit, see ?analog comparator multiplexed input? on page 306 . 25.0.2 acsr ? analog comparator control and status register acbg bandgap reference adc multiplexer output acme aden (1) bit 7 6543210 ?acme ? ? - adts2 adts1 adts0 adcsrb read/ w rite r r/w r r r r/w r/w r/w initial v alue0 0000000 bit 76543210 acd acbg aco aci acie acic acis1 acis0 acsr read/ w rite r/w r/w r r/w r/w r/w r/w r/w initial v alue 0 0 n/a 0 0 0 0 0 305 7593l?avr?09/12 at90usb64/128 ? bit 7 ? acd: analog comparator disable when this bit is w ritten logic one, the po w er to the analog comparator is s w itched off. this bit can be set at any time to turn off the analog comparator. this w ill reduce po w er consumption in acti v e and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. other w ise an interrupt can occur w hen the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set, a fixed bandgap reference v oltage replaces the positi v e input to the analog comparator. when this bit is cleared, ain0 is applied to the positi v e input of the analog compar- ator. see ?internal v oltage reference? on page 62. ? bit 5 ? aco: analog comparator output the output of the analog comparator is synchronized and then directly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hard w are w hen a comparator output e v ent triggers the interrupt mode defined by acis1 and acis0. the analog comparator interr upt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hard w are w hen executing the corresponding inter- rupt handling v ector. alternati v ely, aci is cleared by w riting a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is w ritten logic one and the i-bit in the status register is set, the analog com- parator interrupt is acti v ated. when w ritten logic zero, the interrupt is disabled. ? bit 2 ? acic: analog comparator input capture enable when w ritten logic one, this bit enables the input capture function in timer/counter1 to be trig- gered by the analog comparator. the comparator output is in this case directly connected to the input capture front-end logic, making the compar ator utilize the noise canceler and edge select features of the timer/counter1 input capture interrupt. when w ritten logic zero, no connection bet w een the analog comparator and the input capture function exists. to make the comparator trigger the timer/counter1 input capture interrupt, the icie1 bit in the timer interrupt mask register (timsk1) must be set. ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine w hich comparator e v ents that trigger the analog comparator interrupt. the different settings are sho w n in table 25-1 . when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the acsr register. other w ise an interrupt can occur w hen the bits are changed. table 25-1. acis1/acis0 settings. acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle 0 1 reser v ed 1 0 comparator interrupt on falling output edge 1 1 comparator interrupt on rising output edge 306 7593l?avr?09/12 at90usb64/128 25.1 analog comparator multiplexed input it is possible to select any of the adc7..0 pins to replace the negati v e input to the analog com- parator. the adc multiplexer is used to select this input, and consequently, the adc must be s w itched off to utilize this feature. if the a nalog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is s w itched off (aden in adcsra is zero), and mux2..0 in admux select the input pin to replace the negati v e input to the analog comparator, as sho w n in table 25-2 . if acme is cleared or aden is set, ain1 is applied to the negati v e input to the ana- log comparator. 25.1.1 didr1 ? digital in put disable register 1 ? bit 1, 0 ? ain1d, ain0d: ai n1, ain0 digita l input disable when this bit is w ritten logic one, the digital input buffer on the ain1/0 pin is disabled. the corre- sponding pin register bit w ill al w ays read as zero w hen this bit is set. when an analog signal is applied to the ain1/0 pin and the digital input from this pin is not needed, this bit should be w rit- ten logic one to reduce po w er consumption in the digital input buffer. table 25-2. analog comparator multiplexed input. acme aden mux2..0 analog comparator negative input 0xxxxain1 11xxxain1 1 0 000 adc0 1 0 001 adc1 1 0 010 adc2 1 0 011 adc3 1 0 100 adc4 1 0 101 adc5 1 0 110 adc6 1 0 111 adc7 bit 76543210 ? ? ? ? ? ? ain1d ain0d didr1 read/ w riterrrrrrr/wr/w initial v alue00000000 307 7593l?avr?09/12 at90usb64/128 26. adc ? analog to digital converter 26.1 features ? 10-bit resolution ? 0.5 lsb integral non-linearity ? 2 lsb absolute accuracy ? 65 - 260s conversion time ? up to 15ksps at maximum resolution ? eight multiplexed single ended input channels ? seven differential input channels ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 2.56v adc reference voltage ? free running or single conversion mode ? adc start conversion by auto triggering on interrupt sources ? interrupt on adc conversion complete ? sleep mode noise canceler 26.2 overview the atmel at90usb64/128 features a 10-bit successi v e approximation adc. the adc is con- nected to an 8-channel analog multiplexer w hich allo w s eight single-ended v oltage inputs constructed from the pins of port f. the single-ended v oltage inputs refer to 0v (gnd). the de v ice also supports 16 differential v oltage input combinations. t w o of the differential inputs (adc1, adc0 and adc3, adc2) are equipped w ith a programmable gain stage, pro v iding amplification steps of 0 db (1), 20 db (10 ), or 46 db (200) on the differential input v oltage before the a/d con v ersion. se v en differential analog input channels share a common negati v e terminal (adc1), w hile any other adc input can be selected as the positi v e input terminal. if 1 or 10 gain is used, 8-bit resolution can be expected. if 200 gain is used, 7-bit resolution can be expected. the adc contains a sample and hold circuit w hich ensures that the input v oltage to the adc is held at a constant le v el during con v ersion. a block diagram of the adc is sho w n in figure 26-1 on page 308 . the adc has a separate analog supply v oltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 314 on ho w to connect this pin. internal reference v oltages of nominally 2.56v or av cc are pro v ided on-chip. the v oltage refer- ence may be externally decoupled at the aref pi n by a capacitor for better noise performance. 308 7593l?avr?09/12 at90usb64/128 figure 26-1. analog to digital con v erter block schematic. adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl. & status register (adcsra) adc data register (adch/adcl) mux2 adie adate adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux 3 conversion logic 10-bit dac + - sample & hold comparator internal reference mux decoder mux4 avcc adc7 adc6 adc5 adc4 adc 3 adc2 adc1 adc0 refs0 refs1 adlar + - channel selection gain selection adc[9:0] adc multiplexer output differential amplifier aref bandgap reference prescaler single ended / differential selection gnd pos. input mux neg. input mux trigger select adts[2:0] interrupt flags adhsm start 309 7593l?avr?09/12 at90usb64/128 26.3 operation the adc con v erts an analog input v oltage to a 10-bit digital v alue through successi v e approxi- mation. the minimum v alue represents gnd and the maximum v alue represents the v oltage on the aref pin minus 1 lsb. optionally, av cc or an internal 2.56v reference v oltage may be con- nected to the aref pin by w riting to the refsn bits in the admux register. the internal v oltage reference may thus be decoupled by an external capacitor at the aref pin to impro v e noise immunity. the analog input channel and differ ential gain are selected by w riting to the mux bits in admux. any of the adc input pins, as w ell as gnd and a fixed bandgap v oltage reference, can be selected as single ended inputs to the adc. a selection of adc input pins can be selected as positi v e and negati v e inputs to the differential amplifier. the adc is enabled by setting the adc enable bit, aden in adcsra. voltage reference and input channel selections w ill not go into effect until aden is set. the adc does not consume po w er w hen aden is cleared, so it is recommended to s w itch off the adc before entering po w er sa v ing sleep modes. the adc generates a 10-bit result w hich is presented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. other w ise, adcl must be read first, then adch, to ensure that the content of the data registers belongs to the same con v ersion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a con v ersion completes before adch is read, neither register is updated and the result from the con v ersion is lost. when adch is read, adc access to the adch and ad cl registers is re-enabled. the adc has its o w n interrupt w hich can be triggered w hen a con v ersion completes. the adc access to the data registers is prohibited bet w een reading of adch and adcl, the interrupt w ill trigger e v en if the result is lost. 26.4 starting a conversion a single con v ersion is started by w riting a logical one to the adc start con v ersion bit, adsc. this bit stays high as long as the con v ersion is in progress and w ill be cleared by hard w are w hen the con v ersion is completed. if a different data channel is selected w hile a con v ersion is in progress, the adc w ill finish the current con v ersion before performing the channel change. alternati v ely, a con v ersion can be triggered automatically by v arious sources. auto triggering is enabled by setting the adc auto trigger enable bi t, adate in adcsra. the trigger source is selected by setting the adc trig ger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positi v e edge occurs on the selected trigger signal, the adc prescaler is reset and a con v ersion is started. this pro v ides a method of starting con- v ersions at fixed inter v als. if the trigger signal is still set w hen the con v ersion completes, a ne w con v ersion w ill not be started. if another positi v e edge occurs on the trigger signal during con- v ersion, the edge w ill be ignored. note that an interrupt flag w ill be set e v en if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a con v ersion can thus be triggered w ithout causing an interrupt. ho w e v er, the interrupt flag must be cleared in order to trigger a ne w con v ersion at the next interrupt e v ent. 310 7593l?avr?09/12 at90usb64/128 figure 26-2. adc auto trigger logic. using the adc interrupt flag as a trigger source makes the adc start a ne w con v ersion as soon as the ongoing con v ersion has finished. the adc then operates in free running mode, con- stantly sampling and updating the adc data register. the first con v ersion must be started by w riting a logical one to the adsc bit in adcsra. in this mode the adc w ill perform successi v e con v ersions independently of w hether the adc interrupt flag, adif is cleared or not. if auto triggering is enabled, single con v ersions can be started by w riting adsc in adcsra to one. adsc can also be used to determine if a con v ersion is in progress. the adsc bit w ill be read as one during a con v ersion, independently of ho w the con v ersion w as started. 26.5 prescaling and conversion timing figure 26-3. adc prescaler. by default, the successi v e approximation circuitry requir es an input clock frequency bet w een 50khz and 200khz to get maximum resolution. if a lo w er resolution than 10 bits is needed, the input clock frequency to the adc can be higher th an 200khz to get a higher sample rate. alter- nati v ely, setting the adhsm bit in adcsrb allo w s an increased adc clock frequency at the expense of higher po w er consumption. the adc module contains a prescaler, w hich generates an acc eptable adc clock frequency from any cpu frequency abo v e 100khz. the prescaling is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is s w itched on by setting the aden bit ad s c adif s ource 1 s ource n adt s [2:0] conver s ion logic pre s caler s ta rt clk adc . . . . edge detector adate 7-bit adc pre s caler adc clock s ource ck adp s 0 adp s 1 adp s 2 ck/12 8 ck/2 ck/4 ck/ 8 ck/16 ck/32 ck/64 reset aden s tart 311 7593l?avr?09/12 at90usb64/128 in adcsra. the prescaler keeps running for as lo ng as the aden bit is set, and is continuously reset w hen aden is lo w . when initiating a single ended con v ersion by setting the adsc bit in adcsra, the con v ersion starts at the follo w ing rising edge of the ad c clock cycle. see ?differential channels? on page 312 for details on differential con v ersion timing. a normal con v ersion takes 13 adc clock cycles. the first con v ersion after the adc is s w itched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal con v er- sion and 13.5 adc clock cycles after the start of an first con v ersion. when a con v ersion is complete, the result is w ritten to the adc data registers, and adif is set. in single con v ersion mode, adsc is cleared simultaneously. the soft w are may then set adsc again, and a ne w con v ersion w ill be initiated on the firs t rising adc clock edge. when auto triggering is used, the prescaler is reset w hen the trigger e v ent occurs. this assures a fixed delay from the trigger e v ent to the start of con v ersion. in this mode, the sample-and-hold takes place t w o adc clock cycles after the rising edge on the trigger source signal. three addi- tional cpu clock cycles are used for synchronization logic. in free running mode, a ne w con v ersion w ill be started immediately after the con v ersion com- pletes, w hile adsc remains high. for a summary of con v ersion times, see table 26-1 on page 312 . figure 26-4. adc timing diagram, first con v ersion (single con v ersion mode). figure 26-5. adc timing diagram, single con v ersion. s ign and m s b of result l s b of result adc clock ad s c s ample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 1 8 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and ref s update mux and ref s update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 s ign and m s b of result l s b of result adc clock ad s c adif adch adcl cycle number 12 one conversion next conversion 3 s ample & hold mux and ref s update conversion complete mux and ref s update 312 7593l?avr?09/12 at90usb64/128 figure 26-6. adc timing diagram, auto triggered con v ersion. figure 26-7. adc timing diagram, free running con v ersion. 26.5.1 differential channels when using differential channels, certain aspects of the con v ersion need to be taken into consideration. differential con v ersions are synchronized to the internal clock ck adc2 equal to half the adc clock frequency. this synchroniza tion is done automatically by the adc interface in such a w ay that the sample-and-hold occurs at a specific phase of ck adc2 . a con v ersion initiated by the user (that is, all single con v ersions, and the first free running con v ersion) w hen ck adc2 is lo w w ill take the same amount of time as a single ended con v ersion (13 adc clock cycles from the next prescaled clock cycle). a con v ersion initiated by the user w hen ck adc2 is high w ill take 14 adc clock cycles due to the synchronization mechanism. in free running mode, a ne w con v ersion is initiated immediately after the pre v ious con v ersion completes, and since ck adc2 is high at this time, all automatically started (that is, all but the first) free running con v ersions w ill take 14 adc clock cycles. table 26-1. adc con v ersion time. condition first conversion normal conversion, single ended auto triggered conversion sample & hold (cycles from start of con v ersion) 14.5 1.5 2 con v ersion time (cycles) 25 13 13.5 1 2 3 4 5 6 7 8 9 10 11 12 13 s ign and m s b of result l s b of result adc clock trigger s ource adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset s ample & hold mux and ref s update 11 12 13 s ign and m s b of result l s b of result adc clock ad s c adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete s ample & hold mux and ref s update 313 7593l?avr?09/12 at90usb64/128 if differential channels are used and con v ersions are started by auto triggering, the adc must be s w itched off bet w een con v ersions. when auto triggering is used, the adc prescaler is reset before the con v ersion is started. since the stage is dependent of a stable adc clock prior to the con v ersion, this con v ersion w ill not be v alid. by disabling and then re-enabling the adc bet w een each con v ersion ( w riting aden in adcsra to ?0? then to ?1?), only extended con v ersions are performed. the result from the extended con v ersions w ill be v alid. see ?prescaling and con v er- sion timing? on page 310 for timing details. the gain stage is optimized for a band w idth of 4khz at a ll gain settings. higher frequencies may be subjected to non-linear amplification. an external lo w -pass filter should be used if the input signal contains higher frequency components than the gain stage band w idth. note that the adc clock frequency is independent of the gain stage band w idth limitation. fo r example, the adc clock period may be 6s, allo w ing a channel to be sampled at 12ksps, regardless of the band- w idth of this channel. 26.6 changing channel or reference selection the muxn and refs1:0 bits in the admux register are single buffered through a temporary register to w hich the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point during the con v ersion. the channel and reference selection is continuously updated until a con v ersion is started. once the con v ersion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. con- tinuous updating resumes in the last adc clock cycle before the con v ersion completes (adif in adcsra is set). note that the con v ersion starts on the follo w ing rising adc clock edge after adsc is w ritten. the user is thus ad v ised not to w rite ne w channel or reference selection v alues to admux until one adc cl ock cycle after adsc is w ritten. if auto triggering is used, the exact time of the triggering e v ent can be indeterministic. special care must be taken w hen updating the admux register, in order to control w hich con v ersion w ill be affected by the ne w settings. if both adate and aden is w ritten to one, an interrupt e v ent can occur at any time. if the admux register is changed in this period, the user cannot tell if the next con v ersion is based on the old or the ne w settings. admux can be safely updated in the follo w ing w ays: a. when adate or aden is cleared. b. during con v ersion, minimum one adc clock cycle after the trigger e v ent. c. after a con v ersion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the ne w settings w ill affect the next adc con v ersion. special care should be taken w hen changing differential channels. once a differential channel has been selected, the sta ge may take as much as 12 5s to stabilize to the ne w v alue. thus con v ersions should not be started w ithin the first 125s after selecting a ne w differential chan- nel. alternati v ely, con v ersion results obtained w ithin this period should be discarded. the same settling time should be obser v ed for the first differential con v ersion after changing adc reference (by changing the refs1:0 bits in admux). the settling time and gain stage band w idth is independent of the adhsm bit setting. 314 7593l?avr?09/12 at90usb64/128 26.6.1 adc input channels when changing channel selections, the user should obser v e the follo w ing guidelines to ensure that the correct channel is selected: ? in single con v ersion mode, al w ays select the channel before starting the con v ersion. the channel selection may be changed one adc clock cycle after w riting one to adsc. ho w e v er, the simplest method is to w ait for the con v ersion to complete before changing the channel selection ? in free running mode, al w ays select the channel before starting the first con v ersion. the channel selection may be changed one adc clock cycle after w riting one to adsc. ho w e v er, the simplest method is to w ait for the first con v ersion to complete, and then change the channel selection. since the next con v ersion has already started automatically, the next result w ill reflect the pre v ious channel selection. subsequent con v ersions w ill reflect the ne w channel selection when s w itching to a differential gain channel, the first con v ersion result may ha v e a poor accu- racy due to the required settling time for the automatic offset cancellation circuitry. the user should preferably disregard the first con v ersion result. 26.6.2 adc voltage reference the reference v oltage for the adc (v ref ) indicates the con v ersion range for the adc. single ended channels that exceed v ref w ill result in codes close to 0x3ff. v ref can be selected as either av cc , internal 2.56v reference, or external aref pin. av cc is connected to the adc through a passi v e s w itch. the internal 2.56v reference is gener- ated from the internal bandgap reference (v bg ) through an internal amplifier. in either case, the external aref pin is directly connected to the adc, and the reference v oltage can be made more immune to noise by connecting a capacitor bet w een the aref pin and ground. v ref can also be measured at the aref pin w ith a high impedant v oltmeter. note that v ref is a high impedant source, and only a capaciti v e load should be connected in a system. if the user has a fixed v oltage source connected to the aref pin, the user may not use the other reference v oltage options in the application, as they w ill be shorted to the external v oltage. if no external v oltage is applied to the aref pin, the user may s w itch bet w een av cc and 2.56v as reference selection. the first adc con v ersion result after s w itching reference v oltage source may be inaccurate, and the user is ad v ised to discard this result. if differential channels are used, the selected reference should not be closer to av cc than indi- cated in table 31-5 on page 397 . 26.7 adc noise canceler the adc features a noise canceler that enables con v ersion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used w ith adc noise reduction and idle mode. to make use of this feature, the follo w ing procedure should be used: 315 7593l?avr?09/12 at90usb64/128 a. make sure that the adc is enabled and is not busy con v erting. single con v ersion mode must be selected and the adc con v ersion complete interrupt must be enabled. b. enter adc noise reduction mo de (or idle mode). the adc w ill start a con v ersion once the cpu has been halted. c. if no other interrupts occur before the adc con v ersion completes, the adc inter- rupt w ill w ake up the cpu and execute the adc con v ersion complete interrupt routine. if another interrupt w akes up the cpu before the adc con v ersion is com- plete, that interrupt w ill be executed, and an adc con v ersion complete interrupt request w ill be generated w hen the adc con v ersion completes. the cpu w ill remain in acti v e mode until a ne w sleep command is executed. note that the adc w ill not be automatically turned off w hen entering other sleep modes than idle mode and adc noise reduction mode. the user is ad v ised to w rite zero to aden before enter- ing such sleep modes to a v oid excessi v e po w er consumption. if the adc is enabled in such sleep modes and the user w ants to perform differential con v er- sions, the user is ad v ised to s w itch the adc off and on after w aking up from sleep to prompt an extended con v ersion to get a v alid result. 26.7.1 analog input circuitry the analog input circuitry for single ended channels is illustrated in figure 26-8. an analog source applied to adcn is subjected to the pin capacitance and input leakage of that pin, regard- less of w hether that channel is selected as input for the adc. when the channel is selected, the source must dri v e the s/h capacitor through the series resistance (combined resistance in the input path). the adc is optimized for analog signals w ith an output impedance of approximately 10k or less. if such a source is used, the sampling time w ill be negligible. if a source w ith higher imped- ance is used, the sampling time w ill depend on ho w long time the source needs to charge the s/h capacitor, w ith can v ary w idely. the user is recommended to only use lo w impedant sources w ith slo w ly v arying signals, since this minimizes the required charge transfer to the s/h capacitor. if differential gain channels are used, the input circuitry looks some w hat different, although source impedances of a fe w hundred k or less is recommended. signal components higher th an the nyquist frequency (f adc /2) should not be present for either kind of channels, to a v oid distortion from unpredictable signal con v olution. the user is ad v ised to remo v e high frequency components w ith a lo w -pass filter before applying the signals as inputs to the adc. figure 26-8. analog input circuitry. adcn i ih 1..100k c s /h = 14pf v cc /2 i il 316 7593l?avr?09/12 at90usb64/128 26.7.2 analog noise canceling techniques digital circuitry inside and outside the de v ice generates emi w hich might affect the accuracy of analog measurements. if con v ersion accuracy is critical, the noise le v el can be reduced by applying the follo w ing techniques: a. keep analog signal paths as short as possible. make sure analog tracks run o v er the analog ground plane, and keep them w ell a w ay from high-speed s w itching digi- tal tracks. b. the av cc pin on the de v ice should be connected to the digital v cc supply v oltage v ia an lc net w ork as sho w n in figure 26-9 . c. use the adc noise canceler function to reduce induced noise from the cpu. d. if any adc port pins are used as digital outputs, it is essential that these do not s w itch w hile a con v ersion is in progress. figure 26-9. adc po w er connections. 26.7.3 offset compensation schemes the gain stage has a built-in offset cancellation circ uitry that nulls the offset of differential mea- surements as much as possible. the remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. this offset residue can be then subtracted in soft w are from the measurement results. using this kind of soft w are based offset correction, offset on any channel can be reduced belo w one lsb. 26.7.4 adc accuracy definitions an n-bit single-ended adc con v erts a v oltage linearly bet w een gnd and v ref in 2 n steps (lsbs). the lo w est code is read as 0, and the highest code is read as 2 n -1. se v eral parameters describe the de v iation from the ideal beha v ior: vcc gnd 100nf an a log gro u nd pl a ne (adc0) pf0 (adc7) pf7 (adc1) pf1 (adc2) pf2 (adc 3 ) pf 3 (adc4) pf4 (adc5) pf5 (adc6) pf6 aref gnd avcc 52 5 3 54 55 56 57 58 59 60 61 61 62 62 6 3 6 3 64 64 1 51 nc (ad0) pa0 10 h 317 7593l?avr?09/12 at90usb64/128 ? offset: the de v iation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal v alue: 0 lsb figure 26-10. offset error. ? gain error: after adjusting for offset, the gain error is found as the de v iation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb belo w maximum). ideal v alue: 0 lsb figure 26-11. gain error. ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum de v iation of an actual transition compared to an ideal transition for any code. ideal v alue: 0 lsb output code v ref input voltage ideal adc actual adc offset error output code v ref input voltage ideal adc actual adc gain error 318 7593l?avr?09/12 at90usb64/128 figure 26-12. integral non-linearity (inl). ? differential non-linearity (dnl): the maximum de v iation of the actual code w idth (the inter v al bet w een t w o adjacent transitions) from the ideal code w idth (1 lsb). ideal v alue: 0 lsb figure 26-13. differential non- linearity (dnl). ? quantization error: due to the quantization of the input v oltage into a finite number of codes, a range of input v oltages (1 lsb w ide) w ill code to the same v alue. al w ays 0.5 lsb. ? absolute accuracy: the maximum de v iation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal v alue: 0.5 lsb. 26.8 adc conversion result after the con v ersion is complete (adif is high), the con v ersion result can be found in the adc result registers (adcl, adch). output code v ref input voltage ideal adc actual adc inl output code 0x3ff 0x000 0 v ref input voltage dnl 1 l s b 319 7593l?avr?09/12 at90usb64/128 for single ended con v ersion, the result is: w here v in is the v oltage on the selected input pin and v ref the selected v oltage reference (see table 26-3 on page 322 and table 26-4 on page 322 ). 0x000 represents analog ground, and 0x3ff represents the selected reference v oltage minus one lsb. if differential channels are used, the result is: w here v pos is the v oltage on the positi v e input pin, v neg the v oltage on the negati v e input pin, gain the selected gain factor and v ref the selected v oltage reference. the result is presented in t w o?s complement form, from 0x200 (-512d) through 0x1ff (+511d). note that if the user w ants to perform a quick polarity check of the result, it is sufficient to read the msb of the result (adc9 in adch). if the bit is one, the result is negati v e, and if this bit is zero, the result is posi- ti v e. figure 26-14 sho w s the decoding of the differential input range. table 82 sho w s the resulting output codes if the differential input channel pair (adcn - adcm) is selected w ith a reference v oltage of v ref . adc v in 1024 ? v ref -------------------------- = adc v pos v neg ? () gain 512 ?? v ref ------------------------------------------------------------------------ = 320 7593l?avr?09/12 at90usb64/128 figure 26-14. differential measurement range. 0 output code 0x1ff 0x000 v ref differential input voltage (volts) 0x3ff 0x200 - v ref 321 7593l?avr?09/12 at90usb64/128 example 1: ? admux = 0xed (adc3 - adc2, 10 gain, 2.56v reference, left adjusted result) ? voltage on adc3 is 300mv, v oltage on adc2 is 500mv. ? adcr = 512 10 (300 - 500) / 2560 = -400 = 0x270 ?adcl w ill thus read 0x00, and adch w ill read 0x9c. writing zero to adlar right adjusts the result: adcl = 0x70, adch = 0x02. example 2: ? admux = 0xfb (adc3 - adc2, 1 gain, 2.56v reference, left adjusted result) ? voltage on adc3 is 300mv, v oltage on adc2 is 500mv. ? adcr = 512 1 (300 - 500) / 2560 = -41 = 0x029 . ?adcl w ill thus read 0x40, and adch w ill read 0x0a. writing zero to adlar right adjusts the result: adcl = 0x00, adch = 0x29. 26.9 adc register description 26.9.1 admux ? adc multiplexer selection register ? bit 7:6 ? refs1:0: reference selection bits these bits select the v oltage reference for the adc, as sho w n in table 26-3 on page 322 . if these bits are changed during a con v ersion, the change w ill not go in effect until this con v ersion table 26-2. correlation bet w een input v oltage and output codes. v adcn read code corresponding decimal value v adcm + v ref /gain 0x1ff 511 v adcm + 0.999 v ref /gain 0x1ff 511 v adcm + 0.998 v ref /gain 0x1fe 510 ... ... ... v adcm + 0.001 v ref /gain 0x001 1 v adcm 0x000 0 v adcm - 0.001 v ref /gain 0x3ff -1 ... ... ... v adcm - 0.999 v ref /gain 0x201 -511 v adcm - v ref /gain 0x200 -512 bit 76543210 refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 admux read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue 00000000 322 7593l?avr?09/12 at90usb64/128 is complete (adif in adcs ra is set). the internal v oltage reference options may not be used if an external reference v oltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc con v ersion result in the adc data register. write one to adlar to left adjust the result. other w ise, the result is right adjusted. changing the adlar bit w ill affect the adc data register imm ediately, regardless of any ongoing con v er- sions. for a complete description of this bit, see ?adcl and adch ? the adc data register? on page 324 . ? bits 4:0 ? mux4:0: analog channel selection bits the v alue of these bits selects w hich combination of analog inputs are connected to the adc. these bits also select the gain for the differential channels. see table 26-4 for details. if these bits are changed during a con v ersion, the change w ill not go in effect until this con v ersion is complete (adif in adcsra is set). table 26-3. voltage reference selections for adc. refs1 refs0 voltage reference selection 0 0 aref, internal v ref turned off 01av cc w ith external capacitor on aref pin 1 0 reser v ed 1 1 internal 2.56v voltage reference w ith external capacitor on aref pin table 26-4. input channel and gain selections. mux4..0 single ended input positive differenti al input negative differential input gain 00000 adc0 n/a 00001 adc1 00010 adc2 00011 adc3 00100 adc4 00101 adc5 00110 adc6 00111 adc7 323 7593l?avr?09/12 at90usb64/128 26.9.2 adcsra ? adc control and status register a ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by w riting it to zero, the adc is turned off. turning the adc off w hile a con v ersion is in progress, w ill terminate this con v ersion. ? bit 6 ? adsc: adc start conversion in single con v ersion mode, w rite this bit to one to start each con v ersion. in free running mode, w rite this bit to one to start the first con v ersion. the first con v ersion after adsc has been w ritten after the adc has been enabled, or if adsc is w ritten at the same time as the adc is enabled, 01000 n/a (adc0 / adc0 / 10x) 01001 adc1 adc0 10 01010 (adc0 / adc0 / 200x) 01011 adc1 adc0 200 01100 (reser v ed - adc2 / adc2 / 10x) 01101 adc3 adc2 10 01110 (adc2 / adc2 / 200x) 01111 adc3 adc2 200 10000 adc0 adc1 1 10001 (adc1 / adc1 / 1x) 10010 adc2 adc1 1 10011 adc3 adc1 1 10100 adc4 adc1 1 10101 adc5 adc1 1 10110 adc6 adc1 1 10111 adc7 adc1 1 11000 adc0 adc2 1 11001 adc1 adc2 1 11010 (adc2 / adc2 / 1x) 11011 adc3 adc2 1 11100 adc4 adc2 1 11101 adc5 adc2 1 11110 1.1v (v band gap ) n/a 11111 0v (gnd) table 26-4. input channel and gain selections. (continued) mux4..0 single ended input positive differenti al input negative differential input gain bit 76543210 aden adsc adate adif adie adps2 adps1 adps0 adcsra read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue00000000 324 7593l?avr?09/12 at90usb64/128 w ill take 25 adc clock cycles instead of the normal 13. this first con v ersion performs initializa- tion of the adc. adsc w ill read as one as long as a con v ersion is in progress. when the con v ersion is complete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is w ritten to one, auto triggering of the adc is enabled. the adc w ill start a con- v ersion on a positi v e edge of the selected trigger signal. the trigger source is selected by setting the adc trigger select bits, adts in adcsrb. ? bit 4 ? adif: adc interrupt flag this bit is set w hen an adc con v ersion completes and the data registers are updated. the adc con v ersion complete interrupt is executed if the adie bit and the i-bit in sreg are set. adif is cleared by hard w are w hen executing the corresponding interrupt handling v ector. alter- nati v ely, adif is cleared by w riting a logical one to the flag. be w are that if doing a read-modify- write on adcsra, a pending interrupt can be dis abled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is w ritten to one and the i-bit in sreg is set, the adc con v ersion complete inter- rupt is acti v ated. ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the di v ision factor bet w een the xtal frequency and the input clock to the adc. 26.9.3 adcl and adch ? th e adc data register 26.9.3.1 adlar = 0 table 26-5. adc prescaler selections. adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 1 1 1 128 bit 151413121110 9 8 ? ? ? ? ? ? adc9 adc8 adch adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl bit 76543210 read/ w rite rrrrrrrr rrrrrrrr initial v alue00000000 00000000 325 7593l?avr?09/12 at90usb64/128 26.9.3.2 adlar = 1 when an adc con v ersion is complete, the result is found in these t w o registers. if differential channels are used, the result is presented in t w o?s complement form. when adcl is read, the adc data register is not updated unt il adch is read. consequently, if the result is left adjusted and no more than 8-bit precision (7 bit + sign bit for differential input channels) is required, it is sufficient to read adch. other w ise, adcl must be read first, then adch. the adlar bit in admux, and the mu xn bits in admux affect the w ay the result is read from the registers. if adlar is set, the result is left adjusted. if adla r is cleared (default), the result is right adjusted. ? adc9:0: adc conversion result these bits represent the result from the con v ersion, as detailed in ?adc con v ersion result? on page 318 . 26.9.4 adcsrb ? adc control and status register b ? bit 7 ? adhsm: adc high speed mode writing this bit to one enables the adc high speed mode. this mode enables higher con v ersion rate at the expense of higher po w er consumption. ? bit 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is w ritten to one, the v alue of these bits selects w hich source w ill trigger an adc con v ersion. if adate is cleared, the adts2:0 settings w ill ha v e no effect. a con v ersion w ill be triggered by the rising edge of th e selected in terrupt flag. note that s w itching from a trig- ger source that is cleared to a trigger source that is set, w ill generate a positi v e edge on the trigger signal. if aden in adcsra is set, this w ill start a con v ersion. s w itching to free running mode (adts[2:0]=0) w ill not cause a trigger e v ent, e v en if the adc interrupt flag is set . bit 151413121110 9 8 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch adc1 adc0 ? ????? adcl bit 76543210 read/ w rite rrrrrrrr rrrrrrrr initial v alue00000000 00000000 bit 76543210 adhsm acme ? ? ? adts2 adts1 adts0 adcsrb read/ w rite r/w r/w r r r r/w r/w r/w initial v alue 00000000 table 26-6. adc auto trigger so urce selections. adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match 326 7593l?avr?09/12 at90usb64/128 26.9.5 didr0 ? digital in put disable register 0 ? bit 7:0 ? adc7d..adc0d: ad c7:0 digital input disable when this bit is w ritten logic one, the digital input buffer on the corresponding adc pin is dis- abled. the corresponding pin register bit w ill al w ays read as zero w hen this bit is set. when an analog signal is applied to the adc7..0 pin and the digital input from this pin is not needed, this bit should be w ritten logic one to reduce po w er consumption in the digital input buffer. 1 0 0 timer/counter0 o v erflo w 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 o v erflo w 1 1 1 timer/counter1 capture e v ent table 26-6. adc auto trigger source selections. (continued) adts2 adts1 adts0 trigger source bit 76543210 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue 00000000 327 7593l?avr?09/12 at90usb64/128 27. jtag interface and on-chip debug system 27.0.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabilities ac cording to the ieee std. 1149.1 (jtag) standard ? debugger access to: ? all internal peripheral units ? internal and external ram ? the internal register file ? program counter ? eeprom and flash memories ? extensive on-chip debug support for break conditions, including ? avr break instruction ? break on change of program memory flow ? single step break ? program memory break points on single address or address range ? data memory break points on single address or address range ? programming of flash, eeprom , fuses, and lock bits th rough the jtag interface ? on-chip debugging supported by atmel avr studio ? 27.1 overview the avr ieee std. 1149.1 compliant jtag interface can be used for ? testing pcbs by using the jtag boundary-scan capability ? programming the non- v olatile memories, fuses and lock bits ? on-chip debugging a brief description is gi v en in the follo w ing sections. detailed descriptions for programming v ia the jtag interface, and using the boundary-scan chain can be found in the sections ?program- ming v ia the jtag interface? on page 377 and ?ieee 1149.1 (jtag) boundary-scan? on page 333 , respecti v ely. the on-chip debug support is considered being pri v ate jtag instructions, and distributed w ithin atmel and to selected third party v endors only. figure 27-1 on page 328 sho w s a block diagram of the jtag interface and the on-chip debug system. the tap controller is a state machine controlled by the tck and tms signals. the tap controller selects either the jtag instruction register or one of se v eral data registers as the scan chain (shift register) bet w een the tdi ? input and tdo ? output. the instruction register holds jtag instructi ons controlling the beha v ior of a data register. the id-register, bypass register, and the bou ndary-scan chain are the data registers used for board-le v el testing. the jtag programming interface (actually consisting of se v eral physical and v irtual data registers) is used for serial programming v ia the jtag interface. the internal scan chain and break point scan chain are used for on-chip debugging only. 27.2 tap ? test access port the jtag interface is accessed through four of the avr?s pins. in jtag terminology, these pins constitute the test access port ? tap. these pins are: ? tms: test mode select. this pin is used for na v igating through the tap-controller state machine ? tck: test clock. jtag operation is synchronous to tck 328 7593l?avr?09/12 at90usb64/128 ? tdi: test data in. serial input data to be shifted in to the instruction register or data register (scan chains) ? tdo: test data out. serial output data from instruction register or data register the ieee std. 1149.1 also sp ecifies an optional tap signal; trst ? test reset ? w hich is not pro v ided. when the jtagen fuse is unprogrammed, these four tap pins are normal port pins, and the tap controller is in reset. when programmed, the input tap signals are internally pulled high and the jtag is enabled for boundary-scan and programming. the de v ice is shipped w ith this fuse programmed. for the on-chip debug system, in addition to the jtag interface pins, the reset pin is moni- tored by the debugger to be able to detect external reset sources. the debugger can also pull the reset pin lo w to reset the w hole system, assuming only ope n collectors on the reset line are used in the application. figure 27-1. block diagram. tap controller tdi tdo tck tm s fla s h memory avr cpu digital peripheral unit s jtag / avr core communication interface breakpoint unit flow control unit ocd s tatu s and control internal s can chain m u x in s truction regi s ter id regi s ter bypa ss regi s ter jtag programming interface pc instruction address data breakpoint s can chain addre ss decoder analog peripherial unit s i/o port 0 i/o port n boundary s can chain analog inputs control & clock lines device boundary 329 7593l?avr?09/12 at90usb64/128 figure 27-2. tap controller state diagram. 27.3 tap controller the tap controller is a 16-state finite state machine that controls the operation of the boundary- scan circuitry, jtag programming circuitry, or on-chip debug system. the state transitions depicted in figure 27-2 depend on the signal present on tms (sho w n adjacent to each state transition) at the time of the rising edge at tck. the initial state after a po w er-on reset is test- logic-reset. as a definition in this document, the lsb is shifted in and out first for all shift registers. assuming run-test/idle is the present state, a typical scenario for using the jtag interface is: ? at the tms input, apply the sequence 1, 1, 0, 0 at the rising edges of tck to enter the shift instruction register ? shift-ir state. while in this state, shift the four bits of the jtag instructions into the jtag instruction register from the tdi input at the rising edge of tck. the tms input must be held lo w during input of the three lsbs in order to remain in the shift- ir state. the msb of the instruction is shifted in w hen this state is left by setting tms high. while the instruction is shifted in from the tdi pin, the captured ir-state 0x01 is shifted out on the tdo pin. the jtag instruction selects a particular data register as path bet w een tdi and tdo and controls the circuitry surrounding the selected data register te s t-logic-re s et r u n-te s t/idle shift-dr exit1-dr p aus e-dr exit2-dr upd a te-dr select-ir s c a n c a pt u re-ir shift-ir exit1-ir p aus e-ir exit2-ir upd a te-ir select-dr s c a n c a pt u re-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 330 7593l?avr?09/12 at90usb64/128 ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. the instruction is latched onto the parallel output from the shift register path in the update-ir state. the exit-ir, pause-ir, and exit2-ir states are only used for na v igating the state machine ? at the tms input, apply the sequence 1, 0, 0 at the rising edges of tck to enter the shift data register ? shift-dr state. while in th is state, upload the selected data register (selected by the present jtag instruction in the jtag instruction register) from the tdi input at the rising edge of tck. in order to remain in the shift-dr state, the tms input must be held lo w during input of all bits except the msb. the msb of the data is shifted in w hen this state is left by setting tms high. while the data register is shifted in from the tdi pin, the parallel inputs to the data register captured in the capture-dr state is shifted out on the tdo pin ? apply the tms sequence 1, 1, 0 to re-enter the run-test/idle state. if the selected data register has a latched parallel-output, the latching takes place in the update-dr state. the exit-dr, pause-dr, and exit2-dr states are only used for na v igating the state machine as sho w n in the state diagram, the run-test/idle state need not be entered bet w een selecting jtag instruction and using data registers, and some jtag instructions may select certain functions to be performed in the run-test/idle, making it unsuitable as an idle state. note: independent of the initial state of the tap controller, the test-log ic-reset state can al w ays be entered by holding tms high for fi v e tck clock periods. for detailed information on the jtag specification, refer to the literature listed in ?bibliography? on page 332 . 27.4 using the b oundary-scan chain a complete description of the boundary-scan capa bilities are gi v en in the section ?ieee 1149.1 (jtag) boundary-scan? on page 333 . 27.5 using the on -chip debug system as sho w n in figure 27-1 on page 328 , the hard w are support for on-chip debugging consists mainly of ? a scan chain on the interface bet w een the internal avr cpu and the internal peripheral units ? break point unit ? communication interface bet w een the cpu and jtag system all read or modify/ w rite operations needed for implementing the debugger are done by applying avr instructions v ia the internal avr cpu scan chain. the cpu sends the result to an i/o memory mapped location w hich is part of the communication interface bet w een the cpu and the jtag system. the break point unit implements break on change of program flo w , single step break, t w o program memory break points, and t w o combined break points. together, the four break points can be configured as either: ? four single program memory break points ? three single program memory break point + one single data memory break point ?t w o single program memory break points + t w o single data memory break points ?t w o single program memory break points + one program memory break point w ith mask (?range break point?) 331 7593l?avr?09/12 at90usb64/128 ?t w o single program memory break points + one data memory break point w ith mask (?range break point?) a debugger, like the atmel avr studio, may ho w e v er use one or more of these resources for its internal purpose, lea v ing less flexibility to the end-user. a list of the on-chip debug spec ific jtag instructions is gi v en in ?on-chip debug specific jtag instructions? on page 331 . the jtagen fuse must be programmed to enable the jtag test access port. in addition, the ocden fuse must be programmed and no lock bits must be set for the on-chip debug system to w ork. as a security feature, the on-chip debug system is disabled w hen either of the lb1 or lb2 lock bits are set. other w ise, the on-chip debug system w ould ha v e pro v ided a back-door into a secured de v ice. the avr studio enables the user to fully control execution of programs on an avr de v ice w ith on-chip debug capability, avr in- circuit emulator, or the built-i n avr instruction set simulator. avr studio supports source le v el execution of assembly programs assembled w ith atmel cor- poration?s avr assembler and c programs compiled w ith third party v endors? compilers. avr studio runs under microsoft ? windo w s ? 95/98/2000 and microsoft windo w s nt. for a full description of the atmel avr studio, please refer to the avr studio user guide. only highlights are presented in this document. all necessary execution commands are a v ailable in avr studio, both on source le v el and on disassembly le v el. the user can execute the program, single step through the code either by tracing into or stepping o v er functions, step out of functions, place the cursor on a statement and execute until the statement is reached, stop th e execution, and reset the execution target. in addition, the user can ha v e an unlimited number of code break points (using the break instruction) and up to t w o data memory break points, alternati v ely combined as a mask (range) break point. 27.6 on-chip debug specific jtag instructions the on-chip debug support is considered being pri v ate jtag instructions, and distributed w ithin atmel and to selected third party v endors only. instruction opcodes are listed for reference. 27.6.1 private0; 0x8 pri v ate jtag instruction for accessing on-chip debug system. 27.6.2 private1; 0x9 pri v ate jtag instruction for accessing on-chip debug system. 27.6.3 private2; 0xa pri v ate jtag instruction for accessing on-chip debug system. 27.6.4 private3; 0xb pri v ate jtag instruction for accessing on-chip debug system. 332 7593l?avr?09/12 at90usb64/128 27.7 on-chip debug related register in i/o memory 27.7.1 ocdr ? on-chi p debug register the ocdr register pro v ides a communication channel from the running program in the micro- controller to the debugger. the cpu can transfer a byte to the debugger by w riting to this location. at the same time, an in ternal flag; i/o debug register dirty ? idrd ? is set to indicate to the debugger that the register has been w ritten. when the cpu reads the ocdr register the se v en lsb w ill be from the ocdr register, w hile the msb is the idrd bit. the debugger clears the idrd bit w hen it has read the information. in some avr de v ices, this register is shared w ith a standard i/o location. in this case, the ocdr register can only be accessed if the ocden fuse is programmed, and the debugger enables access to the ocdr register. in all other cases, the standard i/o location is accessed. refer to the debugger documentation for further information on ho w to use this register. 27.8 using the jtag pr ogramming capabilities programming of avr parts v ia jtag is performed v ia the 4-pin jtag port, tck, tms, tdi, and tdo. these are the only pins that need to be controlled/obser v ed to perform jtag program- ming (in addition to po w er pins). it is not required to apply 12v externally. the jtagen fuse must be programmed and the jtd bit in the mcucr register must be cleared to enable the jtag test access port. the jtag programmi ng capability supports: ? flash programming and v erifying ? eeprom programming and v erifying ? fuse programming and v erifying ? lock bit programming and v erifying the lock bit security is exactly as in parallel programming mode. if the lock bits lb1 or lb2 are programmed, the ocden fuse cannot be programmed unless first doing a chip erase. this is a security feature that ensures no back-door exists for reading out the content of a secured de v ice. the details on programming through the jtag interface and programming specific jtag instructions are gi v en in the section ?programming v ia the jtag interface? on page 377 . 27.9 bibliography for more information about general boundary-scan, the follo w ing literature can be consulted: ? ieee: ieee std. 1149.1-1 990. ieee standard test acce ss port and boundary-scan architecture, ieee, 1993. ? colin maunder: the board designers guide to testable logic circuits, addison-wesley, 1992. bit 7 6543210 msb/idrd lsb ocdr read/ w rite r/w r/w r/w r/w r/w r/w r/w r/w initial v alue0 0000000 333 7593l?avr?09/12 at90usb64/128 28. ieee 1149.1 (jtag) boundary-scan 28.1 features ? jtag (ieee std. 1149.1 compliant) interface ? boundary-scan capabili ties according to the jtag standard ? full scan of all port functions as well as analog ci rcuitry having o ff-chip connections ? supports the optional idcode instruction ? additional public avr_reset in struction to reset the avr 28.2 system overview the boundary-scan chain has the capability of dri v ing and obser v ing the logic le v els on the digi- tal i/o pins, as w ell as the boundary bet w een digital and analog logic for analog circuitry ha v ing off-chip connections. at system le v el, all ics ha v ing jtag capabilities are connected serially by the tdi/tdo signals to form a long shift regist er. an external controller sets up the de v ices to dri v e v alues at their output pins, and obser v e the input v alues recei v ed from other de v ices. the controller compares the recei v ed data w ith the expected result. in this w ay, boundary-scan pro- v ides a mechanism for testing interconnections and integrity of components on printed circuits boards by using the four tap signals only. the four ieee 1149.1 defined mandatory jtag in structions idcode, bypass, sample/pre- load, and extest, as w ell as the avr specific public jt ag instruction avr_reset can be used for testing the printed circuit board. initial scanning of the data register path w ill sho w the id-code of the de v ice, since idcode is the default jtag instruction. it may be desirable to ha v e the avr de v ice in reset during test mode. if not reset, inputs to the de v ice may be deter- mined by the scan operations, and the internal soft w are may be in an undetermined state w hen exiting the test mode. entering reset, the outputs of any port pin w ill instantly enter the high impedance state, making the highz instruction redundant. if needed, the bypass instruction can be issued to make the shortest possible scan chain through the de v ice. the de v ice can be set in the reset state either by pulling the external reset pin lo w , or issuing the avr_reset instruction w ith appropriate setting of the reset data register. the extest instruction is used for sampling external pins and loading output pins w ith data. the data from the output latch w ill be dri v en out on the pins as soon as the extest instruction is loaded into the jtag ir-register. therefore, the sample/preload should also be used for setting initial v alues to the scan ring, to a v oid damaging the board w hen issuing the extest instruction for the first time. sample/preload c an also be used for taking a snapshot of the external pins during normal operation of the part. the jtagen fuse must be pr ogrammed and the jtd bit in the i/o register mcucr must be cleared to enable the jtag test access port. when using the jtag interface for boundary-scan, using a jtag tck clock frequency higher than the internal chip frequency is possible. the chip clock is not required to run. 28.3 data registers the data registers rele v ant for boundary-scan operations are: ? bypass register ?de v ice identification register ? reset register ? boundary-scan chain 334 7593l?avr?09/12 at90usb64/128 28.3.1 bypass register the bypass register consists of a single shift register stage. when the bypass register is selected as path bet w een tdi and tdo, the register is reset to 0 w hen lea v ing the capture-dr controller state. the bypass register can be used to shorten the scan chain on a system w hen the other de v ices are to be tested. 28.3.2 device identification register figure 28-1 sho w s the structure of the de v ice identification register. figure 28-1. the format of the de v ice identification register. 28.3.2.1 version version is a 4-bit number identifying the re v ision of the component. the jtag v ersion number follo w s the re v ision of the de v ice. re v ision a is 0x0, re v ision b is 0x1 and so on. 28.3.2.2 part number the part number is a 16-bit code identifying the component. the jtag part number for atmel at90usb64/128 is listed in table 28-1 . 28.3.2.3 manufacturer id the manufacturer id is a 11-bit code identifying the manufacturer. the jtag manufacturer id for atmel is listed in table 28-2 . 28.3.3 reset register the reset register is a test data register used to reset the part. since the avr tri-states port pins w hen reset, the reset register can also replace the function of the un-implemented optional jtag instruction highz. a high v alue in the reset register corresponds to pulling the external reset lo w . the part is reset as long as there is a high v alue present in the reset register. depending on the fuse set- tings for the clock options, the part w ill remain reset for a reset time-out period (refer to ?clock sources? on page 41 ) after releasing the reset register. the output from this data register is not latched, so the reset w ill take place immediately, as sho w n in figure 28-2 on page 335 . msb lsb bit 31 28 27 12 11 1 0 de v ice id version part number manufacturer id 1 4 bits 16 bits 11 bits 1-bit table 28-1. avr jtag part number. part number jtag part number (hex) avr usb 0x9782 table 28-2. manufacturer id. manufacturer jtag manufacturer id (hex) at m e l 0 x 0 1 f 335 7593l?avr?09/12 at90usb64/128 figure 28-2. reset register. 28.3.4 boundary-scan chain the boundary-scan chain has the capability of dri v ing and obser v ing the logic le v els on the dig- ital i/o pins, as w ell as the boundary bet w een digital and analog logic for analog circuitry ha v ing off-chip connections. see ?boundary-scan chain? on page 337 for a complete description. 28.4 boundary-scan specific jtag instructions the instruction register is 4-bit w ide, supporting up to 16 in structions. listed belo w are the jtag instructions useful for boundary-scan operation. note that the optional highz instruction is not implemented, but all outputs w ith tri-state capability can be set in high-impedant state by using the avr_reset instruction, since the initial state for all port pins is tri-state. as a definition in this datasheet, the lsb is shifted in and out first for all shift registers. the opcode for each instruction is sho w n behind the instruction name in hex format. the text describes w hich data register is selected as path bet w een tdi and tdo for each instruction. 28.4.1 extest; 0x0 mandatory jtag instruction for selecting the boundary-scan chain as data register for testing circuitry external to the avr package. for port- pins, pull-up disable, output control, output data, and input data are all accessible in the scan chain. for analog circuits ha v ing off-chip connections, the interface bet w een the analog and the digital logic is in the scan chain. the con- tents of the latched outputs of the boundary-scan chain is dri v en out as soon as the jtag ir- register is loaded w ith the extest instruction. the acti v e states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain ? shift-dr: the internal scan chain is shifted by the tck input ? update-dr: data from the scan chain is applied to output pins 28.4.2 idcode; 0x1 optional jtag instruction selecting the 32-bit id-register as data register. the id-register consists of a v ersion number, a de v ice number and the manufacturer code chosen by jedec. this is the default instruction after po w er-up. dq from tdi clockdr avr_reset to tdo from other intern a l a nd extern a l re s et s o u rce s intern a l re s et 336 7593l?avr?09/12 at90usb64/128 the acti v e states are: ? capture-dr: data in the idcode register is sampled into the boundary-scan chain ? shift-dr: the idcode scan chain is shifted by the tck input 28.4.3 sample_preload; 0x2 mandatory jtag instruction for pre-loading the output latches and taking a snap-shot of the input/output pins w ithout affecting the system operation. ho w e v er, the output latches are not connected to the pins. the boundary-scan chain is selected as data register. the acti v e states are: ? capture-dr: data on the external pins are sampled into the boundary-scan chain ? shift-dr: the boundary-scan chain is shifted by the tck input ? update-dr: data from the boundary-scan chain is applied to the output latches. ho w e v er, the output latches are not connected to the pins 28.4.4 avr_reset; 0xc the avr specific public jtag instruction for forcing the avr de v ice into the reset mode or releasing the jtag reset source. the tap controller is not reset by this in struction. the one bit reset register is selected as data register. note that the reset w ill be acti v e as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the acti v e states are: ? shift-dr: the reset register is shifted by the tck input 28.4.5 bypass; 0xf mandatory jtag instructio n selecting the bypass register for data register. the acti v e states are: ? capture-dr: loads a logic ?0? into the bypass register ? shift-dr: the bypass register cell bet w een tdi and tdo is shifted 28.5 boundary-scan related re gister in i/o memory 28.5.1 mcucr ? mcu control register the mcu control register contains control bits for general mcu functions. ? bits 7 ? jtd: jtag interface disable when this bit is zero, the jtag interface is ena bled if the jtagen fuse is programmed. if this bit is one, the jtag interface is disabled. in order to a v oid unintentional disabling or enabling of the jtag interface, a timed sequence must be follo w ed w hen changing this bit: the application soft w are must w rite this bit to the desired v alue t w ice w ithin four cycles to change its v alue. note that this bit must not be altered w hen using the on-chip debug system. bit 76543210 jtd ? ? pud ? ? ivsel ivce mcucr read/ w rite r/w r r r/w r r r/w r/w initial v alue00000000 337 7593l?avr?09/12 at90usb64/128 28.5.2 mcusr ? mcu status register the mcu status register pro v ides information on w hich reset source caused an mcu reset. ? bit 4 ? jtrf: jtag reset flag this bit is set if a reset is being caused by a logic one in the jtag reset register selected by the jtag instruction avr_reset. this bit is reset by a po w er-on reset, or by w riting a logic zero to the flag. 28.6 boundary-scan chain the boundary-scan chain has the capability of dri v ing and obser v ing the logic le v els on the digi- tal i/o pins, as w ell as the boundary bet w een digital and analog logic for analog circuitry ha v ing off-chip connection. 28.6.1 scanning the digital port pins figure 28-3 on page 338 sho w s the boundary-scan cell for a bi-directional port pin. the pull-up function is disabled during boundary-scan w hen the jtag ic contains extest or sample_preload. the cell consists of a bi-dir ectional pin cell that combines the three sig- nals output control - ocxn, output data - odxn, and input data - idxn, into only a t w o-stage shift register. the port and pin indexes are not used in the follo w ing description the boundary-scan logic is not included in the figures in the datasheet. figure 28-4 on page 339 sho w s a simple digital port pin as described in the section ?i/o-ports? on page 71 . the boundary- scan details from figure 28-3 on page 338 replaces the dashed box in figure 28-4 on page 339 . when no alternate port function is present, the input data - id - corresponds to the pinxn regis- ter v alue (but id has no synchronizer), output data corresponds to the port register, output control corresponds to the data direction - dd register, and the pull-up enable - puexn - cor- responds to logic expression pud ddxn portxn. digital alternate port functions are connected outside the dotted box in figure 28-4 on page 339 to make the scan chain read the actual pin v alue. for analog function, there is a direct connec- tion from the external pin to the analog circuit. there is no scan chain on the interface bet w een the digital and the analog circuitry, but some digi tal control signal to analog circuitry are turned off to a v oid dri v ing contention on the pads. when jtag ir contains extest or sample_preload the clock is not sent out on the port pins e v en if the ckout fuse is programmed. e v en though the clock is output w hen the jtag ir contains sample_preload, the clock is not sampled by the boundary scan. bit 76543210 ? ? ?jtrf wdrf borf extrf porf mcusr read/ w rite r r r r/w r/w r/w r/w r/w initial v alue 0 0 0 see bit description 338 7593l?avr?09/12 at90usb64/128 figure 28-3. boundary-scan cell for bi-directional port pin w ith pull-up function. dq dq g 0 1 0 1 dq dq g 0 1 0 1 0 1 port pin (pxn) vcc extest to next cell shiftdr o u tp u t control (oc) o u tp u t d a t a (od) inp u t d a t a (id) from l as t cell upd a tedr clockdr ff1 ld1 ld0 ff0 0 1 p u ll- u p en ab le (pue) 339 7593l?avr?09/12 at90usb64/128 figure 28-4. general port pin schematic diagram. 28.6.2 scanning the reset pin the reset pin accepts 5v acti v e lo w logic for standard reset operation, and 12v acti v e high logic for high voltage para llel programming. an obser v e-only cell as sho w n in figure 28-5 is inserted for the 5v reset signal. figure 28-5. obser v e-only cell. clk rpx rrx wrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk : i/o clock rdx: read ddrx d l q q reset reset q q d q q d clr portxn q q d clr ddxn pinxn data b u s sleep sleep: sleep control pxn i/o i/o see bo u nd a ry- s c a n de s cription for det a il s ! puexn ocxn odxn idxn puexn: pullup enable for pin pxn ocxn: output control for pin pxn odxn: output data to pin pxn idxn: input data from pin pxn 0 1 dq from previo us cell clockdr shiftdr to next cell from s y s tem pin to s y s tem logic ff1 340 7593l?avr?09/12 at90usb64/128 28.7 atmel at90usb64/ 128 boundary-scan order table 28-3 sho w s the scan order bet w een tdi and tdo w hen the boundary-scan chain is selected as data path. bit 0 is the lsb; the first bit scanned in, and the first bit scanned out. the scan order follo w s the pin-out order as far as possible. therefore, the bits of port a and port fis scanned in the opposite bit order of the other ports. exceptions from the rules are the scan chains for the analog circuits, w hich constitute the most significant bits of the scan chain regard- less of w hich physical pin they are connected to. in figure 28-3 on page 338 , pxn. data corresponds to ff0, pxn. control corresponds to ff1, pxn. bit 4, 5, 6 and 7 of port f is not in the scan chain, since these pins constitute the tap pins w hen the jtag is enabled. the usb pads are not included in the boundary-scan. table 28-3. at90usb64/128 boundary-scan order. bit number signal name module 88 pe6.data port e 87 pe6.control 86 pe7.data 85 pe7.control 84 pe3.data 83 pe3.control 82 pb0.data port b 81 pb0.control 80 pb1.data 79 pb1.control 78 pb2.data 77 pb2.control 76 pb3.data 75 pb3.control 74 pb4.data 73 pb4.control 72 pb5.data 71 pb5.control 70 pb6.data 69 pb6.control 68 pb7.data 67 pb7.control 66 pe4.data porte 65 pe4.control 64 pe5.data 63 pe5.control 62 rstt reset logic (obser v e only) 341 7593l?avr?09/12 at90usb64/128 61 pd0.data port d 60 pd0.control 59 pd1.data 58 pd1.control 57 pd2.data 56 pd2.control 55 pd3.data 54 pd3.control 53 pd4.data 52 pd4.control 51 pd5.data 50 pd5.control 49 pd6.data 48 pd6.control 47 pd7.data 46 pd7.control 45 pe0.data port e 44 pe0.control 43 pe1.data 42 pe1.control 41 pc0.data port c 40 pc0.control 39 pc1.data 38 pc1.control 37 pc2.data 36 pc2.control 35 pc3.data 34 pc3.control 33 pc4.data 32 pc4.control 31 pc5.data 30 pc5.control 29 pc6.data 28 pc6.control 27 pc7.data 26 pc7.control table 28-3. at90usb64/128 boundary-scan order. (continued) bit number signal name module 342 7593l?avr?09/12 at90usb64/128 28.8 boundary-scan descripti on language files boundary-scan description language (bsdl) files describe boundary-scan capable de v ices in a standard format used by automated test-generation soft w are. the order and function of bits in the boundary-scan data register are included in this description. bsdl files are a v ailable for atmel at90usb64/128. 25 pe2.data port e 24 pe2.control 23 pa7.data port a 22 pa7.control 21 pa6.data 20 pa6.control 19 pa5.data 18 pa5.control 17 pa4.data 16 pa4.control 15 pa3.data 14 pa3.control 13 pa2.data 12 pa2.control 11 pa1.data 10 pa1.control 9pa0.data 8 pa0.control 7pf3.data port f 6 pf3.control 5pf2.data 4 pf2.control 3pf1.data 2 pf1.control 1pf0.data 0 pf0.control table 28-3. at90usb64/128 boundary-scan order. (continued) bit number signal name module 343 7593l?avr?09/12 at90usb64/128 29. boot loader support ? read -while-write self-programming the boot loader support pro v ides a real read-while-write self-programming mechanism for do w nloading and uploading program code by the mcu itself. this feature allo w s flexible applica- tion soft w are updates controlled by the mcu using a flash-resident boot loader program. the boot loader program can use any a v ailable data interface and associated protocol to read code and w rite (program) that code into the flash memory, or read the code from the program mem- ory. the program code w ithin the boot loader section has the capability to w rite into the entire flash, including the boot loader me mory. the boot loader can thus e v en modify itself, and it can also erase itself from the code if the feature is not needed anymore. the size of the boot loader memory is configurable w ith fuses and the boot loader has t w o separate sets of boot lock bits w hich can be set independently. this gi v es the user a unique flex ibility to select differ- ent le v els of protection. general information on spm and elpm is pro v ided in see ?avr cpu core? on page 11. 29.1 boot loader features ? read-while-write self-programming ? flexible boot memory size ? high security (separat e boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modify-write support note: 1. a page is a section in the flash consisting of se v eral bytes (see table 30-11 on page 364 ) used during programming. the page organiz ation does not affect normal operation. 29.2 application and bo ot loader flash sections the flash memory is organized in t w o main sections, the application section and the boot loader section (see figure 29-2 on page 346 ). the size of the different sections is configured by the bootsz fuses as sho w n in table 29-8 on page 357 and figure 29-2 on page 346 . these t w o sections can ha v e different le v el of protection since they ha v e different sets of lock bits. 29.2.1 application section the application section is the section of the flash that is used for storing the application code. the protection le v el for the application section can be selected by the application boot lock bits (boot lock bits 0), see table 29-2 on page 347 . the application section can ne v er store any boot loader code since the spm instruction is disabled w hen executed from the application section. 29.2.2 bls ? boot loader section while the application section is used for storing the application code, the the boot loader soft- w are must be located in the bls since the spm instruction can initiate a programming w hen executing from the bls only. the spm instruct ion can access the entire flash, including the bls itself. the protection le v el for the boot loader section can be selected by the boot loader lock bits (boot lock bits 1), see table 29-3 on page 347 . 29.3 read-while-write and no read- while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader soft- w are update is dependent on w hich address that is being programmed. in addition to the t w o 344 7593l?avr?09/12 at90usb64/128 sections that are configurable by the bootsz fuses as described abo v e, the flash is also di v ided into t w o fixed sections, the read-while-write (rww) section and the no read-while- write (nrww) section. the limit bet w een the rww- and nrww sections is gi v en in table 29- 1 and figure 29-1 on page 345 . the main difference bet w een the t w o sections is: ? when erasing or w riting a page located inside the rww section, the nrww section can be read during the operation ? when erasing or w riting a page located inside the nr ww section, the cpu is halted during the entire operation note that the user soft w are can ne v er read any code that is located inside the rww section dur- ing a boot loader soft w are operation. the syntax ?read-while-write section? refers to w hich section that is being programmed (erased or w ritten), not w hich section that actually is being read during a boot loader soft w are update. 29.3.1 rww ? read-while-write section if a boot loader soft w are update is programming a page inside the rww section, it is possible to read code from the flash, but only code that is located in the nrww section. during an on- going programming, the soft w are must ensure that the rww section ne v er is being read. if the user soft w are is trying to read code that is located inside the rww section (i.e., by load program memory, call, or jump instructions or an interrupt) during programming, the soft w are might end up in an unkno w n state. to a v oid this, the interrupts should either be disabled or mo v ed to the boot loader section. the boot loader section is al w ays located in the nrww section. the rww section busy bit (rwwsb) in the store program memory control and status register (spmcsr) w ill be read as logical one as long as the rww section is blocked for reading. after a programming is completed, the rwwsb must be cleared by soft w are before reading code located in the rww section. see ?spmcsr ? store program memory control and status reg- ister? on page 349. for details on ho w to clear rwwsb. 29.3.2 nrww ? no read-while-write section the code located in the nrww section can be read w hen the boot loader soft w are is updating a page in the rww section. when the boot loader code updates the nrww section, the cpu is halted during the entire page erase or page write operation. table 29-1. read-while-write features. which section does the z- pointer address during the programming? which section can be read during programming? is the cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no 345 7593l?avr?09/12 at90usb64/128 figure 29-1. read-while-write v s. no read-while-write. re a d-while-write (rww) s ection no re a d-while-write (nrww) s ection z-pointer addre ss e s rww s ection z-pointer a ddre ss e s nrww s ection cpu i s h a lted d u ring the oper a tion code loc a ted in nrww s ection. c a n b e re a d d u ring the oper a tion 346 7593l?avr?09/12 at90usb64/128 figure 29-2. memory sections. note: 1. the parameters in the figure abo v e are gi v en in table 29-8 on page 357 . 29.4 boot loader lock bits if no boot loader capability is needed, the entir e flash is a v ailable for application code. the boot loader has t w o separate sets of boot lock bits w hich can be set independently. this gi v es the user a unique flexibilit y to select different le v els of protection. the user can select: ? to protect the entire flash from a soft w are update by the mcu ? to protect only the boot loader flash section from a soft w are update by the mcu ? to protect only the application flash section from a soft w are update by the mcu ? allo w soft w are update in the entire flash see table 29-2 on page 347 and table 29-3 on page 347 for further details. the boot lock bits can be set by soft w are and in serial or in parallel programming mode. they can only be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the programming of the flash memory by spm instru ction. similarly, the general read/write lock (lock bit mode 1) does not control reading nor w riting by (e)lpm/spm, if it is attempted. 0x0000 fl as hend pro g ram memory boot s z = '11' applic a tion fl as h s ection boot lo a der fl as h s ection fl as hend pro g ram memory boot s z = '10' 0x0000 pro g ram memory boot s z = '01' pro g ram memory boot s z = '00' applic a tion fl as h s ection boot lo a der fl as h s ection 0x0000 fl as hend applic a tion fl as h s ection fl as hend end rww st a rt nrww applic a tion fl as h s ection boot lo a der fl as h s ection boot lo a der fl as h s ection end rww st a rt nrww end rww st a rt nrww 0x0000 end rww, end a pplic a tion st a rt nrww, s t a rt b oot lo a der applic a tion fl as h s ection applic a tion fl as h s ection applic a tion fl as h s ection re a d-while-write s ection no re a d-while-write s ection re a d-while-write s ection no re a d-while-write s ection re a d-while-write s ection no re a d-while-write s ection re a d-while-write s ection no re a d-while-write s ection end a pplic a tion st a rt b oot lo a der end a pplic a tion st a rt b oot lo a der end a pplic a tion st a rt b oot lo a der 347 7593l?avr?09/12 at90usb64/128 note: 1. ?1? means unprogrammed, ?0? means programmed . note: 1. ?1? means unprogrammed, ?0? means programmed. 29.5 entering the b oot loader program the boot loader can be executed w ith three different conditions: 29.5.1 regular application conditions. a jump or call from the application program. this may be initiated by a trigger such as a com- mand recei v ed v ia usart, spi or usb. 29.5.2 boot reset fuse the boot reset fuse (bootrst) can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the application code is loaded, the program can start executing the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is programmed, the reset vector w ill al w ays point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. table 29-2. boot lock bit0 protection modes (application section) (1) . blb0 mode blb02 blb01 protection 111 no restrictions for spm or (e)lpm accessing the application section. 2 1 0 spm is not allo w ed to w rite to the application section. 300 spm is not allo w ed to w rite to the application section, and (e)lpm executing from the boot loader section is not allo w ed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled w hile executing from the application section. 401 (e)lpm executing from the boot loader section is not allo w ed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled w hile executing from the application section. table 29-3. boot lock bit1 protection modes (boot loader section) (1) . blb1 mode blb12 blb11 protection 111 no restrictions for spm or (e)lpm accessing the boot loader section. 2 1 0 spm is not allo w ed to w rite to the boot loader section. 300 spm is not allo w ed to w rite to the boot loader section, and (e)lpm executing from t he application section is not allo w ed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled w hile executing from the boot loader section. 401 (e)lpm executing from the application section is not allo w ed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled w hile executing from the boot loader section. 348 7593l?avr?09/12 at90usb64/128 note: 1. ?1? means unprogrammed, ?0? means programmed. 29.5.3 external hardware conditions the hard w are boot enable fuse (hwbe) can be programmed (see table 29-5 ) so that upon special hard w are conditions under reset, the boot loader execution is forced after reset. note: 1. ?1? means unprogrammed, ?0? means programmed. when the hwbe fuse is enable the ale/hwb pin is configured as input during reset and sam- pled during reset rising edge. when ale/hwb pin is ?0? during reset rising edge, the reset v ector w ill be set as the boot loader re set address and the boot loader w ill be executed (see figure 29-3 ). figure 29-3. boot process description. table 29-4. boot reset fuse (1) . bootrst reset address 1 reset vector = applicat ion reset (address 0x0000) 0 reset vector = boot loader reset (see table 29-8 on page 357 ) table 29-5. hard w are boot enable fuse (1) . hwbe reset address 1ale/hwb pin can not be used to force boot loader execution after reset 0ale/hwb pin is used during reset to force boot loader execution after reset hwbe bootrst ? ext. hardware conditions ? reset vector = application reset reset vector = boot loader reset ? reset ale/hwb t shrh t hhrh 349 7593l?avr?09/12 at90usb64/128 29.5.4 spmcsr ? store program memory control and status register the store program memory control and status register contains the control bits needed to con- trol the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is w ritten to one, and the i-bit in the status register is set (one), the spm ready interrupt w ill be enabled. the spm ready interrupt w ill be executed as long as the spmen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the rww section is initi- ated, the rwwsb w ill be set (one) by hard w are. when the rwwsb bit is set, the rww section cannot be accessed. the rwwsb bit w ill be cleared if the rwwsre bit is w ritten to one after a self-programming operation is completed. alternati v ely the rwwsb bit w ill automatically be cleared if a page load operation is initiated. ? bit 5 ? sigrd: signature row read if this bit is w ritten to one at the same time as spmen, the next lpm instruction w ithin three clock cycles w ill read a byte from the signature ro w into the destination register. see ?reading the signature ro w from soft w are? on page 354 for details. an spm instruction w ithin four cycles after sigrd and spmen are set w ill ha v e no effect. this operation is reser v ed for future use and should not be used. ? bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb w ill be set by hard w are). to re-enable the rww section, the user soft w are must w ait until the programming is completed (spmen w ill be cleared). then, if the rwwsre bit is w ritten to one at the same time as spmen, the next spm instruction w ithin four clock cycles re-enables the rww se ction. the rww section cannot be re-enabled w hile the flash is busy w ith a page erase or a page write (spmen is set). if the rwwsre bit is w rit- ten w hile the flash is being loaded, the flash load operation w ill abort and the data loaded w ill be lost. ? bit 3 ? blbset: boot lock bit set if this bit is w ritten to one at the same time as spmen, the next spm instruction w ithin four clock cycles sets boot lock bits, according to the data in r0. the data in r1 and the address in the z- pointer are ignored. the blbset bit w ill automatically be cleared upon completion of the lock bit set, or if no spm instruction is executed w ithin four clock cycles. an (e)lpm instruction w ithin three cycles after blbset and spmen are set in the spmcsr register, w ill read either the lock bits or the fuse bits (depending on z0 in th e z-pointer) into the destination register. see ?reading the fuse and lock bits from soft w are? on page 353 for details. bit 7 6 5 4 3 2 1 0 spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen spmcsr read/ w rite r/w r r/w r/w r/w r/w r/w r/w initial v alue 0 0 0 0 0 0 0 0 350 7593l?avr?09/12 at90usb64/128 ? bit 2 ? pgwrt: page write if this bit is w ritten to one at the same time as spmen, the next spm instruction w ithin four clock cycles executes page write, w ith the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit w ill auto-clear upon comp letion of a page write, or if no spm instruction is executed w ithin four clock cycles. the cpu is halted during the ent ire page write operation if the nrww section is addressed. ? bit 1 ? pgers: page erase if this bit is w ritten to one at the same time as spmen, the next spm instruction w ithin four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bit w ill auto-clear upon comple tion of a page erase, or if no spm instruction is executed w ithin four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 0 ? spmen: store program memory enable this bit enables the spm instruction for the next four clock cycles. if w ritten to one together w ith either rwwsre, blbset, pgwrt? or pgers, the follo w ing spm instruction w ill ha v e a spe- cial meaning, see description abo v e. if only spmen is w ritten, the follo w ing spm instruction w ill store the v alue in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is ignored. the spmen bit w ill auto-clear upon completion of an spm instruction, or if no spm instruction is executed w ithin four clock cycles. during page erase and page write, the spmen bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lo w er fi v e bits w ill ha v e no effect. note: only one spm instruction should be acti v e at any time. 29.6 addressing the flash during self-programming the z-pointer is used to address the spm commands. the z pointer consists of the z-registers zl and zh in the register file, and rampz in the i/o space. the number of bits actually used is implementation dependent. note that the rampz register is only implemented w hen the pro- gram space is larger than 64kbytes. since the flash is organized in pages (see table 30-11 on page 364 ), the program counter can be treated as ha v ing t w o different sections. one section, consisting of the least significant bits, is addressing the w ords w ithin a page, w hile the most significant bits are addressing the pages. this is sho w n in figure 29-4 on page 351 . note that the page erase and page write operations are addressed independently. therefore it is of major importance that the boot loader soft w are addresses the same page in both the page erase and page write operation. once a program- ming operation is initiated, the address is latched and the z-pointer can be used for other operations. the (e)lpm instruction use the z-pointer to st ore the address. since this instruction addresses the flash byte-by-byte, also bit z0 of the z-pointer is used. bit 2322212019181716 15 14 13 12 11 10 9 8 rampz rampz7 rampz6 rampz5 rampz4 rampz3 rampz2 rampz1 rampz0 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30)z7z6z5z4z3z2z1z0 76543210 351 7593l?avr?09/12 at90usb64/128 figure 29-4. addressing the flash during spm (1) . note: 1. the different v ariables used in figure 29-4 are listed in table 29-10 on page 358 . 29.7 self-programming the flash the program memory is updated in a page by page fashion. before programming a page w ith the data stored in the temporary page buffer, the page must be erased. the temporary page buf- fer is filled one w ord at a time using spm and the buffer can be filled either before the page erase command or bet w een a page erase and a page write operation: alternati v e 1, fill the buffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternati v e 2, fill the buffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be re w ritten. when using alternati v e 1, the boot loader pro v ides an effecti v e read-modify-write feature w hich allo w s the user soft w are to first read the page, do the necessary changes, and then w rite back the modified data. if alter- nati v e 2 is used, it is not possible to read the old data w hile loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase and page write operation is addressing the same program memory 0 1 23 z - pointer bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word page pcword[pagemsb:0]: 00 01 02 pageend page pcword pcpage pcmsb pagemsb program counter 352 7593l?avr?09/12 at90usb64/128 page. see ?simple assembly code example for a boot loader? on page 355 for an assembly code example. 29.7.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, w rite ?x0000011? to spmcsr and execute spm w ithin four clock cycles after w riting spmcsr. the data in r1 and r0 is ignored. the page address must be w ritten to pcpage in the z-register. other bits in the z-pointer w ill be ignored during this operation. ? page erase to the rww section: the nrww section can be read during the page erase ? page erase to the nrww section: the cpu is halted during the operation 29.7.2 filling the temporary buffer (page loading) to w rite an instruction w ord, set up the address in the z-pointer and data in r1:r0, w rite ?00000001? to spmcsr and execute spm w ithin four clock cycles after w riting spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer w ill auto-erase after a page write operation or by w riting the rwwsre bit in spmcsr. it is also erased after a system reset. note that it is not possible to w rite more than one time to each address w ithout erasing the temporary buffer. if the eeprom is w ritten in the middle of an spm page load operation, all data loaded w ill be lost. 29.7.3 performing a page write to execute page write, set up the address in the z-pointer, w rite ?x0000101? to spmcsr and execute spm w ithin four clock cycles after w riting spmcsr. the data in r1 and r0 is ignored. the page address must be w ritten to pcpage. other bits in the z-pointer must be w ritten to zero during this operation. ? page write to the rww section: the nrww section can be read during the page write ? page write to the nrww section: the cpu is halted during the operation 29.7.4 using the spm interrupt if the spm interrupt is enabled, the spm interrupt w ill generate a constant interrupt w hen the spmen bit in spmcsr is cleared. this means th at the interrupt can be used instead of polling the spmcsr register in soft w are. when using the spm interrupt, the interrupt vectors should be mo v ed to the bls section to a v oid that an interrupt is accessing the rww section w hen it is blocked for reading. ho w to mo v e the interrupts is described in ?interrupts? on page 68 . 29.7.5 consideration while updating bls special care must be taken if the user allo w s the boot loader section to be updated by lea v ing boot lock bit11 unprogrammed. an accidental w rite to the boot loader itself can corrupt the entire boot loader, and further soft w are updates might be impossible. if it is not necessary to change the boot loader soft w are itself, it is recommended to program the boot lock bit11 to protect the boot loader soft w are from any internal soft w are changes. 29.7.6 prevent reading the rww section during self-programming during self-programming (either page erase or page write), the rww section is al w ays blocked for reading. the user soft w are itself must pre v ent that this section is addressed during the self programming operation. the rwwsb in the spmcsr w ill be set as long as the rww section is busy. during self-programming the interrupt vector table should be mo v ed to the bls 353 7593l?avr?09/12 at90usb64/128 as described in ?interrupts? on page 68 , or the interrupts must be disabled. before addressing the rww section after the programming is completed, the user soft w are must clear the rwwsb by w riting the rwwsre. see ?simple assembly code example for a boot loader? on page 355 for an example. 29.7.7 setting the boot loader lock bits by spm to set the boot loader lock bits, w rite the desired data to r0, w rite ?x0001001? to spmcsr and execute spm w ithin four clock cycles after w riting spmcsr. the only accessible lock bits are the boot lock bits that may pre v ent the application and boot loader section from any soft- w are update by the mcu. see table 29-2 on page 347 and table 29-3 on page 347 for ho w the different settings of the boot loader bits affect the flash access. if bits 5..2 in r0 are cleared (zero), the corresponding boot lock bit w ill be programmed if an spm instruction is executed w ithin four cycles after blbset and spmen are set in spmcsr. the z-pointer is don?t ca re during this operation, but for fu ture compatibility it is recommended to load the z-pointer w ith 0x0001 (same as used for reading the lo ck bits). for future compatibility it is also recommended to set bits 7, 6, 1, and 0 in r0 to ?1? w hen w riting the lock bits. when pro- gramming the lock bits the entire flash can be read during the operation. 29.7.8 eeprom write prevents writing to spmcsr note that an eeprom w rite operation w ill block all soft w are programming to flash. reading the fuses and lock bits from soft w are w ill also be pre v ented during the eeprom w rite operation. it is recommended th at the user checks the status bit (eepe) in the eecr register and v erifies that the bit is cleared before w riting to the spmcsr register. 29.7.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from soft w are. to read the lock bits, load the z-pointer w ith 0x0001 and set the blbset and spmen bits in spmcsr. when an (e)lpm instruction is executed w ithin three cpu cycles after the blbset and spmen bits are set in spmcsr, the v alue of the lock bits w ill be loaded in th e destination register. the blbset and spmen bits w ill auto-clear upon comple tion of reading the lock bits or if no (e)lpm instruction is executed w ithin three cpu cycles or no spm instruction is executed w ithin four cpu cycles. when blbset and spmen are cleared, (e)lpm w ill w ork as described in the instruction set manual . the algorithm for reading the fuse lo w byte is similar to the one described abo v e for reading the lock bits. to read the fuse lo w byte, load the z-pointer w ith 0x0000 and set the blbset and spmen bits in spmcsr. when an (e)lpm instruction is executed w ithin three cycles after the blbset and spmen bits are set in the spmcsr, the v alue of the fuse lo w byte (flb) w ill be loaded in the destination register as sho w n belo w . refer to table 30-5 on page 361 for a detailed description and mapping of the fuse lo w byte. bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 1 1 bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 7654 3210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 354 7593l?avr?09/12 at90usb64/128 similarly, w hen reading the fuse high byte, load 0x0003 in the z-pointer. when an (e)lpm instruction is executed w ithin three cycles after the blbset and spmen bits are set in the spmcsr, the v alue of the fuse high byte (fhb) w ill be loaded in the des tination register as sho w n belo w . refer to table 30-4 on page 361 for detailed description and mapping of the fuse high byte. when reading the extended fuse byte, load 0x0002 in the z-pointer. when an (e)lpm instruc- tion is executed w ithin three cycles after the blbset and spmen bits are set in the spmcsr, the v alue of the extended fuse byte (efb) w ill be loaded in the desti nation register as sho w n belo w . refer to table 30-3 on page 360 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are programmed, w ill be read as zero. fuse and lock bits that are unprogrammed, w ill be read as one. 29.7.10 reading the signature row from software to read the signature ro w from soft w are, load the z-pointer w ith the signature byte address gi v en in table 29-6 on page 354 and set the sigrd and spmen bits in spmcsr. when an lpm instruction is executed w ithin three cpu cycles after the sigrd and spmen bits are set in spmcsr, the signature byte v alue w ill be loaded in the destinat ion register. the sigrd and spmen bits w ill auto-clear upon completion of reading t he signature ro w lock bits or if no lpm instruction is executed w ithin three cpu cycles. when sigrd and spmen are cleared, lpm w ill w ork as described in the instruction set manual. at90usb64/128 includes a unique 10-bytes serial number located in the signature ro w . this unique serial number can be used as a usb serial number in the de v ice enumeration process. the pointer addresses to access this unique serial number are gi v en in table 29-6 on page 354 . note: all other addresses are reser v ed for future use. 29.7.11 preventing flash corruption during periods of lo w v cc , the flash program can be corrupted because the supply v oltage is too lo w for the cpu and the flash to operate properly. these issues are the same as for board le v el systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by t w o situations w hen the v oltage is too lo w . first, a regular w rite sequence to the flash requires a minimum v oltage to operate correctly. secondly, bit 7654 3210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 bit 7654 3210 rd ? ? ? ? ? efb2 efb1 efb0 table 29-6. signature ro w addressing. signature byte z-pointer address de v ice signature byte 1 0x0000 de v ice signature byte 2 0x0002 de v ice signature byte 3 0x0004 rc oscillator calibration byte 0x0001 unique serial number from 0x000e to 0x0018 355 7593l?avr?09/12 at90usb64/128 the cpu itself can execute instruct ions incorrectly, if the supply v oltage for executing instructions is too lo w . flash corruption can easily be a v oided by follo w ing these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to pre v ent any boot loader soft w are updates. 2. keep the avr reset acti v e (lo w ) during periods of insufficient po w er supply v oltage. this can be done by enabling the internal bro w n-out detector (bod) if the operating v oltage matches the detection le v el. if not, an external lo w v cc reset protection circuit can be used. if a reset occurs w hile a w rite operation is in progress, the w rite operation w ill be completed pro v ided that the po w er supply v oltage is sufficient. 3. keep the avr core in po w er-do w n sleep mode during periods of lo w v cc . this w ill pre- v ent the cpu from attempting to decode and execute instructions, effecti v ely protecting the spmcsr register and thus the flash from unintentional w rites. 29.7.12 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 29-7 sho w s the typical pro- gramming time for flash accesses from the cpu. 29.7.13 simple assembly code example for a boot loader ;- the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y-pointer ; the first data location in flash is pointed to by the z-pointer ;- error handling is not included ;- the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;- registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcsrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;- it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcsrval, (1< 358 7593l?avr?09/12 at90usb64/128 note: 1. z0: should be zero for all spm commands, byte select for the (e)lpm instruction. see ?addressing the flash during self-programming? on page 350 for details about the use of z- pointer during self-programming. table 29-10. explanation of different v ariables used in figure 29-4 on page 351 and the map- ping to the z-pointer. variable corresponding z-value description (1) pcmsb 16 most significant bit in the program counter. (the program counter is 17 bits pc[16:0]) pag e m s b 6 most significant bit w hich is used to address the w ords w ithin one page (128 w ords in a page requires se v en bits pc [6:0]). zpcmsb z17 bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z7 bit in z-pointer that is mapped to pcmsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[16:7] z17:z8 program counter page address: page select, for page erase and page write pcword pc[6:0] z7:z1 program counter w ord address: word select, for filling temporary buffer (must be zero during page write operation) pcmsb 15 most significant bit in the program counter. (the program counter is 16 bits pc[15:0]) pag e m s b 6 most significant bit w hich is used to address the w ords w ithin one page (128 w ords in a page requires 7 bits pc [6:0]). zpcmsb z16 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z7 bit in z-register that is mapped to pagemsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[15:7] z16:z7 program counter page address: page select, for page erase and page write. pcword pc[6:0] z7:z1 program counter w ord address: word select, for filling temporary buffer (must be zero during page write operation). 359 7593l?avr?09/12 at90usb64/128 30. memory programming 30.1 program and data memory lock bits the atmel at90usb64/128 pro v ides six lock bits, w hich can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 30-2 . the lock bits can only be erased to ?1? w ith the chip erase command. note: 1. ?1? means unprogrammed, ?0? means programmed . table 30-1. lock bit byte (1) . lock bit byte bit no. description default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 5 boot lock bit 1 (unprogrammed) blb11 4 boot lock bit 0 (programmed) blb02 3 boot lock bit 1 (unprogrammed) blb01 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 0 (programmed) lb1 0 lock bit 0 (programmed) table 30-2. lock bit protection modes (1)(2) . memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flash and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and v erification of the flash and eeprom is disabled in parall el and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) blb0 mode blb02 blb01 111 no restrictions for spm or (e)lpm accessing the application section. 2 1 0 spm is not allo w ed to w rite to the application section. 300 spm is not allo w ed to w rite to the application section, and (e)lpm executing from the boot loader section is not allo w ed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled w hile executing from the application section. 401 (e)lpm executing from the boot loader section is not allo w ed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled w hile executing from the application section. 360 7593l?avr?09/12 at90usb64/128 notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed. 30.2 fuse bits the atmel at90usb64/128 has four fuse bytes. table 30-3 - table 30-5 on page 361 describe briefly the functionality of all the fuses and ho w they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. note: 1. see table 9-2 on page 60 for bodlevel fuse decoding. blb1 mode blb12 blb11 111 no restrictions for spm or (e)lpm accessing the boot loader section. 2 1 0 spm is not allo w ed to w rite to the boot loader section. 300 spm is not allo w ed to w rite to the boot loader section, and (e)lpm executing from t he application section is not allo w ed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled w hile executing from the boot loader section. 401 (e)lpm executing from the application section is not allo w ed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts are disabled w hile executing from the boot loader section. table 30-2. lock bit protection modes (1)(2) . (continued) memory lock bits protection type table 30-3. extended fuse byte ( 0xf3 ). fuse low byte bit no. des cription default value ?7? 1 ?6? 1 ?5? 1 ?4? 1 hwbe 3 hard w are boot enable 0 (programmed) bodlevel2 (1) 2bro w n-out detector trigger le v el 0 (programmed) bodlevel1 (1) 1bro w n-out detector trigger le v el 1 (unprogrammed) bodlevel0 (1) 0bro w n-out detector trigger le v el 1 (unprogrammed) 361 7593l?avr?09/12 at90usb64/128 note: 1. the spien fuse is not accessible in serial programming mode. 2. see table 29-8 on page 357 for details. 3. see ?wdtcsr ? watchdog timer control register? on page 65 for details. 4. ne v er ship a product w ith the ocden fuse programmed regardless of the setting of lock bits and jtagen fuse. a programmed ocden fuse en ables some parts of the clock system to be running in all sleep modes. this may increase the po w er consumption. note: 1. the default v alue of sut1..0 results in maximum start-up time for the default clock source (258k ck + 4.1ms). see table 9-1 on page 58 for details. 2. the default setting of cksel3..0 results in external crystal oscillator @ 8mhz. see table 7-1 on page 41 for details. 3. the ckout fuse allo w the system clock to be output on portc7. see ?clock output buffer? on page 47 for details. 4. see ?system clock prescaler? on page 47 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 30.2.1 latching of fuses the fuse v alues are latched w hen the de v ice enters programming mode and changes of the fuse v alues w ill ha v e no effect until the part lea v es programming mode. this does not apply to table 30-4. fuse high byte (at90usb128: 0x99 - at90usb64: 0x9b ). fuse high byte bit no. d escription default value ocden (4) 7 enable ocd 1 (unprogrammed, ocd disabled) jtagen 6 enable jtag 0 (programmed, jtag enabled) spien (1) 5 enable serial program and data do w nloading 0 (programmed, spi prog. enabled) wdton (3) 4 watchdog timer al w ays on 1 (unprogrammed) eesave 3 eeprom memory is preser v ed through the chip erase 1 (unprogrammed, eeprom not preser v ed) bootsz1 2 select boot size (see table 30-6 on page 363 for details) 0 (programmed) (2) bootsz0 1 select boot size (see table 30-6 on page 363 for details) 0 (programmed) (2) (at90usb128) 1 (unprogrammed) (2) (at90usb64) bootrst 0 select reset vector 1 (unprogrammed) table 30-5. fuse lo w byte ( 0x5e ). fuse low byte bit no. description default value ckdiv8 (4) 7di v ide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 0 (programmed) (1) sut0 4 select start-up time 1 (unprogrammed) (1) cksel3 3 select clock source 1 (unprogrammed) (2) cksel2 2 select clock source 1 (unprogrammed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) 362 7593l?avr?09/12 at90usb64/128 the eesave fuse w hich w ill take effect once it is progra mmed. the fuses are also latched on po w er-up in normal mode. 30.3 signature bytes all atmel microcontrollers ha v e a three-byte signature code w hich identifies the de v ice. this code can be read in both serial and parallel mode, also w hen the de v ice is locked. the three bytes reside in a separate address space. atmel at90usb128x signature bytes: 1. 0x000: 0x1e (indicates manufactured by atmel). 2. 0x001: 0x97 (indicates 128kb flash memory). 3. 0x002: 0x82 (indicates at90usb128x de v ice). atmel at90usb64x signature bytes: 1. 0x000: 0x1e (indicates manufactured by atmel). 2. 0x001: 0x96 (indicates 64kb flash memory). 3. 0x002: 0x82 (indicates at90usb64x de v ice). 30.4 calibration byte the at90usb64/128 has a byte calibration v alue for the internal rc oscillator. this byte resides in the high byte of address 0x000 in th e signature address space. during reset, this byte is automatically w ritten into the osccal register to ensure correct frequency of the calibrated rc oscillator. 30.5 parallel programming paramet ers, pin mapping, and commands this section describes ho w to parallel program and v erify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the at90usb64/128. pulses are assumed to be at least 250ns unless other w ise noted. 30.5.1 signal names in this section, some pins of the at90usb64/128 are referenced by signal names describing their functionality during parallel programming, see figure 30-1 on page 363 and table 30-6 on page 363 . pins not described in the follo w ing table are referenced by pin names. the xa1/xa0 pins determine the action executed w hen the xtal1 pin is gi v en a positi v e pulse. the bit coding is sho w n in table 30-9 on page 364 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are sho w n in table 30-10 on page 364 . 363 7593l?avr?09/12 at90usb64/128 figure 30-1. parallel programming (1) . note: 1. unused pins should be left floating. table 30-6. pin name mapping. signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: de v ice is busy programming 1: de v ice is ready for ne w command oe pd2 i output enable (acti v e lo w ) wr pd3 i write pulse (acti v e lo w ) bs1 pd4 i byte select 1 xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pagel pd7 i program memory and eeprom data page load bs2 pa0 i byte select 2 data pb7-0 i/o bi-directional data bus (output w hen oe is lo w ) table 30-7. bs2 and bs1 encoding. bs2 bs1 flash/eeprom address flash data loading/reading fuse programming reading fuse and lock bits 00lo w byte lo w byte lo w byte fuse lo w byte 0 1 high byte high byte high byte lock-bits 10 extended high byte reser v ed extended byte extended fuse byte 11reser v ed reser v ed reser v ed fuse high byte vcc +5v gnd xtal1 pd1 pd2 pd3 pd4 pd5 pd6 pb7 - pb0 data re s et pd7 +12v b s 1 xa0 xa1 oe rdy/b s y pagel pa0 wr b s 2 avcc +5v 364 7593l?avr?09/12 at90usb64/128 table 30-8. pin v alues used to enter programming mode. pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 table 30-9. xa1 and xa0 enoding. xa1 xa0 action when xtal1 is pulsed 00 load flash or eeprom address (high or lo w address byte determined by bs2 and bs1). 0 1 load data (high or lo w data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 30-10. command byte bit encoding. command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom table 30-11. no. of w ords in a page and no. of pages in the flash. flash size page size pcword no. of pages pcpage pcmsb 16k w ords (32kbytes) 64 w ords pc[6:0] 256 pc[13:7] 13 32k w ords (64kbytes) 128 w ords pc[6:0] 256 pc[14:7] 14 64k w ords (128kbytes) 128 w ords pc[6:0] 512 pc[15:7] 15 365 7593l?avr?09/12 at90usb64/128 30.6 parallel programming 30.6.1 enter programming mode the follo w ing algorithm puts the de v ice in parallel programming mode: 1. apply 4.5 - 5.5v bet w een v cc and gnd. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 30-8 on page 364 to ?0000? and w ait at least 100ns. 4. apply 11.5 - 12.5v to reset . any acti v ity on prog_enable pins w ithin 100ns after +12v has been applied to reset , w ill cause the de v ice to fail entering programming mode. 5. wait at least 50s before sending a ne w command. 30.6.2 considerations for efficient programming the loaded command and address are retained in the de v ice during programming. for efficient programming, the follo w ing should be considered. ? the command needs only be loaded once w hen w riting or reading multiple memory locations ?skip w riting the data v alue 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase ? address high byte needs only be loaded before programming or reading a ne w 256 w ord w indo w in flash or 256 byte eeprom. this cons ideration also applies to signature bytes reading 30.6.3 chip erase the chip erase w ill erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be perfor med before the flas h and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preser v ed during chip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. gi v e xtal1 a positi v e pulse. this loads the command. 5. gi v e wr a negati v e pulse. this starts the chip erase. rdy/bsy goes lo w . 6. wait until rdy/bsy goes high before loading a ne w command. table 30-12. no. of w ords in a page and no. of pages in the eeprom. eeprom size page size pcword no. of pages pcpage eeamsb 1kbytes 4 bytes eea[2:0] 256 eea[9:3] 9 2kbytes 8 bytes eea[2:0] 256 eea[10:3] 10 4kbytes 8 bytes eea[2:0] 512 eea[11:3] 11 366 7593l?avr?09/12 at90usb64/128 30.6.4 programming the flash the flash is organized in pages, see table 30-11 on page 364 . when programming the flash, the program data is latched into a page buffer. this allo w s one page of program data to be pro- grammed simultaneously. the follo w ing procedure describes ho w to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. gi v e xtal1 a positi v e pulse. this loads the command. b. load address lo w byte (address bits 7..0) 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?00?. this selects the address lo w byte. 3. set data = address lo w byte (0x00 - 0xff). 4. gi v e xtal1 a positi v e pulse. this loads the address lo w byte. c. load data lo w byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data lo w byte (0x00 - 0xff). 3. gi v e xtal1 a positi v e pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. gi v e xtal1 a positi v e pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. gi v e pagel a positi v e pulse. this latches the data bytes. (see figure 30-3 on page 368 for signal w a v eforms) f. repeat b through e until the entire buffer is filled or until all data w ithin the page is loaded. while the lo w er bits in the address are mapped to w ords w ithin the page, the higher bits address the pages w ithin the flash. this is illustrated in figure 30-2 on page 367 . note that if less than eight bits are required to address w ords in the page (pagesize < 256), the most significant bit(s) in the address lo w byte are used to address the page w hen performing a page write. g. load address high byte (address bits15..8) 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?01?. this selects the address high byte. 3. set data = address high byte (0x00 - 0xff). 4. gi v e xtal1 a positi v e pulse. this loads the address high byte. h. load address extended high byte (address bits 23..16) 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs2, bs1 to ?10?. this selects the address extended high byte. 367 7593l?avr?09/12 at90usb64/128 3. set data = address extended high byte (0x00 - 0xff). 4. gi v e xtal1 a positi v e pulse. this loads the address high byte. i. program page 1. set bs2, bs1 to ?00? 2. gi v e wr a negati v e pulse. this starts programming of the entire page of data. rdy/bsy goes lo w . 3. wait until rdy/bsy goes high (see figure 30-3 on page 368 for signal w a v eforms). j. repeat b through i until the entire flash is programmed or until all data has been programmed. k. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. gi v e xtal1 a positi v e pulse. this loads the command, and the internal w rite signals are reset. figure 30-2. addressing the flash w hich is organized in pages (1) . note: 1. pcpage and pcword are listed in table 30-11 on page 364 . program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 368 7593l?avr?09/12 at90usb64/128 figure 30-3. programming the flash w a v eforms (1) . note: 1. ?xx? is don?t care. the letters refer to the programming description abo v e. 30.6.5 programming the eeprom the eeprom is organized in pages, see table 30-12 on page 365 . when programming the eeprom, the program data is latche d into a page buffer. this allo w s one page of data to be programmed simultaneously. th e programming algorithm for th e eeprom data memory is as follo w s (refer to ?programming the flash? on page 366 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address lo w byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (gi v e pagel a positi v e pulse). k: repeat 3 through 5 until the entire buffer is filled. l: program eeprom page 1. set bs2, bs1 to ?00?. 2. gi v e wr a negati v e pulse. this starts programm ing of the eeprom page. rdy/bsy goes lo w . 3. wait until to rdy/bsy goes high before programming the next page (see figure 30-4 on page 369 for signal w a v eforms). rdy/b s y wr oe re s et +12v pagel b s 2 0x10 addr. low addr. high data data low data high addr. low data low data high xa1 xa0 b s 1 xtal1 xx xx xx abcdeb cdeg f addr. ext.h h i 369 7593l?avr?09/12 at90usb64/128 figure 30-4. programming the eeprom w a v eforms. 30.6.6 reading the flash the algorithm for reading the flash memory is as follo w s (refer to ?programming the flash? on page 366 for details on command and address loading): 1. a: load command ?0000 0010?. 2. h: load address extended byte (0x00- 0xff). 3. g: load address high byte (0x00 - 0xff). 4. b: load address lo w byte (0x00 - 0xff). 5. set oe to ?0?, and bs1 to ?0?. the flash w ord lo w byte can no w be read at data. 6. set bs to ?1?. the flash w ord high byte can no w be read at data. 7. set oe to ?1?. 30.6.7 reading the eeprom the algorithm for reading th e eeprom memory is as follo w s (refer to ?programming the flash? on page 366 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address lo w byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can no w be read at data. 5. set oe to ?1?. 30.6.8 programming the fuse low bits the algorithm for programming the fuse lo w bits is as follo w s (refer to ?programming the flash? on page 366 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data lo w byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. gi v e wr a negati v e pulse and w ait for rdy/bsy to go high. rdy/b s y wr oe re s et +12v pagel b s 2 0x11 addr. high data addr. low data addr. low data xx xa1 xa0 b s 1 xtal1 xx agbceb c el k 370 7593l?avr?09/12 at90usb64/128 30.6.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follo w s (refer to ?programming the flash? on page 366 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data lo w byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs2, bs1 to ?01?. this selects high data byte. 4. gi v e wr a negati v e pulse and w ait for rdy/bsy to go high. 5. set bs2, bs1 to ?00?. this selects lo w data byte. 30.6.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follo w s (refer to ?programming the flash? on page 366 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data lo w byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs2, bs1 to ?10?. this selects extended data byte. 4. 4. gi v e wr a negati v e pulse and w ait for rdy/bsy to go high. 5. 5. set bs2, bs1 to ?00?. this selects lo w data byte. figure 30-5. programming the fuses w a v eforms. 30.6.11 programming the lock bits the algorithm for programming the lock bits is as follo w s (refer to ?programming the flash? on page 366 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data lo w byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. gi v e wr a negati v e pulse and w ait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. rdy/bsy wr oe reset +12v pagel 0x40 data data xx xa1 xa0 bs1 xtal1 ac 0x40 data xx ac write f us e low b yte write f us e high b yte 0x40 data xx ac write extended f us e b yte bs2 371 7593l?avr?09/12 at90usb64/128 30.6.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follo w s (refer to ?programming the flash? on page 366 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, and bs2, bs1 to ?00?. the status of the fuse lo w bits can no w be read at data (?0? means programmed). 3. set oe to ?0?, and bs2, bs1 to ?11?. the status of the fuse high bits can no w be read at data (?0? means programmed). 4. set oe to ?0?, and bs2, bs1 to ?10?. the status of the extended fuse bits can no w be read at data (?0? means programmed). 5. set oe to ?0?, and bs2, bs1 to ?01?. the status of the lock bits can no w be read at data (?0? means programmed). 6. set oe to ?1?. figure 30-6. mapping bet w een bs1, bs2 and the fuse and lock bits during read. 30.6.13 reading the signature bytes the algorithm for reading the signature bytes is as follo w s (refer to ?programming the flash? on page 366 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address lo w byte (0x00 - 0x02). 3. set oe to ?0?, and bs to ?0?. the selected signature byte can no w be read at data. 4. set oe to ?1?. 30.6.14 reading the calibration byte the algorithm for reading the calibration byte is as follo w s (refer to ?programming the flash? on page 366 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address lo w byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can no w be read at data. 4. set oe to ?1?. lock bits 0 1 b s 2 fuse high byte 0 1 b s 1 data fuse low byte 0 1 b s 2 extended fuse byte 372 7593l?avr?09/12 at90usb64/128 30.6.15 parallel programming characteristics figure 30-7. parallel programming timing, including some general timing requirements. figure 30-8. parallel programming ti ming, loading sequence w ith timing requirements (1) . note: 1. the timing requirements sho w n in figure 30-7 (that is, t dvxh , t xhxl , and t xldx ) also apply to loading operation. figure 30-9. parallel programming timing, reading sequence ( w ithin the same page) w ith tim- ing requirements (1) . data & control (data, xa0/1, b s 1, b s 2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/b s y pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl xtal1 pagel t plxh xlxh t t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data b s 1 xa0 xa1 load addre ss (low byte) load data (low byte) load data (high byte) load data load addre ss (low byte) xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data b s 1 xa0 xa1 load addre ss (low byte) read data (low byte) read data (high byte) load addre ss (low byte) t bvdv t oldv t xlol t ohdz 373 7593l?avr?09/12 at90usb64/128 note: 1. the timing requirements sho w n in figure 30-7 (that is, t dvxh , t xhxl , and t xldx ) also apply to reading operation. notes: 1. t wlrh is v alid for the write flash, write eeprom, write fuse bits and write lock bits commands. 2. t wlrh_ce is v alid for the chip erase command. 30.7 serial downloading both the flash and eeprom memo ry arrays can be programmed using a serial programming bus w hile reset is pulled to gnd. the serial programming interface consists of pins sck, pdi (input) and pdo (output). after reset is set lo w , the programming enable instruction needs to be executed first before program/erase operations can be executed. note, in table 30-14 on page 374 , the pin mapping for serial programming is listed. not all packages use the spi pins dedicated for the internal serial peripheral interface - spi. table 30-13. parallel programming characteristics, v cc = 5v 10%. symbol parameter min. typ. max. units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 lo w to xtal1 high 200 t xhxl xtal1 pulse width high 150 t xldx data and control hold after xtal1 lo w 67 t xlwl xtal1 lo w to wr lo w 0 t xlph xtal1 lo w to pagel high 0 t plxh pag e l l o w to xtal1 high 150 t bvph bs1 valid before pagel high 67 t phpl pagel pulse width high 150 t plbx bs1 hold after pagel lo w 67 t wlbx bs2/1 hold after wr lo w 67 t plwl pagel lo w to wr lo w 67 t bvwl bs2/1 valid to wr lo w 67 t wlwh wr pulse width lo w 150 t wlrl wr lo w to rdy/bsy lo w 01 s t wlrh wr lo w to rdy/bsy high (1) 3.7 4.5 ms t wlrh_ce wr lo w to rdy/bsy high for chip erase (2) 7.5 9 t xlol xtal1 lo w to oe lo w 0 ns t bvdv bs1 valid to data v alid 0 250 t oldv oe lo w to data valid 250 t ohdz oe high to data tri-stated 250 374 7593l?avr?09/12 at90usb64/128 30.8 serial programming pin mapping figure 30-10. serial programming and v erify (1) . notes: 1. if the de v ice is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. 2. v cc - 0.3v < avcc < v cc + 0.3v, ho w e v er, avcc should al w ays be w ithin 1.8 - 5.5v. when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of e v ery memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a v alid clock must be present. the minimum lo w and high periods for the serial clock (sck) input are defined as follo w s: lo w : > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck >= 12mhz high: > 2 cpu clock cycles for f ck < 12mhz, 3 cpu clock cycles for f ck >= 12mhz 30.8.1 serial programming algorithm when w riting serial data to the atmel at90usb64/ 128, data is clocked on the rising edge of sck. when reading data from the at90usb64/128, data is cl ocked on the falling edge of sck. see figure 30-11 on page 375 for timing details. to program and v erify the at90usb64/128 in the serial programming mode, the follo w ing sequence is recommended (see four byte instruction formats in table 30-16 on page 376 ): 1. po w er-up sequence: apply po w er bet w een v cc and gnd w hile reset and sck are set to ?0?. in some sys- tems, the programmer can not guarantee that sck is held lo w during po w er-up. in this case, reset must be gi v en a positi v e pulse of at least t w o cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20ms and enable serial programming by sending the programming enable serial instruction to pin pdi. table 30-14. pin mapping serial programming. symbol pins (tqfp-64) i/o description pdi pb2 i serial data in pdo pb3 o serial data out sck pb1 i serial clock vcc gnd xtal1 sck pdo pdi reset +1.8 - 5.5v avcc +1.8 - 5.5v (2) 375 7593l?avr?09/12 at90usb64/128 3. the serial programming instructions w ill not w ork if the communication is out of syn- chronization. when in sync. the second byte (0x53), w ill echo back w hen issuing the third byte of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, gi v e reset a positi v e pulse and issue a ne w programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 7 lsb of the address and data together w ith the load program memory page instruction. to ensure correct loading of the page, the data lo w byte must be loaded before data high byte is applied for a gi v en address. the program memory page is stored by loading the write program memory page instruction w ith the address lines 15..8. before issuing this command, make sure the instruction load extended address byte has been used to define the msb of the address. the extended address byte is stored until the command is re-issued, i.e., the command needs only be issued for the first page, and w hen crossing the 64kword boundary. if polling (rdy/bsy ) is not used, the user must w ait at least t wd_flash before issuing the next page. (see table 30- 15 .) accessing the serial programming interface before the flash w rite operation com- pletes can result in incorrect programming. 5. the eeprom array is programmed one byte at a time by supplying the address and data together w ith the appropriate write instruction. an eeprom memory location is first automatically erased before ne w data is w ritten. if polling is not used, the user must w ait at least t wd_eeprom before issuing the next byte. (see table 30-15 .) in a chip erased de v ice, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be v erified by using the read instruction w hich returns the content at the selected address at serial output pdo. when reading the flash memory, use the instruction load extended address byte to define the upper address byte, w hich is not included in the read program memory instruction. the extended address byte is stored until the command is re-issued, that is, the command needs only be issued for the first page, and w hen crossing the 64kword boundary. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. po w er-off sequence (if needed): set reset to ?1?. tu r n v cc po w er off. figure 30-11. serial programming w a v eforms. table 30-15. minimum w ait delay before w riting the next flash or eeprom location. symbol minimum wait delay t wd_flash 4.5ms t wd_eeprom 9.0ms t wd_erase 9.0ms m s b m s b l s b l s b s erial clock input ( s ck) s erial data input (mo s i) (mi s o) s ample s erial data output 376 7593l?avr?09/12 at90usb64/128 table 30-16. serial programming instruction set. instruction instruction format operation byte 1 byte 2 byte 3 byte 4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after reset goes lo w . chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase eeprom and flash. load extended address byte 0100 1101 0000 0000 cccc cccc xxxx xxxx defines extended address byte for read program memory and write program memory page. read program memory 0010 h 000 aaaa aaaa bbbb bbbb oooo oooo read h (high or lo w ) data o from program memory at w ord address c : a : b . load program memory page 0100 h 000 xxxx xxxx xx bb bbbb iiii iiii write h (high or lo w ) data i to program memory page at w ord address b . data lo w byte must be loaded before data high byte is applied w ithin the same address. write program memory page 0100 1100 aaaa aaaa bb xx xxxx xxxx xxxx write program memory page at address c : a : b . read eeprom memory 1010 0000 0000 aaaa bbbb bbbb oooo oooo read data o from eeprom memory at address a : b . write eeprom memory 1100 0000 0000 aaaa bbbb bbbb iiii iiii write data i to eeprom memory at address a : b . load eeprom memory page (page access) 1100 0001 0000 0000 0000 00 bb iiii iiii load data i to eeprom memory page buffer. after data is loaded, program eeprom page. write eeprom memory page (page access) 1100 0010 0000 aaaa bbbb bb00 xxxx xxxx write eeprom page at address a : b . read lock bits 0101 1000 0000 0000 xxxx xxxx xx oo oooo read lock bits. ?0? = programmed, ?1? = unprogrammed. see table 30-1 on page 359 for details. write lock bits 1010 1100 111x xxxx xxxx xxxx 11 ii iiii write lock bits. set bits = ?0? to program lock bits. see table 30-1 on page 359 for details. read signature byte 0011 0000 000x xxxx xxxx xx bb oooo oooo read signature byte o at address b . write fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. write fuse high bits 1010 1100 1010 1000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. write extended fuse bits 1010 1100 1010 0100 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 30-3 on page 360 for details. read fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo read fuse bits. ?0? = programmed, ?1? = unprogrammed. read fuse high bits 0101 1000 0000 1000 xxxx xxxx oooo oooo read fuse high bits. ?0? = pro- grammed, ?1? = unprogrammed. 377 7593l?avr?09/12 at90usb64/128 note: a = address high bits, b = address lo w bits, c = address extended bits, h = 0 - lo w byte, 1 - high byte, o = data out, i = data in, x = don?t care. 30.8.2 serial programming characteristics for characteristics of the serial programming module see ?spi timing characteristics? on page 395 . 30.9 programming via the jtag interface programming through the jtag interface requires control of the four jtag specific pins: tck, tms, tdi, and tdo. control of the reset and clock pins is not required. to be able to use the jtag interface, the jtagen fuse must be programmed. the de v ice is default shipped w ith the fuse programmed. in addition, the jtd bit in mcucr must be cleared. alternati v ely, if the jtd bit is set, the external reset can be forced lo w . then, the jtd bit w ill be cleared after t w o chip clocks, and the jtag pins are a v ailable for programming. this pro v ides a means of using the jtag pins as normal port pins in running mode w hile still allo w ing in-sys- tem programming v ia the jtag interface. note that this technique can not be used w hen using the jtag pins for boundary-scan or on-chip debug. in these cases the jtag pins must be ded- icated for this purpose. during programming the clock frequency of the tck input must be less than the maximum fre- quency of the chip. the system clock prescaler can not be used to di v ide the tck clock input into a sufficiently lo w frequency. as a definition in this datasheet, the lsb is shifted in and out first of all shift registers. 30.9.1 programming specific jtag instructions the instruction register is 4-bit w ide, supporting up to 16 instructions. the jtag instructions useful for programming are listed belo w . the opcode for each instruction is sho w n behind the instruction name in hex format. the text describes w hich data register is selected as path bet w een tdi and tdo for each instruction. the run-test/idle state of the tap controller is used to generate internal clocks. it can also be used as an idle state bet w een jtag sequences. the state machine sequence for changing the instruction w ord is sho w n in figure 30-12 on page 378 . read extended fuse bits 0101 0000 0000 1000 xxxx xxxx oooo oooo read extended fuse bits. ?0? = pro- grammed, ?1? = unprogrammed. see table 30-3 on page 360 for details. read calibration byte 0011 1000 000x xxxx 0000 0000 oooo oooo read calibration byte poll rdy/bsy 1111 0000 0000 0000 xxxx xxxx xxxx xxx o if o = ?1?, a programming operation is still busy. wait until this bit returns to ?0? before applying another command. table 30-16. serial programming instruction set. (continued) instruction instruction format operation byte 1 byte 2 byte 3 byte 4 378 7593l?avr?09/12 at90usb64/128 figure 30-12. state machine sequence for changing the instruction w ord. 30.9.2 avr_reset (0xc) the avr specific public jtag in struction for setting the avr de v ice in the reset mode or taking the de v ice out from the reset mode. the tap controller is not reset by this instruction. the one bit reset register is selected as data register. note that the reset w ill be acti v e as long as there is a logic ?one? in the reset chain. the output from this chain is not latched. the acti v e states are: ? shift-dr: the reset register is shifted by the tck input 30.9.3 prog_enable (0x4) the avr specific public jtag in struction for enabling programming v ia the jtag port. the 16- bit programming enable register is selected as data register. the acti v e states are the follo w ing: ? shift-dr: the programming enable signature is shifted into the data register ? update-dr: the programming enable signature is compared to the correct v alue, and programming mode is entered if the signature is v alid te s t-logic-re s et r u n-te s t/idle shift-dr exit1-dr p aus e-dr exit2-dr upd a te-dr s elect-ir s can capture-ir s hift-ir exit1-ir pau s e-ir exit2-ir update-ir s elect-dr s can c a pt u re-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 379 7593l?avr?09/12 at90usb64/128 30.9.4 prog_commands (0x5) the avr specific public jtag instruction for entering programming commands v ia the jtag port. the 15-bit programming command register is selected as data register. the acti v e states are the follo w ing: ? capture-dr: the result of the pre v ious command is loaded into the data register ? shift-dr: the data register is shifted by the tck input, shifting out the result of the pre v ious command and shifting in the ne w command ? update-dr: the programming command is applied to the flash inputs ? run-test/idle: one clock cycle is generated, executing the applied command 30.9.5 prog_pageload (0x6) the avr specific public jtag instruction to directly load the flash data page v ia the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the eight lsbs of the programming command register. the acti v e states are the follo w ing: ? shift-dr: the flash data byte register is shifted by the tck input ? update-dr: the content of the flash data byte register is copied into a temporary register. a w rite sequence is initiated that w ithin 11 tck cycles loads the content of the temporary register into the flash page buffer. the avr automatically alternates bet w een w riting the lo w and the high byte for each ne w update-dr state, starting w ith the lo w byte for the first update-dr encountered after entering the prog_pageload command. the program counter is pre-incriminated before w riting the lo w byte, except for the first w ritten byte. this ensures that the first data is w ritten to the address set up by prog_commands, and loading the last location in the page buffer does not make the program counter increment into the next page 30.9.6 prog_pageread (0x7) the avr specific public jt ag instruction to directly capture the flash content v ia the jtag port. an 8-bit flash data byte register is selected as the data register. this is physically the 8 lsbs of the programming command register. the acti v e states are the follo w ing: ? capture-dr: the content of the selected flash byte is captured into the flash data byte register. the avr automatically alternates bet w een reading the lo w and the high byte for each ne w capture-dr state, starting w ith the lo w byte for the first capture-dr encountered after entering the prog_pageread command. the program counter is post-incremented after reading each high byte, including the first r ead byte. this ensures that the first data is captured from the first address set up by prog_commands, and reading the last location in the page makes the program counter increment into the next page ? shift-dr: the flash data byte register is shifted by the tck input 30.9.7 data registers the data registers are selected by the jtag instruction registers described in section ?pro- gramming specific jtag instructions? on page 377 . the data registers rele v ant for programming operations are: ? reset register ? programming enable register ? programming command register ? flash data byte register 380 7593l?avr?09/12 at90usb64/128 30.9.8 reset register the reset register is a test data register used to reset the part during programming. it is required to reset the part before entering programming mode. a high v alue in the reset regist er corresponds to pullin g the external reset lo w . the part is reset as long as there is a high v alue present in the reset register. depending on the fuse settings for the clock options, the part w ill remain reset for a reset time-out period (refer to ?clock sources? on page 41 ) after releasing the reset register. the output from this data register is not latched, so the reset w ill take place immediately, as sho w n in figure 9-1 on page 58 . 30.9.9 programming enable register the programming enable register is a 16-bit regist er. the contents of this register is compared to the programming enable signature, binary code 0b1010_0011_0111_0000. when the con- tents of the register is equal to the programming enable signature, programming v ia the jtag port is enabled. the register is reset to 0 on po w er-on reset, and should al w ays be reset w hen lea v ing programming mode. figure 30-13. programming enable register. 30.9.10 programming command register the programming command register is a 15-bit regist er. this register is us ed to serially shift in programming commands, and to serially shift out the result of the pre v ious command, if any. the jtag programming instruction set is sho w n in table 30-17 on page 382 . the state sequence w hen shifting in the programming co mmands is illustrated in figure 30-15 on page 385 . tdi tdo d a t a = dq clockdr & prog_enable progr a mming en ab le 0xa 3 70 381 7593l?avr?09/12 at90usb64/128 figure 30-14. programming command register. tdi tdo s t r o b e s a d d r e s s / d a t a fl as h eeprom f us e s lock b it s 382 7593l?avr?09/12 at90usb64/128 table 30-17. jtag programming instruction set. a = address high bits, b = address lo w bits, c = address extended bits, h = 0 - lo w byte, 1 - high byte, o = data out, i = data in, x = don?t care. instruction tdi sequence tdo sequence notes 1a. chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b. poll for chip erase complete 0110011_10000000 xxxxx o x_xxxxxxxx (2) 2a. enter flash write 0100011_00010000 xxxxxxx_xxxxxxxx 2b. load address extended high byte 0001011_ cccccccc xxxxxxx_xxxxxxxx (10) 2c. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx 2d. load address lo w byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 2e. load data lo w byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 2f. load data high byte 0010111_ iiiiiiii xxxxxxx_xxxxxxxx 2g. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2h. write flash page 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 2i. poll for page write complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 3a. enter flash read 0100011_00000010 xxxxxxx_xxxxxxxx 3b. load address extended high byte 0001011_ cccccccc xxxxxxx_xxxxxxxx (10) 3c. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx 3d. load address lo w byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 3e. read data lo w and high byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo lo w byte high byte 4a. enter eeprom write 0100011_00010001 xxxxxxx_xxxxxxxx 4b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (10) 4c. load address lo w byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 4d. load data byte 0010011_ iiiiiiii xxxxxxx_xxxxxxxx 4e. latch data 0110111_00000000 1110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 4f. write eeprom page 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 383 7593l?avr?09/12 at90usb64/128 4g. poll for page write complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 5a. enter eeprom read 0100011_00000011 xxxxxxx_xxxxxxxx 5b. load address high byte 0000111_ aaaaaaaa xxxxxxx_xxxxxxxx (10) 5c. load address lo w byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 5d. read data byte 0110011_ bbbbbbbb 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 6a. enter fuse write 0100011_01000000 xxxxxxx_xxxxxxxx 6b. load data lo w byte (6) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6c. write fuse extended byte 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6d. poll for fuse write complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 6e. load data lo w byte (7) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6f. write fuse high byte 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6g. poll for fuse write complete 0110111_00000000 xxxxx o x_xxxxxxxx (2) 6h. load data lo w byte (7) 0010011_ iiiiiiii xxxxxxx_xxxxxxxx (3) 6i. write fuse lo w byte 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 6j. poll for fuse write complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 7a. enter lock bit write 0100011_00100000 xxxxxxx_xxxxxxxx 7b. load data byte (9) 0010011_11 iiiiii xxxxxxx_xxxxxxxx (4) 7c. write lock bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 7d. poll for lock bit write complete 0110011_00000000 xxxxx o x_xxxxxxxx (2) 8a. enter fuse/lock bit read 0100011_00000100 xxxxxxx_xxxxxxxx 8b. read extended fuse byte (6) 0111010_00000000 0111011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8c. read fuse high byte (7) 0111110_00000000 0111111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo table 30-17. jtag programming instruction set. (continued) a = address high bits, b = address lo w bits, c = address extended bits, h = 0 - lo w byte, 1 - high byte, o = data out, i = data in, x = don?t care. instruction tdi sequence tdo sequence notes 384 7593l?avr?09/12 at90usb64/128 notes: 1. this command sequence is not required if the se v en msb are correctly set by the pre v ious command sequence ( w hich is normally the case). 2. repeat until o = ?1?. 3. set bits to ?0? to program the corresponding fuse, ?1? to un-program the fuse. 4. set bits to ?0? to program the corresponding lock bit, ?1? to lea v e the lock bit unchanged. 5. ?0? = programmed, ?1? = un-programmed. 6. the bit mapping for fuses extended byte is listed in table 30-3 on page 360 . 7. the bit mapping for fuses high byte is listed in table 30-4 on page 361 . 8. the bit mapping for fuses lo w byte is listed in table 30-5 on page 361 . 9. the bit mapping for lock bits byte is listed in table 30-1 on page 359 . 10. address bits exceeding pcmsb and eeamsb ( table 30-11 on page 364 and table 30-12 on page 365 ) are don?t care. 11. all tdi and tdo sequences are represented by binary digits (0b...). 8d. read fuse lo w byte (8) 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 8e. read lock bits (9) 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xx oooooo (5) 8f. read fuses and lock bits 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo xxxxxxx_ oooooooo (5) fuse ext. byte fuse high byte fuse lo w byte lock bits 9a. enter signature byte read 0100011_00001000 xxxxxxx_xxxxxxxx 9b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 9c. read signature byte 0110010_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 10a. enter calibration byte read 0100011_00001000 xxxxxxx_xxxxxxxx 10b. load address byte 0000011_ bbbbbbbb xxxxxxx_xxxxxxxx 10c. read calibration byte 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_ oooooooo 11a. load no operation command 0100011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx table 30-17. jtag programming instruction set. (continued) a = address high bits, b = address lo w bits, c = address extended bits, h = 0 - lo w byte, 1 - high byte, o = data out, i = data in, x = don?t care. instruction tdi sequence tdo sequence notes 385 7593l?avr?09/12 at90usb64/128 figure 30-15. state machine sequence for changing/reading the data w ord. 30.9.11 flash data byte register the flash data byte register pro v ides an efficient w ay to load the entire flash page buffer before executing page write, or to read out/ v erify the content of the flash. a state machine sets up the control signals to the flash and senses the strobe signals from the flash, thus only the data w ords need to be shifted in/out. the flash data byte register actually consists of the 8-bit scan chain and a 8-bit temporary reg- ister. during page load, the update-dr state copies the content of the scan chain o v er to the temporary register and initiates a w rite sequence that w ithin 11 tck cycles loads the content of the temporary register into the flash page buffer. the avr automatically alternates bet w een w riting the lo w and the high byte for each ne w update-dr state, starting w ith the lo w byte for the first update-dr encountered after entering the prog_pageload command. the program counter is pre-incremented before w riting the lo w byte, except for the first w ritten byte. this ensures that the first data is w ritten to the address set up by prog_commands, and loading the last location in the page buffer does not make the program counter increment into the next page. during page read, the content of the selected flash byte is captured into the flash data byte register during the capture-dr state. the avr automatically alternates bet w een reading the lo w and the high byte for each ne w capture-dr state, starting w ith the lo w byte for the first cap- te s t-logic-re s et run-te s t/idle s hift-dr exit1-dr pau s e-dr exit2-dr update-dr select-ir s c a n c a pt u re-ir shift-ir exit1-ir p aus e-ir exit2-ir upd a te-ir s elect-dr s can capture-dr 0 1 0 11 1 00 00 11 1 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 1 386 7593l?avr?09/12 at90usb64/128 ture-dr encountered after entering the prog_pageread command. the program counter is post-incremented after reading each high byte, including the first read byte. this ensures that the first data is captured from the first ad dress set up by prog_commands, and reading the last location in the page makes the program counter increment into the next page. figure 30-16. flash data byte register. the state machine controlling the flash data by te register is clocked by tck. during normal operation in w hich eight bits are shifted for each fl ash byte, the clock cycles needed to na v igate through the tap controller automatically feeds the state machine for the flash data byte regis- ter w ith sufficient number of clock pulses to comp lete its operation transparently for the user. ho w e v er, if too fe w bits are shifted bet w een each update-dr state during page load, the tap controller should stay in the run-test/idle state for some tck cycles to ensure that there are at least 11 tck cycles bet w een each update-dr state. 30.9.12 programming algorithm all references belo w of type ?1a?, ?1b?, and so on, refer to table 30-17 on page 382 . 30.9.13 entering programming mode 1. enter jtag instruction avr_reset and shift 1 in the reset register. 2. enter instruction prog_enable and shift 0b1010_0011_0111_0000 in the program- ming enable register. 30.9.14 leaving programming mode 1. enter jtag instruction prog_commands. 2. disable all programming instructions by using no operation instruction 11a. 3. enter instruction prog_enable and shift 0b0000_0000_0000_0000 in the program- ming enable register. 4. enter jtag instruction avr_reset and shift 0 in the reset register. tdi tdo d a t a fl as h eeprom f us e s lock b it s strobes address st a te m a chine 387 7593l?avr?09/12 at90usb64/128 30.9.15 performing chip erase 1. enter jtag instruction prog_commands. 2. start chip erase using programming instruction 1a. 3. poll for chip erase complete usin g programming instruction 1b, or w ait for t wlrh_ce (refer to table 30-13 on page 373 ). 30.9.16 programming the flash before programming the flash a chip erase must be performed, see ?performing chip erase? on page 387 . 1. enter jtag instruction prog_commands. 2. enable flash w rite using programming instruction 2a. 3. load address extended high byte using programming instruction 2b. 4. load address high byte using programming instruction 2c. 5. load address lo w byte using programming instruction 2d. 6. load data using programming instructions 2e, 2f and 2g. 7. repeat steps 5 and 6 for all instruction w ords in the page. 8. write the page using programming instruction 2h. 9. poll for flash w rite complete using programming instruction 2i, or w ait for t wlrh (refer to table 30-13 on page 373 ). 10. repeat steps 3 to 9 until all data ha v e been programmed. a more efficient data transfer can be achie v ed using the prog_pageload instruction: 1. enter jtag instruction prog_commands. 2. enable flash w rite using programming instruction 2a. 3. load the page address using programming instructions 2b, 2c and 2d. pcword (refer to table 30-11 on page 364 ) is used to address w ithin one page and must be w ritten as 0. 4. enter jtag instruction prog_pageload. 5. load the entire page by shifting in all instruction w ords in the page byte-by-byte, start- ing w ith the lsb of the first instruction in the page and ending w ith the msb of the last instruction in the page. use update-dr to copy the contents of the flash data byte register into the flash page location and to auto-increment the program counter before each ne w w ord. 6. enter jtag instruction prog_commands. 7. write the page using programming instruction 2h. 8. poll for flash w rite complete using programming instruction 2i, or w ait for t wlrh (refer to table 30-13 on page 373 ). 9. repeat steps 3 to 8 until all data ha v e been programmed. 30.9.17 reading the flash 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load address using programming instructions 3b, 3c and 3d. 4. read data using programming instruction 3e. 5. repeat steps 3 and 4 until all data ha v e been read. a more efficient data transfer can be achie v ed using the prog_pageread instruction: 388 7593l?avr?09/12 at90usb64/128 1. enter jtag instruction prog_commands. 2. enable flash read using programming instruction 3a. 3. load the page address using programming instructions 3b, 3c and 3d. pcword (refer to table 30-11 on page 364 ) is used to address w ithin one page and must be w ritten as 0. 4. enter jtag instruction prog_pageread. 5. read the entire page (or flash) by shifting out all instruction w ords in the page (or flash), starting w ith the lsb of the first instruction in the page (flash) and ending w ith the msb of the last instruction in the page (flash). the capture-dr state both captures the data from the flash, and also auto-increments the program counter after each w ord is read. note that capture-dr comes before the shift-dr state. hence, the first byte w hich is shifted out contains v alid data. 6. enter jtag instruction prog_commands. 7. repeat steps 3 to 6 until all data ha v e been read. 30.9.18 programming the eeprom before programming the eeprom a chip erase must be performed, see ?performing chip erase? on page 387 . 1. enter jtag instruction prog_commands. 2. enable eeprom w rite using programming instruction 4a. 3. load address high byte using programming instruction 4b. 4. load address lo w byte using programming instruction 4c. 5. load data using programming instructions 4d and 4e. 6. repeat steps 4 and 5 for all data bytes in the page. 7. write the data using programming instruction 4f. 8. poll for eeprom w rite complete using programming instruction 4g, or w ait for t wlrh (refer to table 30-13 on page 373 ). 9. repeat steps 3 to 8 until all data ha v e been programmed. note that the prog_pageload instruction can not be used w hen programming the eeprom. 30.9.19 reading the eeprom 1. enter jtag instruction prog_commands. 2. enable eeprom read using programming instruction 5a. 3. load address using programming instructions 5b and 5c. 4. read data using programming instruction 5d. 5. repeat steps 3 and 4 until all data ha v e been read. note that the prog_pageread instruction can not be used w hen reading the eeprom. 30.9.20 programming the fuses 1. enter jtag instruction prog_commands. 2. enable fuse w rite using programming instruction 6a. 3. load data high byte using programming instructions 6b. a bit v alue of ?0? w ill program the corresponding fuse, a ?1? w ill un-program the fuse. 4. write fuse high byte using programming instruction 6c. 5. poll for fuse w rite complete using progra mming instruction 6d, or w ait for t wlrh (refer to table 30-13 on page 373 ). 389 7593l?avr?09/12 at90usb64/128 6. load data lo w byte using programming instructions 6e. a ?0? w ill program the fuse, a ?1? w ill unprogram the fuse. 7. write fuse lo w byte using programming instruction 6f. 8. poll for fuse w rite complete using progra mming instruction 6g, or w ait for t wlrh (refer to table 30-13 on page 373 ). 30.9.21 programming the lock bits 1. enter jtag instruction prog_commands. 2. enable lock bit w rite using programming instruction 7a. 3. load data using programming instructions 7b. a bit v alue of ?0? w ill program the corre- sponding lock bit, a ?1? w ill lea v e the lock bit unchanged. 4. write lock bits using programming instruction 7c. 5. poll for lock bit w rite complete using programming instruction 7d, or w ait for t wlrh (refer to table 30-13 on page 373 ). 30.9.22 reading the fuses and lock bits 1. enter jtag instruction prog_commands. 2. enable fuse/lock bit read using programming instruction 8a. 3. to read all fuses and lock bits, use programming instruction 8e. to only read fuse high byte, use programming instruction 8b. to only read fuse lo w byte, use programming instruction 8c. to only read lock bits, use programming instruction 8d. 30.9.23 reading the signature bytes 1. enter jtag instruction prog_commands. 2. enable signature byte read using programming instruction 9a. 3. load address 0x00 using programming instruction 9b. 4. read first signature byte us ing programming instruction 9c. 5. repeat steps 3 and 4 w ith address 0x01 and address 0x02 to read the second and third signature bytes, respecti v ely. 30.9.24 reading the calibration byte 1. enter jtag instruction prog_commands. 2. enable calibration byte read using programming instruction 10a. 3. load address 0x00 using programming instruction 10b. 4. read the calibration byte using programming instruction 10c. 390 7593l?avr?09/12 at90usb64/128 31. electrical characterist ics for atmel at90usb64/128 31.1 absolute maximum ratings * 31.2 dc characteristics operating temperature..................................... -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature...................................... -65c to +150c voltage on any pin except reset and vbus w ith respect to ground (7) .............................-0.5v to v cc +0.5v voltage on reset w ith respect to ground ......-0.5v to +13.0v voltage on vbus w ith respect to ground...........-0.5v to +6.0v maximum operating v oltage............................................ +6.0v dc current per i/o pin.................................................. 40.0ma dc current v cc and gnd pins .............. ........... ......... 200.0ma t a = -40 c to 85 c, v cc = 2.7v to 5.5v (unless other w ise noted). symbol parameter condition min. (5) typ. max. (5) units v il input lo w voltage,except xtal1 and reset pin v cc = 2.7v - 5.5v -0.5 0.2v cc (1) v v il1 input lo w voltage, xtal1 pin v cc = 2.7v - 5.5v -0.5 0.1v cc (1) v il2 input lo w voltage, reset pin v cc = 2.7v - 5.5v -0.5 0.1v cc (1) v ih input high voltage, except xtal1 and reset pins v cc = 2.7v - 5.5v 0.6v cc (2) v cc + 0.5 v ih1 input high voltage, xtal1 pin v cc = 2.7v - 5.5v 0.7v cc (2) v cc + 0.5 v ih2 input high voltage, reset pin v cc = 2.7v - 5.5v 0.9v cc (2) v cc + 0.5 v ol output lo w voltage (3) i ol = 10ma, v cc = 5v i ol = 5ma, v cc = 3v 0.3 0.2 0.7 0.5 v oh output high voltage (4) i oh = -20ma, v cc = 5v i oh = -10ma, v cc = 3v 4.2 2.3 4.5 2.6 i il input leakage current i/o pin v cc = 5.5v, pin lo w (absolute v alue) 1 a i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute v alue) 1 r rst reset pull-up resistor 30 60 k r pu i/o pin pull-up resistor 20 50 391 7593l?avr?09/12 at90usb64/128 note: 1. "max" means the highest v alue w here the pin is guaranteed to be read as lo w 2. "min" means the lo w est v alue w here the pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), the follo w ing must be obser v ed: atmel at90usb64/128: 1.)the sum of all iol, for ports a0-a7, g2, c4-c7 should not exceed 100ma. 2.)the sum of all iol, for ports c0-c3, g0-g1, d0-d7 should not exceed 100ma. 3.)the sum of all iol, for ports g3-g5, b0-b7, e0-e7 should not exceed 100ma. 4.)the sum of all iol, for ports f0-f7 should not exceed 100ma. if iol exceeds the test condition, vol may exceed the related sp ecification. pins are not guar anteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), the follo w ing must be obser v ed: at90usb64/128: 1)the sum of all ioh, for ports a0-a7, g2, c4-c7 should not exceed 100ma. 2)the sum of all ioh, for ports c0-c3, g0-g1, d0-d7 should not exceed 100ma. 3)the sum of all ioh, for ports g3-g5, b0-b7, e0-e7 should not exceed 100ma. 4)the sum of all ioh, for ports f0-f7 should not exceed 100ma. 5. all dc characteristics contained in this datasheet are based on simulation and characterization of other avr microcon- trollers manufactured in the same process technology. these v alues are preliminary v alues representing design targets, and w ill be updated after characterization of actual silicon 6. values w ith ?prr1 ? po w er reduction register 1? disabled (0x00). i cc po w er supply current (6) acti v e 4mhz, v cc = 3v (at90usb64/128) 2.5 5 ma acti v e 8mhz, v cc = 3v (at90usb64/128) 510 acti v e 8mhz, v cc = 5v (at90usb64/128) 10 18 acti v e 16mhz, v cc = 5v (at90usb64/128) 19 30 icc po w er-do w n mode wdt enabled, bod enabled, v cc = 3v, 25c 30 a wdt enabled, bod disabled, v cc = 3v, 25c 10 wdt disabled, bod disabled, v cc = 3v, 25c 2 v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 10 40 mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acid analog comparator propagation delay v cc = 2.7v v cc = 4.0v 750 500 ns iq usb regulator quiescent current uv cc >3.6v, i = 0ma 10 30 a vusb usb regulator output voltage (ucap) uv cc >3.6v, i = 40ma (8) 3.0 3.3 3.5 v t a = -40 c to 85 c, v cc = 2.7v to 5.5v (unless other w ise noted). (continued) symbol parameter condition min. (5) typ. max. (5) units 392 7593l?avr?09/12 at90usb64/128 7. as specified on the usb electrical chapter of usb specifications 2.0, the d+/d- pads can w ithstand v oltages do w n to -1v applied through a 39 resistor 8. usb peripheral consumes up to 50ma from the regulator or uv cc pin w hen usb is used at full-load 31.3 external clock drive waveforms figure 31-1. external clock dri v e w a v eforms. 31.4 external clock drive note: all dc characteristics contained in this datasheet are based on simulation and characterization of other avr microcontrollers manufactured in the same process technology. these v alues are pre- liminary v alues representing design targets, and w ill be updated after characterization of actual silicon. 31.5 maximum speed vs. v cc maximum frequency is depending on v cc. as sho w n in figure 31-2 on page 393 , the maximum frequency v s. v cc cur v e is linear bet w een 2.7v < v cc < 5.5v. v il1 v ih1 table 31-1. external clock dri v e. symbol parameter v cc =1.8-5.5v v cc =2.7-5.5v v cc =4.5-5.5v units min. max. min. max. min. max. 1/t clcl oscillator frequency 0208016mhz t clcl clock period 500 125 62.5 ns t chcx high time 200 50 25 t clcx lo w time 200 50 25 t clch rise time 2.0 1.6 0.5 s t chcl fall time 2.0 1.6 0.5 t clcl change in period from one clock cycle to the next 22 2% 393 7593l?avr?09/12 at90usb64/128 figure 31-2. maximum frequency v s. v cc , atmel at90usb64/128. 31.6 2-wire serial inte rface characteristics table 31-2 describes the requirements for de v ices connected to the 2- w ire serial bus. the at90usb64/128 2- w ire serial interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 31-3 on page 394 . 16mhz 8mhz table 31-2. 2- w ire serial bus requirements. symbol parameter condition min max units vil input lo w - v oltage -0.5 0.3 v cc v vih input high- v oltage 0.7 v cc v cc + 0.5 vhys (1) hysteresis of schmitt trigger inputs 0.05 v cc (2) ? vol (1) output lo w - v oltage 3ma sink current 0 0.4 tr (1) rise time for both sda and scl 20 + 0.1c b (3)(2) 300 ns tof (1) output fall time from v ihmin to v ilmax 10pf < c b < 400pf (3) 20 + 0.1c b (3)(2) 250 tsp (1) spikes suppressed by input filter 0 50 (2) i i input current each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a c i (1) capacitance for each i/o pin ? 10 pf f scl scl clock frequency f ck (4) > max(16f scl , 250khz) (5) 0 400 khz rp value of pull-up resistor f scl 100khz f scl > 100khz v cc 0.4v ? 3ma ---------------------------- 1000ns c b ------------------- v cc 0.4v ? 3ma ---------------------------- 300ns c b --------------- - 394 7593l?avr?09/12 at90usb64/128 notes: 1. in atmel at90usb64/128, this parameter is characterized and not 100% tested. 2. required only for f scl >100khz. 3. c b = capacitance of one bus line in pf. 4. f ck = cpu clock frequency 5. this requirement applies to all at90usb64/128 2- w ire serial interface operation. other de v ices connected to the 2- w ire serial bus need only obey the general f scl requirement. 6. the actual lo w period generated by the at90usb64/128 2- w ire serial interface is (1/f scl - 2/f ck ), thus f ck must be greater than 6mhz for the lo w time requirement to be strictly met at f scl = 100khz. 7. the actual lo w period generated by the at90usb64/128 2- w ire serial interface is (1/f scl - 2/f ck ), thus the lo w time require- ment w ill not be strictly met for f scl > 308khz w hen f ck = 8mhz. still, at90usb64/128 de v ices connected to the bus may communicate at full speed (400khz) w ith other at90usb64/128 de v ices, as w ell as any other de v ice w ith a proper t low acceptance margin. figure 31-3. 2- w ire serial bus timing. t hd;sta hold time (repeated) start condition f scl 100khz 4.0 ? s f scl > 100khz 0.6 ? t low lo w period of the scl clock f scl 100khz (6) 4.7 ? f scl > 100khz (7) 1.3 ? t high high period of the scl clock f scl 100khz 4.0 ? f scl > 100khz 0.6 ? t su;sta set-up time for a repeated start condition f scl 100khz 4.7 ? f scl > 100khz 0.6 ? t hd;dat data hold time f scl 100khz 0 3.45 f scl > 100khz 0 0.9 t su;dat data setup time f scl 100khz 250 ? ns f scl > 100khz 100 ? t su;sto setup time for stop condition f scl 100khz 4.0 ? s f scl > 100khz 0.6 ? t buf bus free time bet w een a stop and start condition f scl 100khz 4.7 ? f scl > 100khz 1.3 ? table 31-2. 2- w ire serial bus requirements. (continued) symbol parameter condition min max units t su;sta t low t high t low t of t hd;sta t hd;dat t su;dat t su;sto t buf scl sda t r 395 7593l?avr?09/12 at90usb64/128 31.7 spi timing characteristics see figure 31-4 and figure 31-5 on page 396 for details. note: 1. in spi programming mode the minimum sck high/lo w period is: - 2 t clcl for f ck <12mhz - 3 t clcl for f ck >12mhz figure 31-4. spi interface timing requirements (master mode). table 31-3. spi timing parameters. description mode min. typ. max. 1 sck period master see table 18-4 on page 174 ns 2 sck high/lo w master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5 hold master 10 6 out to sck master 0.5 t sck 7 sck to out master 10 8 sck to out high master 10 9ss lo w to out sla v e15 10 sck period sla v e4 t ck 11 sck high/lo w (1) sla v e2 t ck 12 rise/fall time sla v e1.6s 13 setup sla v e10 ns 14 hold sla v et ck 15 sck to out sla v e15 16 sck to ss high sla v e20 17 ss high to tri-state sla v e10 18 ss lo w to sck sla v e20 mo s i (data output) s ck (cpol = 1) mi s o (data input) s ck (cpol = 0) ss m s bl s b l s b m s b ... ... 61 22 3 45 8 7 396 7593l?avr?09/12 at90usb64/128 figure 31-5. spi interface timing requirements (sla v e mode). 31.8 hardware boot entr ance timing characteristics figure 31-6. hard w are boot timing requirements. mi so (data output) s ck (cpol = 1) mo si (data input) s ck (cpol = 0) ss m s bl s b l s b m s b ... ... 10 11 11 12 13 14 17 15 9 x 16 table 31-4. hard w are boot timings. symbol parameter min. max. tshrh hwb lo w setup before reset high 0 thhrh hwb lo w hold after reset high startuptime (sut) + time out delay (tout) reset ale/hwb t shrh t hhrh 397 7593l?avr?09/12 at90usb64/128 31.9 adc characteristics table 31-5. adc characteristics. symbol parameter condition min. typ. max. units resolution single ended con v ersion 10 bits differential con v ersion gain = 1 or 10 8 differential con v ersion gain = 200 7 absolute accuracy (including inl, dnl, quantization error, gain and offset error) single ended con v ersion v ref = 4v, v cc = 4v, adc clock = 200khz 1.5 lsb single ended con v ersion v ref = 4v, v cc = 4v, adc clock = 1mhz single ended con v ersion v ref = 4v, v cc = 4v, adc clock = 200khz noise reduction mode 1.5 single ended con v ersion v ref = 4v, v cc = 4v, adc clock = 1mhz noise reduction mode absolute accuracy gain = 1, 10, 200 v ref = 4v, v cc = 5v adc clock = 50 - 200khz 1 integral non-linearity (inl) single ended con v ersion v ref = 4v, v cc = 4v, adc clock = 200khz 0.5 1 integral non-linearity (inl) (accuracy after calibration for offset and gain error) gain = 1, 10, 200 v ref = 4v, v cc = 5v adc clock = 50 - 200khz 0.5 1 differential non-linearity (dnl) single ended con v ersion v ref = 4v, v cc = 4v, adc clock = 200khz 0.3 1 gain error single ended con v ersion v ref = 4v, v cc = 4v, adc clock = 200khz -2 0 +2 gain = 1, 10, 200 -2 0 +2 offset error single ended con v ersion v ref = 4v, v cc = 4v, adc clock = 200khz -2 1 +2 gain = 1, 10, 200 v ref = 4v, v cc = 5v adc clock = 50 - 200khz -1 0 +1 con v ersion time free running con v ersion 65 260 s clock frequency single ended con v ersion 50 1000 khz 398 7593l?avr?09/12 at90usb64/128 avcc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage single ended con v ersion 2.0 avcc differential con v ersion 2.0 avcc - 0.5 v in input voltage single ended channels 0 v ref differential con v ersion 0 avcc input band w idth single ended channels 38,5 khz differential channels 4 v int1 internal voltage reference 1.1v 1.0 1.1 1.2 v v int2 internal voltage reference 2.56v 2.4 2.56 2.8 r ref reference input resistance 32 k r ain analog input resistance 100 m table 31-5. adc characteristics. (continued) symbol parameter condition min. typ. max. units 399 7593l?avr?09/12 at90usb64/128 31.10 external data memory timing notes: 1. this assumes 50% clock duty cycl e. the half peri od is actually the high time of the external clock, xtal1. 2. this assumes 50% clock duty cycle. the half peri od is actually the lo w time of the external clock, xtal1. table 31-6. external data memory characteristics, 4.5 - 5.5 volts, no w ait-state. symbol parameter 8mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 1t lhll ale pulse width 115 1.0t clcl -10 ns 2t avll address valid a to ale lo w 57.5 0.5t clcl -5 (1) 3a t llax_st address hold after ale lo w , w rite access 55 3b t llax_ld address hold after ale lo w , read access 55 4t avllc address valid c to ale lo w 57.5 0.5t clcl -5 (1) 5t avrl address valid to rd lo w 115 1.0t clcl -10 6t avwl address valid to wr lo w 115 1.0t clcl -10 7t llwl ale lo w to wr lo w 47.5 67.5 0.5t clcl -15 (2) 0.5t clcl +5 (2) 8t llrl ale lo w to rd lo w 47.5 67.5 0.5t clcl -15 (2) 0.5t clcl +5 (2) 9t dvrh data setup to rd high 40 40 10 t rldv read lo w to data valid 75 1.0t clcl -50 11 t rhdx data hold after rd high 0 0 12 t rlrh rd pulse width 115 1.0t clcl -10 13 t dvwl data setup to wr lo w 42.5 0.5t clcl -20 (1) 14 t whdx data hold after wr high 115 1.0t clcl -10 15 t dvwh data valid to wr high 125 1.0t clcl 16 t wlwh wr pulse width 115 1.0t clcl -10 table 31-7. external data memory characteristics, 4.5 - 5.5 volts, 1 cycle w ait-state. symbol parameter 8mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read lo w to data valid 200 2.0t clcl -50 ns 12 t rlrh rd pulse width 240 2.0t clcl -10 15 t dvwh data valid to wr high 240 2.0t clcl 16 t wlwh wr pulse width 240 2.0t clcl -10 400 7593l?avr?09/12 at90usb64/128 table 31-8. external data memory characteristics, 4.5 - 5.5 volts, srwn1 = 1, srwn0 = 0. symbol parameter 4mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read lo w to data valid 325 3.0t clcl -50 ns 12 t rlrh rd pulse width 365 3.0t clcl -10 15 t dvwh data valid to wr high 375 3.0t clcl 16 t wlwh wr pulse width 365 3.0t clcl -10 table 31-9. external data memory characteristics, 4.5 - 5.5 volts, srwn1 = 1, srwn0 = 1. symbol parameter 4mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 16 mhz 10 t rldv read lo w to data valid 325 3.0t clcl -50 ns 12 t rlrh rd pulse width 365 3.0t clcl -10 14 t whdx data hold after wr high 240 2.0t clcl -10 15 t dvwh data valid to wr high 375 3.0t clcl 16 t wlwh wr pulse width 365 3.0t clcl -10 table 31-10. external data memory characteristics, 2.7 - 5.5 volts, no w ait-state. symbol parameter 4mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 8 mhz 1t lhll ale pulse width 235 t clcl -15 ns 2t avll address valid a to ale lo w 115 0.5t clcl -10 (1) 3a t llax_st address hold after ale lo w , w rite access 55 3b t llax_ld address hold after ale lo w , read access 55 4t avllc address valid c to ale lo w 115 0.5t clcl -10 (1) 5t avrl address valid to rd lo w 235 1.0t clcl -15 6t avwl address valid to wr lo w 235 1.0t clcl -15 7t llwl ale lo w to wr lo w 115 130 0.5t clcl -10 (2) 0.5t clcl +5 (2) 8t llrl ale lo w to rd lo w 115 130 0.5t clcl -10 (2) 0.5t clcl +5 (2) 9t dvrh data setup to rd high 45 45 10 t rldv read lo w to data valid 190 1.0t clcl -60 11 t rhdx data hold after rd high 0 0 401 7593l?avr?09/12 at90usb64/128 notes: 1. this assumes 50% clock duty cycl e. the half peri od is actually the high time of the external clock, xtal1. 2. this assumes 50% clock duty cycle. the half peri od is actually the lo w time of the external clock, xtal1. 12 t rlrh rd pulse width 235 1.0t clcl -15 ns 13 t dvwl data setup to wr lo w 105 0.5t clcl -20 (1) 14 t whdx data hold after wr high 235 1.0t clcl -15 15 t dvwh data valid to wr high 250 1.0t clcl 16 t wlwh wr pulse width 235 1.0t clcl -15 table 31-10. external data memory characteristics, 2.7 - 5.5 volts, no w ait-state. (continued) symbol parameter 4mhz oscillator variable oscillator unit min. max. min. max. table 31-11. external data memory characteristics, 2.7 - 5.5 volts, srwn1 = 0, srwn0 = 1. symbol parameter 4mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read lo w to data valid 440 2.0t clcl -60 ns 12 t rlrh rd pulse width 485 2.0t clcl -15 15 t dvwh data valid to wr high 500 2.0t clcl 16 t wlwh wr pulse width 485 2.0t clcl -15 table 31-12. external data memory characteristics, 2.7 - 5.5 volts, srwn1 = 1, srwn0 = 0. symbol parameter 4mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read lo w to data valid 690 3.0t clcl -60 ns 12 t rlrh rd pulse width 735 3.0t clcl -15 15 t dvwh data valid to wr high 750 3.0t clcl 16 t wlwh wr pulse width 735 3.0t clcl -15 table 31-13. external data memory characteristics, 2.7 - 5.5 volts, srwn1 = 1, srwn0 = 1. symbol parameter 4mhz oscillator variable oscillator unit min. max. min. max. 01/t clcl oscillator frequency 0.0 8 mhz 10 t rldv read lo w to data valid 690 3.0t clcl -60 ns 12 t rlrh rd pulse width 735 3.0t clcl -15 14 t whdx data hold after wr high 485 2.0t clcl -15 15 t dvwh data valid to wr high 750 3.0t clcl 16 t wlwh wr pulse width 735 3.0t clcl -15 402 7593l?avr?09/12 at90usb64/128 figure 31-7. external memory timing (srwn1 = 0, srwn0 = 0. figure 31-8. external memory timing (srwn1 = 0, srwn0 = 1). ale t1 t2 t 3 write re a d wr t4 a15:8 addre ss prev. a ddr. da7:0 addre ss d a t a prev. d a t a xx rd da7:0 (xmbk = 0) d a t a addre ss sy s tem clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 1 3 10 11 14 15 9 ale t1 t2 t 3 write re a d wr t5 a15:8 addre ss prev. a ddr. da7:0 addre ss d a t a prev. d a t a xx rd da7:0 (xmbk = 0) d a t a addre ss sy s tem clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 1 3 10 11 14 15 9 t4 403 7593l?avr?09/12 at90usb64/128 figure 31-9. external memory timing (srwn1 = 1, srwn0 = 0). figure 31-10. external memory timing (srwn1 = 1, srwn0 = 1). the ale pulse in the last period (t4-t7) is only present if the next instruction accesses the ram (internal or external). ale t1 t2 t 3 write re a d wr t6 a15:8 addre ss prev. a ddr. da7:0 addre ss d a t a prev. d a t a xx rd da7:0 (xmbk = 0) d a t a addre ss sy s tem clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 1 3 10 11 14 15 9 t4 t5 ale t1 t2 t 3 write re a d wr t7 a15:8 addre ss prev. a ddr. da7:0 addre ss d a t a prev. d a t a xx rd da7:0 (xmbk = 0) d a t a addre ss sy s tem clock (clk cpu ) 1 4 2 7 6 3a 3b 5 8 12 16 1 3 10 11 14 15 9 t4 t5 t6 404 7593l?avr?09/12 at90usb64/128 32. atmel at90usb64/128 typical characteristics the follo w ing charts sho w typical beha v ior. these figures are not tested during manufacturing. all current consumption measurements are performed w ith all i/o pins configured as inputs and w ith internal pull-ups enabled. a sine w a v e generator w ith rail-to-rail output is used as clock source. all acti v e- and idle current consumption measurements are done w ith all bits in the prr regis- ters set and thus, the corresponding i/o modules are turned off. also the analog comparator is disabled during these measurements. the po w er consumption in po w er-do w n mode is independent of clock selection. the current consumption is a function of se v eral factors such as: operating v oltage, operating frequency, loading of i/o pins, s w itching rate of i/o pins, code executed and ambient tempera- ture. the dominating factors are operating v oltage and frequency. the current dra w n from capaciti v e loaded pins may be estimated (for one pin) as c l v cc f w here c l = load capacitance, v cc = operating v oltage and f = a v erage s w itching frequency of i/o pin. the parts are characterized at frequencies higher than test limits. parts are not guaranteed to function properly at frequencies higher than the ordering code indicates. the difference bet w een current consumption in po w er-do w n mode w ith watchdog timer enabled and po w er-do w n mode w ith watchdog timer disabled represents the differential cur- rent dra w n by the watchdog timer. 405 7593l?avr?09/12 at90usb64/128 32.1 input voltage levels figure 32-1. input lo w v oltage v s. v cc , all i/os excluding dp/dm, xtal1 and reset. figure 32-2. input high v oltage v s. v cc , all i/os excluding dp/dm, xtal1 and reset. 0.50 0.75 1.00 1.25 1.50 1.75 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v cc (v) thres hold (v) 85 25 -40 0.50 0.75 1.00 1.25 1.50 1.75 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v cc (v) thres hold (v) 85 25 -40 406 7593l?avr?09/12 at90usb64/128 32.2 output voltage levels figure 32-3. output lo w v oltage v s. output current, all i/os excluding dp/dm, v cc = 3v. figure 32-4. output lo w v oltage v s. output current, all i/os excluding dp/dm, v cc = 5v. 0 0.2 0.4 0.6 0. 8 1.0 1.2 0 5 10 15 20 i ol (ma) v ol (v) 85 25 -40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0 5 10 15 20 i ol (ma) v ol (v) 85 25 -40 407 7593l?avr?09/12 at90usb64/128 figure 32-5. output high v oltage v s. output current, all i/os excluding dp/dm, v cc = 3v. figure 32-6. output high v oltage v s. output current, all i/os excluding dp/dm, v cc = 5v. 1. 8 2.0 2.2 2.4 2.6 2. 8 3.0 0 5 10 15 20 i oh (ma) v oh (v) 85 25 -40 4.2 4.4 4.6 4. 8 5.0 0 5 10 15 20 i oh (ma) v oh (v) 85 25 -40 408 7593l?avr?09/12 at90usb64/128 32.3 power-down supply current figure 32-7. po w er-do w n supply current v s. v cc , w ith bod disabled, wdt disabled, t = 25c. figure 32-8. po w er-do w n supply current v s. v cc , w ith bod disabled, wdt enabled, t = 25c. 0 0.5 1.0 1.5 2.0 2.5 3.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v cc (v) i cc ( a) 0 2 4 6 8 10 12 14 16 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v cc (v) i cc ( a) 409 7593l?avr?09/12 at90usb64/128 figure 32-9. po w er-do w n supply current v s. v cc , w ith bod enabled, wdt enabled, t = 25c. 32.4 power-save supply current figure 32-10. po w er-sa v e supply current v s. v cc , w ith bod & wdt disabled, t = 25c. 0 10 20 30 40 50 60 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v cc (v) i cc ( a) 0 1 2 3 4 5 6 7 8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v cc (v) i cc ( a) 410 7593l?avr?09/12 at90usb64/128 32.5 idle supply current figure 32-11. idle supply current v s. frequency, t = 25c. 32.6 active supply current figure 32-12. acti v e supply current v s. frequency, t = 25c. 0 5 10 15 20 246 8 10 12 14 16 fre q uency (mhz) i cc (ma) 5.5 5.0 4.5 3.3 2.7 0 5 10 15 20 25 246 8 10 12 14 16 fre q uency (mhz) i cc (ma) 5.5 5.0 4.5 3.3 2.7 411 7593l?avr?09/12 at90usb64/128 32.7 reset supply current figure 32-13. reset supply current v s. frequency. 32.8 i/o pull-up current figure 32-14. i/o pull-up current v s. pin v oltage, v cc = 5v. 0 2 4 6 8 10 12 46 8 10 12 14 16 fre q uency (mhz) i cc (ma) 5.5 5.0 4.5 3.3 2.7 -20 0 20 40 60 8 0 100 120 140 012345 v op (v) i op (ua) 85 25 -40 412 7593l?avr?09/12 at90usb64/128 figure 32-15. reset pull-up current v s. pin v oltage, v cc = 5v. 32.9 bandgap voltage figure 32-16. bandgap v oltage v s. temperature. 0 20 40 60 8 0 100 120 012345 v re s et (v) i re s et ( a) 85 25 -40 1.0 8 0 1.0 8 5 1.090 1.095 1.100 1.105 1.110 1.115 -40-30-20-100 10203040506070 8 0 temperature (c) bandgap voltage (v) 5.5 5.0 4.5 4.0 3.6 2.7 413 7593l?avr?09/12 at90usb64/128 32.10 internal aref voltage figure 32-17. internal aref reference v oltage v s. temperature, v cc = 2.7-5.5v. 32.11 usb regulator figure 32-18. usb regulator quiescent current v s. input v oltage, no load. 2.54 2.56 2.5 8 2.60 2.62 2.64 -40 -20 0 20 40 60 8 0 te mpe ra ture (c) tens ion vref inter (v) 0 10 20 30 40 50 60 70 8 0 90 100 3.0 3.5 4.0 4.5 5.0 5.5 6.0 voltage (v) i cc ( a) 414 7593l?avr?09/12 at90usb64/128 figure 32-19. usb regulator output v oltage v s. input v oltage, load = 75 . note: the 75 load is equi v alent to the maximum a v erage consumption of the usb peripheral in opera- tion (full bus load). 32.12 bod levels figure 32-20. bod v oltage (2.4v le v el) v s. temperature. 2.6 2. 8 3.0 3.2 3.4 3.0 3.5 4.0 4.5 5.0 5.5 input voltage (v) output voltage (v) 85 25 -40 2.42 2.44 2.46 2.4 8 2.50 2.52 2.54 -40-30-20-100 10203040506070 8 0 temperature (c) thres hold (v) rising vcc falling vcc 415 7593l?avr?09/12 at90usb64/128 figure 32-21. bod v oltage (3.4v le v el) v s. temperature. figure 32-22. bod v oltage (4.3v le v el) v s. temperature. 3.42 3.44 3.46 3.4 8 3.50 3.52 3.54 3.56 -40-30-20-100 10203040506070 8 0 temperature (c) thres hold (v) rising vcc falling vcc 4.34 4.36 4.3 8 4.40 4.42 4.44 4.46 4.4 8 4.50 -40-30-20-100 10203040506070 8 0 temperature (c) thres hold (v) rising vcc falling vcc 416 7593l?avr?09/12 at90usb64/128 32.13 watchdog timer frequency figure 32-23. wdt oscillator frequency v s. v cc . 32.14 internal rc osci llator frequency figure 32-24. rc oscillator frequency v s. osccal, t = 25c. 10 8 110 112 114 116 11 8 120 122 124 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v cc (v) f rc (khz) 85 25 -40 2 4 6 8 10 12 14 16 -1 15 31 47 63 79 95 111 127 143 159 175 191 207 223 239 255 o s ccal (x1) f rc (mhz) 417 7593l?avr?09/12 at90usb64/128 figure 32-25. rc oscillator frequency v s. v cc . figure 32-26. rc oscillator frequency v s. temperature. 7. 8 7.9 8 .0 8 .1 8 .2 8 .3 8 .4 8 .5 8 .6 8 .7 8 . 8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 v cc (v) f rc (mhz) 85 25 -40 7. 8 8 .0 8 .2 8 .4 8 .6 8 . 8 -40 -30 -20 -10 0 10 20 30 40 50 60 70 8 0 te mpe ra ture (c) f rc (mhz) 5.5 4.0 3.3 3.0 2.7 418 7593l?avr?09/12 at90usb64/128 32.15 power-on reset figure 32-27. po w er-on reset le v el v s. temperature. 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 -40-30-20-100 10203040506070 8 0 te mpe ra ture (c) por voltage (v) 419 7593l?avr?09/12 at90usb64/128 33. register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reser v ed - - - - - - - - (0xfe) reser v ed - - - - - - - - (0xfd) reser v ed - - - - - - - - (0xfc) reser v ed - - - - - - - - (0xfb) reser v ed - - - - - - - - (0xfa) reser v ed - - - - - - - - (0xf9) otgtcon page value (0xf8) upint pint7:0 (0xf7) upbchx - - - - - pbyct10:8 (0xf6) upbclx pbyct7:0 (0xf5) uperrx - counter1:0 crc16 timeout pid datapid datatgl (0xf4) ueint epint6:0 (0xf3) uebchx - - - - -byct10:8 (0xf2) uebclx byct7:0 (0xf1) uedatx dat7:0 (0xf0) ueienx flerre nakine - nakoute rxstpe rxoute stallede txine (0xef) uesta1x - - - - - ctrldir currbk1:0 (0xee) uesta0x cfgok overfi underfi - dtseq1:0 nbusybk1:0 (0xed) uecfg1x epsize2:0 epbk1:0 alloc (0xec) uecfg0x eptype1:0 - - epdir (0xeb) ueconx stallrq stallrqc rstdt epen (0xea) uerst eprst6:0 (0xe9) uenum epnum2:0 (0xe8) ueintx fifocon nakini rwal na kouti rxstpi rxouti stalledi txini (0xe7) reser v ed - - - - (0xe6) udmfn fncerr (0xe5) udfnumh fnum10:8 (0xe4) udfnuml fnum7:0 (0xe3) udaddr adden uadd6:0 (0xe2) udien uprsme eorsme wakeupe eorste sofe suspe (0xe1) udint uprsmi eorsmi wakeupi eorsti sofi suspi (0xe0) udcon lsm rmwkup detach (0xdf) otgint stoi hnperri roleexi bcerri vberri srpi (0xde) otgien stoe hnperre roleex e bcerre vberre srpe (0xdd) otgcon hnpreq srpreq srpsel vbu shwc vbusreq vbusrqc (0xdc) reser v ed (0xdb) reser v ed (0xda) usbint idti vbusti (0xd9) usbsta speed id vbus (0xd8) usbcon usbe host frzclk otgpade idte vbuste (0xd7) uhwcon uimod uide uvcone uvrege (0xd6) reser v ed (0xd5) reser v ed (0xd4) reser v ed (0xd3) reser v ed (0xd2) reser v ed - - - - - - - - (0xd1) reser v ed - - - - - - - - (0xd0) reser v ed - - - - - - - - (0xcf) reser v ed - - - - - - - - (0xce) udr1 usart1 i/o data register (0xcd) ubrr1h - - - - usart1 baud rate register high byte (0xcc) ubrr1l usart1 baud rate register lo w byte (0xcb) reser v ed - - - - - - - - (0xca) ucsr1c umsel11 umsel10 upm1 1 upm10 usbs1 ucsz11 ucsz10 ucpol1 (0xc9) ucsr1b rxcie1 txcie1 udrie 1 rxen1 txen1 ucsz12 rxb81 txb81 (0xc8) ucsr1a rxc1 txc1 udre1 fe1 dor1 pe1 u2x1 mpcm1 (0xc7) reser v ed - - - - - - - - (0xc6) reser v ed - - - - - - - - (0xc5) reser v ed - - - - - - - - (0xc4) reser v ed - - - - - - - - (0xc3) reser v ed - - - - - - - - (0xc2) reser v ed - - - - - - - - (0xc1) reser v ed - - - - - - - - (0xc0) reser v ed - - - - - - - - (0xbf) reser v ed - - - - - - - - 420 7593l?avr?09/12 at90usb64/128 (0xbe) reser v ed - - - - - - - - (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 twam0 - (0xbc) twcr twint twea twsta twsto twwc twen -twie (0xbb) twdr 2- w ire serial interface data register (0xba) twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce (0xb9) twsr tws7 tw s6 tws5 tws4 tws3 - twps1 twps0 (0xb8) twbr 2- w ire serial interface bit rate register (0xb7) reser v ed - - - - - - - - (0xb6) assr - exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub (0xb5) reser v ed - - - - - - - - (0xb4) ocr2b timer/counter2 output compare register b (0xb3) ocr2a timer/counter2 output compare register a (0xb2) tcnt2 timer/counter2 (8 bit) (0xb1) tccr2b foc2a foc2b - - wgm22 cs22 cs21 cs20 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 - -wgm21wgm20 (0xaf) updatx pdat7:0 (0xae) upienx flerre nakede - perre txstpe txoute rxstalle rxine (0xad) upcfg2x intfrq7:0 (0xac) upstax cfgok overfi underfi dtseq1:0 nbusybk1:0 (0xab) upcfg1x psize2:0 pbk1:0 alloc (0xaa) upcfg0x ptype1:0 ptoken1:0 pepnum3:0 (0xa9) upconx pfreeze inmode rstdt pen (0xa8) uprst prst6:0 (0xa7) upnum pnum2:0 (0xa6) upintx fifocon nakedi rwal perri txstpi txouti rxstalli rxini (0xa5) upinrqx inrq7:0 (0xa4) uhflen flen7:0 (0xa3) uhfnumh fnum10:8 (0xa2) uhfnuml fnum7:0 (0xa1) uhaddr hadd6:0 (0xa0) uhien hwupe hsofe rxrsme rsmede rste ddisce dconne (0x9f) uhint hwupi hsofi rxrs mi rsmedi rsti ddisci dconni (0x9e) uhcon resume reset sofen (0x9d) ocr3ch timer/counter3 - output compare register c high byte (0x9c) ocr3cl timer/counter3 - output compare register c lo w byte (0x9b) ocr3bh timer/counter3 - output compare register b high byte (0x9a) ocr3bl timer/counter3 - output compare register b lo w byte (0x99) ocr3ah timer/counter3 - output compare register a high byte (0x98) ocr3al timer/counter3 - output compare register a lo w byte (0x97) icr3h timer/counter3 - input capture register high byte (0x96) icr3l timer/counter3 - input capture register lo w byte (0x95) tcnt3h timer/counter3 - counter register high byte (0x94) tcnt3l timer/counter3 - counter register lo w byte (0x93) reser v ed - - - - - - - - (0x92) tccr3c foc3a foc3b foc3c - - - - - (0x91) tccr3b icnc3 ices3 - wgm33 wgm32 cs32 cs31 cs30 (0x90) tccr3a com3a1 com3a0 com3b1 com3b0 com3c1 com3c0 wgm31 wgm30 (0x8f) reser v ed - - - - - - - - (0x8e) reser v ed - - - - - - - - (0x8d) ocr1ch timer/counter1 - output compare register c high byte (0x8c) ocr1cl timer/counter1 - output compare register c lo w byte (0x8b) ocr1bh timer/counter1 - output compare register b high byte (0x8a) ocr1bl timer/counter1 - output compare register b lo w byte (0x89) ocr1ah timer/counter1 - output compare register a high byte (0x88) ocr1al timer/counter1 - output compare register a lo w byte (0x87) icr1h timer/counter1 - input capture register high byte (0x86) icr1l timer/counter1 - input capture register lo w byte (0x85) tcnt1h timer/counter1 - counter register high byte (0x84) tcnt1l timer/counter1 - counter register lo w byte (0x83) reser v ed - - - - - - - - (0x82) tccr1c foc1a foc1b foc1c - - - - - (0x81) tccr1b icnc1 ices1 - wgm13 wgm12 cs12 cs11 cs10 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 com1c1 com1c0 wgm11 wgm10 (0x7f) didr1 - - - - - -ain1dain0d (0x7e) didr0 adc7d adc6d adc5d adc4d adc3d adc2d adc1d adc0d (0x7d) - - - - - - - - - address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 421 7593l?avr?09/12 at90usb64/128 (0x7c) admux refs1 refs0 adlar mux4 mux3 mux2 mux1 mux0 (0x7b) adcsrb adhsm acme - - - adts2 adts1 adts0 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 (0x79) adch adc data register high byte (0x78) adcl adc data register lo w byte (0x77) reser v ed - - - - - - - - (0x76) reser v ed - - - - - - - - (0x75) xmcrb xmbk - - - - xmm2 xmm1 xmm0 (0x74) xmcra sre srl2 srl1 srl0 srw11 srw10 srw01 srw00 (0x73) reser v ed - - - - - - - - (0x72) reser v ed - - - - - - - - (0x71) timsk3 - -icie3 - ocie3c ocie3b ocie3a toie3 (0x70) timsk2 - - - - - ocie2b ocie2a toie2 (0x6f) timsk1 - -icie1 - ocie1c ocie1b ocie1a toie1 (0x6e) timsk0 - - - - - ocie0b ocie0a toie0 (0x6d) reser v ed - - - - - - - - (0x6c) reser v ed - - - - - - - - (0x6b) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 (0x6a) eicrb isc71 isc70 isc61 isc60 isc51 isc50 isc41 isc40 (0x69) eicra isc31 isc30 isc21 isc20 isc11 isc10 isc01 isc00 (0x68) pcicr - - - - - - -pcie0 (0x67) reser v ed - - - - - - - - (0x66) osccal oscillator calibration register (0x65) prr1 prusb - - -prtim3 - - prusart1 (0x64) prr0 prtwi prtim2 prtim0 -prtim1prspi - pradc (0x63) reser v ed - - - - - - - - (0x62) reser v ed - - - - - - - - (0x61) clkpr clkpce - - - clkps3 clkps2 clkps1 clkps0 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 0x3f (0x5f) sreg i t h s v n z c 0x3e (0x5e) sph sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 0x3c (0x5c) reser v ed - - - - - - - - 0x3b (0x5b) rampz - - - - - - rampz1 rampz0 0x3a (0x5a) reser v ed - - - - - - - - 0x39 (0x59) reser v ed - - - - - - - - 0x38 (0x58) reser v ed - - - - - - - - 0x37 (0x57) spmcsr spmie rwwsb sigrd rwwsre blbset pgwrt pgers spmen 0x36 (0x56) reser v ed - - - - - - - - 0x35 (0x55) mcucr jtd - -pud - - ivsel ivce 0x34 (0x54) mcusr - - - jtrf wdrf borf extrf porf 0x33 (0x53) smcr - - - - sm2 sm1 sm0 se 0x32 (0x52) reser v ed - - - - - - - - 0x31 (0x51) ocdr/ mondr ocdr7 ocdr6 ocdr5 ocdr4 ocdr3 ocdr2 ocdr1 ocdr0 monitor data register 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 0x2f (0x4f) reser v ed - - - - - - - - 0x2e (0x4e) spdr spi data register 0x2d (0x4d) spsr spif wcol - - - - - spi2x 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 0x2b (0x4b) gpior2 general purpose i/o register 2 0x2a (0x4a) gpior1 general purpose i/o register 1 0x29 (0x49) pllcsr - - - pllp2 pllp1 pllp0 plle plock 0x28 (0x48) ocr0b timer/counter0 output compare register b 0x27 (0x47) ocr0a timer/counter0 output compare register a 0x26 (0x46) tcnt0 timer/counter0 (8 bit) 0x25 (0x45) tccr0b foc0a foc0b - - wgm02 cs02 cs01 cs00 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 - -wgm01wgm00 0x23 (0x43) gtccr tsm - - - - - psrasy psrsync 0x22 (0x42) eearh - - - - eeprom address register high byte 0x21 (0x41) eearl eeprom address register lo w byte 0x20 (0x40) eedr eeprom data register 0x1f (0x3f) eecr - - eepm1 eepm0 eerie eempe eepe eere 0x1e (0x3e) gpior0 general purpose i/o register 0 0x1d (0x3d) eimsk int7 int6 int5 int4 int3 int2 int1 int0 0x1c (0x3c) eifr intf7 intf6 intf5 intf4 intf3 intf2 intf1 intf0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 422 7593l?avr?09/12 at90usb64/128 note: 1. for compatibility w ith future de v ices, reser v ed bits should be w ritten to zero if accessed. reser v ed i/o memory addresses should ne v er be w ritten. 2. i/o registers w ithin the address range $00 - $1f are directly bit-accessible using the sbi and cbi instructions. in these reg- isters, the v alue of single bits can be checked by using the sbis and sbic instructions. 3. some of the status flags are cleared by w riting a logical one to them. note that the cbi and sbi instructions w ill operate on all bits in the i/o register, w riting a one back into any flag read as set, thus clearing the flag. the cbi and sbi instructions w ork w ith registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses $00 - $3f must be used. when addressing i/o regis- ters as data space using ld and st instructions, $20 mu st be added to these addresses. the atmel at90usb64/128 is a complex microcontroller w ith more peripheral units than can be supported w ithin the 64 location reser v ed in opcode for the in and out instructions. for the extended i/o space from $60 - $1ff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 0x1b (0x3b) pcifr - - - - - - -pcif0 0x1a (0x3a) reser v ed - - - - - - - - 0x19 (0x39) reser v ed - - - - - - - - 0x18 (0x38) tifr3 - -icf3 - ocf3c ocf3b ocf3a tov3 0x17 (0x37) tifr2 - - - - - ocf2b ocf2a tov2 0x16 (0x36) tifr1 - -icf1 - ocf1c ocf1b ocf1a tov1 0x15 (0x35) tifr0 - - - - - ocf0b ocf0a tov0 0x14 (0x34) reser v ed - - - - - - - - 0x13 (0x33) reser v ed - - - - - - - - 0x12 (0x32) reser v ed - - - - - - - - 0x11 (0x31) portf portf7 portf6 portf5 portf4 portf3 portf2 portf1 portf0 0x10 (0x30) ddrf ddf7 ddf6 ddf5 ddf4 ddf3 ddf2 ddf1 ddf0 0x0f (0x2f) pinf pinf7 pinf6 pinf5 pinf4 pinf3 pinf2 pinf1 pinf0 0x0e (0x2e) porte porte7 porte6 porte 5 porte4 porte3 porte2 porte1 porte0 0x0d (0x2d) ddre dde7 dde6 dde5 dde4 dde3 dde2 dde1 dde0 0x0c (0x2c) pine pine7 pine6 pine5 pine4 pine3 pine2 pine1 pine0 0x0b (0x2b) portd portd7 portd6 portd 5 portd4 portd3 portd2 portd1 portd0 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 0x09 (0x29) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 0x08 (0x28) portc portc7 portc6 portc5 portc4 portc3 portc2 portc1 portc0 0x07 (0x27) ddrc ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 0x06 (0x26) pinc pinc7 pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 0x05 (0x25) portb portb7 portb6 portb 5 portb4 portb3 portb2 portb1 portb0 0x04 (0x24) ddrb ddb7 ddb6 d db5 ddb4 ddb3 ddb2 ddb1 ddb0 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 0x02 (0x22) porta porta7 porta6 porta 5 porta4 porta3 porta2 porta1 porta0 0x01 (0x21) ddra dda7 dda6 d da5 dda4 dda3 dda2 dda1 dda0 0x00 (0x20) pina pina7 pina6 pina5 pina4 pina3 pina2 pina1 pina0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page 423 7593l?avr?09/12 at90usb64/128 34. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add t w o registers rd rd + rr z,c,n,v,h 1 adc rd, rr add w ith carry t w o registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract t w o registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract w ith carry t w o registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract w ith carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusi v e or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd t w o?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed w ith unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed w ith unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relati v e jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 eijmp extended indirect jump to (z) pc (eind:z) none 2 jmp k direct jump pc knone3 rcall k relati v e subroutine call pc pc + k + 1 none 4 icall indirect call to (z) pc znone4 eicall extended indirect call to (z) pc (eind:z) none 4 call k direct subroutine call pc knone5 ret subroutine return pc stack none 5 reti interrupt return pc stack i 5 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare w ith carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register w ith immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 sbrs rr, b skip if bit in regi ster is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lo w er if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if o v erflo w flag is set if (v = 1) then pc pc + k + 1 none 1/2 424 7593l?avr?09/12 at90usb64/128 brvc k branch if o v erflo w flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1none2 cbi p,b clear bit in i/o register i/o(p,b) 0none2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd s w ap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1 sreg(s) 1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) tnone1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negati v e flag n 1n1 cln clear negati v e flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set t w os complement o v erflo w .v 1v1 clv clear t w os complement o v erflo w v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr mo v e bet w een registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd knone1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect w ith displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect w ith displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect w ith displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect w ith displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (z) none 3 elpm rd, z+ extended load program memory rd (rampz:z), rampz:z rampz:z+1 none 3 mnemonics operands description operation flags #clocks 425 7593l?avr?09/12 at90usb64/128 spm store program memory (z) r1:r0 none - in rd, p in port rd pnone1 out p, rr out port p rr none 1 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a mnemonics operands description operation flags #clocks 426 7593l?avr?09/12 at90usb64/128 35. ordering information 35.1 atmel at90usb646 notes: 1. this de v ice can also be supplied in w afer form. please contact your local atmel sales office for detailed ordering information and minimum quantities. 2. pb-free packaging complies to the european directi v e for restriction of hazardous substances (rohs directi v e). also halide free and fully green. 3. see ?maximum speed v s. vcc? on page 392 . speed [mhz] power supply [v] ordering code (2) usb interface package (1) operating range 16 (3) 2.7-5.5 AT90USB646-AU at90usb646-mu de v ice md ps industrial (-40 to +85c) md 64 - lead, 14 14mm body size, 1.0mm body thickness 0.8mm lead pitch, thin profile plastic quad flat package (tqfp) ps 64 - lead, 9 9mm body size, 0.50mm pitch quad flat no lead package (qfn) 427 7593l?avr?09/12 at90usb64/128 35.2 atmel at90usb647 notes: 1. this de v ice can also be supplied in w afer form. please contact your local atmel sales office for detailed ordering information and minimum quantities. 2. pb-free packaging complies to the european directi v e for restriction of hazardous substances (rohs directi v e). also halide free and fully green. 3. see ?maximum speed v s. vcc? on page 392 . speed [mhz] power supply [v] ordering code (2) usb interface package (1) operating range 16 (3) 2.7-5.5 at90usb647-au at90usb647-mu usb otg md ps industrial (-40 to +85c) md 64 - lead, 14 14mm body size, 1.0mm body thickness 0.8mm lead pitch, thin profile plastic quad flat package (tqfp) ps 64 - lead, 9 9mm body size, 0.50mm pitch quad flat no lead package (qfn) 428 7593l?avr?09/12 at90usb64/128 35.3 atmel at90usb1286 notes: 1. this de v ice can also be supplied in w afer form. please contact your local atmel sales office for detailed ordering information and minimum quantities. 2. pb-free packaging complies to the european directi v e for restriction of hazardous substances (rohs directi v e). also halide free and fully green. 3. see ?maximum speed v s. vcc? on page 392 . speed [mhz] power supply [v] ordering code (2) usb interface package (1) operating range 16 (3) 2.7-5.5 at90usb1286-au at90usb1286-mu de v ice md ps industrial (-40 to +85c) md 64 - lead, 14 14mm body size, 1.0mm body thickness 0.8mm lead pitch, thin profile plastic quad flat package (tqfp) ps 64 - lead, 9 9mm body size, 0.50mm pitch quad flat no lead package (qfn) 429 7593l?avr?09/12 at90usb64/128 35.4 atmel at90usb1287 notes: 1. this de v ice can also be supplied in w afer form. please contact your local atmel sales office for detailed ordering information and minimum quantities. 2. pb-free packaging complies to the european directi v e for restriction of hazardous substances (rohs directi v e). also halide free and fully green. 3. see ?maximum speed v s. vcc? on page 392 . speed [mhz] power supply [v] ordering code (2) usb interface package (1) operating range 16 (3) 2.7-5.5 at90usb1287-au at90usb1287-mu host (otg) md ps industrial (-40 to +85c) md 64 - lead, 14 14mm body size, 1.0mm body thickness 0.8mm lead pitch, thin profile plastic quad flat package (tqfp) ps 64 - lead, 9 9mm body size, 0.50mm pitch quad flat no lead package (qfn) 430 7593l?avr?09/12 at90usb64/128 36. packaging information 36.1 tqfp64 431 7593l?avr?09/12 at90usb64/128 432 7593l?avr?09/12 at90usb64/128 36.2 qfn64 433 7593l?avr?09/12 at90usb64/128 434 7593l?avr?09/12 at90usb64/128 37. errata 37.1 atmel at90usb1287/6 errata 37.1.1 at90usb1287/6 errata history notes: 1. a blank or any alphanumeric string. 37.1.2 at90usb1287/6 first release ? incorrect cpu beha v ior for vbusti and idti interrupts routines ? usb eye diagram v iolation in lo w -speed mode ? transient perturbation in usb suspend mode generates o v er consumption ? vbus session v alid threshold v oltage ? usb signal rate ? vbus residual le v el ? spike on twi pins w hen twi is enabled ? high current consumption in sleep mode ? async timer interrupt w ake up from sleep generate multiple interrupts 9. incorrect cpu behavior for vbusti and idti interrupts routines the cpu core may incorrectly execute the interrupt v ector related to the vbusti and idti interrupt flags. problem fix/workaround do not enable these interrupts, firm w are must process these usb e v ents by polling vbusti and idti flags. 8. usb eye diagram violation in low-speed mode the lo w to high transition of d- v iolates the usb eye diagram specification w hen transmitting w ith lo w -speed signaling. problem fix/workaround none. 7. transient perturbation in usb suspend mode generates overconsumption in de v ice mode and w hen the usb is suspended, transient perturbation recei v ed on the usb lines generates a w ake up state. ho w e v er the idle state follo w ing the perturbation does silicon release 90usb1286-16mu 90usb1287-16au 90usb1287-16mu first release date code up to 0648 date code up to 0714 and lots 0735 6h2726 (1) date code up to 0701 second release date code from 0709 to 0801 except lots 0801 7h5103 (1) from date code 0722 to 0806 except lots 0735 6h2726 (1) date code from 0714 to 0810 except lots 0748 7h5103 (1) third release lots 0801 7h5103 (1) and date code from 0814 date code from 0814 lots 0748 7h5103 (1) and date code from 0814 fourth release tbd tbd tbd 435 7593l?avr?09/12 at90usb64/128 not set the suspi bit anymore. the internal usb engine remains in suspend mode but the usb differential recei v er is still enabled and generates a typical 300a extra-po w er con- sumption. detection of the suspend state after the transient perturbation should be performed by soft w are (instead of reading the suspi bit). problem fix/workaround usb w ai v er allo w s bus po w ered de v ices to consume up to 2.5ma in suspend state. 6. vbus session valid threshold voltage the vsession v alid threshold v oltage is internally connected to vbus_valid (4.4v approx.). that causes the de v ice to attach to the bus only w hen vbus is greater than vbusvalid instead of v_session valid . thus if vbus is lo w er than 4.4v, the de v ice is detached. problem fix/workaround according to the usb po w er drop budget, this may require connecting the de v ice toa root hub or a self-po w ered hub. 5. ubs signal rate the a v erage usb signal rate may sometime be measured out of the usb specifications (12mhz 30khz) w ith short frames. when measured on a long period, the a v erage signal rate v alue complies w ith the specifications. this bit rate de v iation does not generates com- munication or functional errors. problem fix/workaround none. 4. vbus residual level in usb de v ice and host mode, once a 5v le v el has been detected to the vbus pad, a resid- ual le v el (about 3v) can be measured on the vbus pin. problem fix/workaround none. 3. spike on twi pins when twi is enabled 100ns negati v e spike occurs on sda and scl pins w hen twi is enabled. problem fix/workaround no kno w n w orkaround, enable atmel at90usb64/128 twi first v ersus the others nodes of the twi net w ork. 2. high current consumption in sleep mode if a pending interrupt cannot w ake the part up from the selected mode, the current consump- tion w ill increase during sleep w hen executing the sleep instruction directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to w ake up the part from the sleep mode should be disabled. 436 7593l?avr?09/12 at90usb64/128 1. asynchronous timer interrupt wake up from sleep generates multiple interrupts if the cpu core is in sleep and w akes-up from an asynchronous timer interrupt and then go back in sleep again it may w ake up multiple times. problem fix/workaround a soft w are w orkaround is to w ait w ith performing the sleep instruction until tcnt2>ocr2+1. 437 7593l?avr?09/12 at90usb64/128 37.1.3 atmel at90usb1287/6 second release ? incorrect cpu beha v ior for vbusti and idti interrupts routines ? usb eye diagram v iolation in lo w -speed mode ? transient perturbation in usb suspend mode generates o v er consumption ? vbus session v alid threshold v oltage ? spike on twi pins w hen twi is enabled ? high current consumption in sleep mode ? async timer interrupt w ake up from sleep generate multiple interrupts 7. incorrect cpu behavior for vbusti and idti interrupts routines the cpu core may incorrectly execute the interrupt v ector related to the vbusti and idti interrupt flags. problem fix/workaround do not enable these interrupts, firm w are must process these usb e v ents by polling vbusti and idti flags. 6. usb eye diagram violation in low-speed mode the lo w to high transition of d- v iolates the usb eye diagram specification w hen transmitting w ith lo w -speed signaling. problem fix/workaround none. 5. transient perturbation in usb suspend mode generates overconsumption in de v ice mode and w hen the usb is suspended, transient perturbation recei v ed on the usb lines generates a w ake up state. ho w e v er the idle state follo w ing the perturbation does not set the suspi bit anymore. the internal usb engine remains in suspend mode but the usb differential recei v er is still enabled and generates a typical 300a extra-po w er con- sumption. detection of the suspend state after the transient perturbation should be performed by soft w are (instead of reading the suspi bit). problem fix/workaround usb w ai v er allo w s bus po w ered de v ices to consume up to 2.5ma in suspend state. 4. vbus session valid threshold voltage the vsession v alid threshold v oltage is internally connected to vbus_valid (4.4v approx.). that causes the de v ice to attach to the bus only w hen vbus is greater than vbusvalid instead of v_session valid . thus if vbus is lo w er than 4.4v, the de v ice is detached. problem fix/workaround according to the usb po w er drop budget, this may require connecting the de v ice toa root hub or a self-po w ered hub. 3. spike on twi pins when twi is enabled 100ns negati v e spike occurs on sda and scl pins w hen twi is enabled. 438 7593l?avr?09/12 at90usb64/128 problem fix/workaround no kno w n w orkaround, enable atmel at90usb64/128 twi first v ersus the others nodes of the twi net w ork. 2. high current consumption in sleep mode if a pending interrupt cannot w ake the part up from the selected mode, the current consump- tion w ill increase during sleep w hen executing the sleep instruction directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to w ake up the part from the sleep mode should be disabled. 1. asynchronous timer interrupt wake up from sleep generates multiple interrupts if the cpu core is in sleep and w akes-up from an asynchronous timer interrupt and then go back in sleep again it may w ake up multiple times. problem fix/workaround a soft w are w orkaround is to w ait w ith performing the sleep instruction until tcnt2>ocr2+1. 439 7593l?avr?09/12 at90usb64/128 37.1.4 atmel at90usb1287/6 third release ? incorrect cpu beha v ior for vbusti and idti interrupts routines ? transient perturbation in usb suspend mode generates o v er consumption ? spike on twi pins w hen twi is enabled ? high current consumption in sleep mode ? async timer interrupt w ake up from sleep generate multiple interrupts 5. incorrect cpu behavior for vbusti and idti interrupts routines the cpu core may incorrectly execute the interrupt v ector related to the vbusti and idti interrupt flags. problem fix/workaround do not enable these interrupts, firm w are must process these usb e v ents by polling vbusti and idti flags. 4. transient perturbation in usb suspend mode generates overconsumption in de v ice mode and w hen the usb is suspended, transient perturbation recei v ed on the usb lines generates a w ake up state. ho w e v er the idle state follo w ing the perturbation does not set the suspi bit. the internal usb engine remains in suspend mode but the usb differ- ential recei v er is still enabled and generates a typical 300a extra-po w er consumption. detection of the suspend state after the transient perturbation should be performed by soft- w are (instead of reading the suspi bit). problem fix/workaround usb w ai v er allo w s bus po w ered de v ices to consume up to 2.5ma in suspend state. 3. spike on twi pins when twi is enabled 100ns negati v e spike occurs on sda and scl pins w hen twi is enabled. problem fix/workaround no kno w n w orkaround, enable at90usb64/128 twi first, before the others nodes of the twi net w ork. 2. high current consumption in sleep mode if a pending interrupt cannot w ake the part up from the selected mode, the current consump- tion w ill increase during sleep w hen executing the sleep instruction directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to w ake up the part from sleep mode should be disabled. 1. asynchronous timer interrupt wake up from sleep generates multiple interrupts if the cpu core is in sleep mode and w akes-up from an asynchronous timer interrupt and then goes back into sleep mode, it may w ake up multiple times. 440 7593l?avr?09/12 at90usb64/128 problem fix/workaround a soft w are w orkaround is to w ait before performing the sleep instruction: until tcnt2>ocr2+1. 441 7593l?avr?09/12 at90usb64/128 37.1.5 atmel at90usb1287/6 fourth release ? transient perturbation in usb suspend mode generates o v er consumption ? spike on twi pins w hen twi is enabled ? high current consumption in sleep mode ? async timer interrupt w ake up from sleep generate multiple interrupts 4. transient perturbation in usb suspend mode generates overconsumption in de v ice mode and w hen the usb is suspended, transient perturbation recei v ed on the usb lines generates a w ake up state. ho w e v er the idle state follo w ing the perturbation does not set the suspi bit. the internal usb engine remains in suspend mode but the usb differ- ential recei v er is still enabled and generates a typical 300a extra-po w er consumption. detection of the suspend state after the transient perturbation should be performed by soft- w are (instead of reading the suspi bit). problem fix/workaround usb w ai v er allo w s bus po w ered de v ices to consume up to 2.5ma in suspend state. 3. spike on twi pins when twi is enabled 100ns negati v e spike occurs on sda and scl pins w hen twi is enabled. problem fix/workaround no kno w n w orkaround, enable atmel at90usb64/128 twi first, before the others nodes of the twi net w ork. 2. high current consumption in sleep mode if a pending interrupt cannot w ake the part up from the selected mode, the current consump- tion w ill increase during sleep w hen executing the sleep instruction directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to w ake up the part from sleep mode should be disabled. 1. asynchronous timer interrupt wake up from sleep generates multiple interrupts if the cpu core is in sleep mode and w akes-up from an asynchronous timer interrupt and then goes back into sleep mode, it may w ake up multiple times. problem fix/workaround a soft w are w orkaround is to w ait before performing the sleep instruction: until tcnt2>ocr2+1. 442 7593l?avr?09/12 at90usb64/128 37.2 atmel at90usb646/7 errata 37.2.1 at90usb646/7 errata history tbd note ?*? means a blank or any alphanumeric string. 37.2.2 at90usb646/7 first release. ? incorrect interrupt routine execution for vbusti, idti interrupts flags ? usb eye diagram v iolation in lo w -speed mode ? transient perturbation in usb suspend mode generates o v er consumption ? spike on twi pins w hen twi is enabled ? high current consumption in sleep mode ? async timer interrupt w ake up from sleep generate multiple interrupts 6. incorrect cpu behavior for vbusti and idti interrupts routines the cpu core may incorrectly execute the interrupt v ector related to the vbusti and idti interrupt flags. problem fix/workaround do not enable these interrupts, firm w are must process these usb e v ents by polling vbusti and idti flags. 5. usb eye diagram violation in low-speed mode the lo w to high transition of d- v iolates the usb eye diagram specification w hen transmitting w ith lo w -speed signaling. problem fix/workaround none. 4. transient perturbation in usb suspend mode generates overconsumption in de v ice mode and w hen the usb is suspended, transient perturbation recei v ed on the usb lines generates a w ake up state. ho w e v er the idle state follo w ing the perturbation does not set the suspi bit anymore. the internal usb engine remains in suspend mode but the usb differential recei v er is still enabled and generates a typical 300a extra-po w er con- sumption. detection of the suspend state after the transient perturbation should be performed by soft w are (instead of reading the suspi bit). problem fix/workaround usb w ai v er allo w s bus po w ered de v ices to consume up to 2.5ma in suspend state. 3. spike on twi pins when twi is enabled 100ns negati v e spike occurs on sda and scl pins w hen twi is enabled. silicon release 90usb646-16mu 90usb647-16au 90usb647-16mu first release second release 443 7593l?avr?09/12 at90usb64/128 problem fix/workaround no kno w n w orkaround, enable atmel at90usb64/128 twi first v ersus the others nodes of the twi net w ork. 2. high current consumption in sleep mode if a pending interrupt cannot w ake the part up from the selected mode, the current consump- tion w ill increase during sleep w hen executing the sleep instruction directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to w ake up the part from the sleep mode should be disabled. 1. asynchronous timer interrupt wake up from sleep generates multiple interrupts if the cpu core is in sleep and w akes-up from an asynchronous timer interrupt and then go back in sleep mode again it may w ake up se v eral times. problem fix/workaround a soft w are w orkaround is to w ait w ith performing the sleep instruction until tcnt2>ocr2+1. 444 7593l?avr?09/12 at90usb64/128 37.2.3 atmel at90usb646/7 second release. ? usb eye diagram v iolation in lo w -speed mode ? transient perturbation in usb suspend mode generates o v er consumption ? spike on twi pins w hen twi is enabled ? high current consumption in sleep mode ? async timer interrupt w ake up from sleep generate multiple interrupts 5. usb eye diagram violation in low-speed mode the lo w to high transition of d- v iolates the usb eye diagram specification w hen transmitting w ith lo w -speed signaling. problem fix/workaround none. 4. transient perturbation in usb suspend mode generates overconsumption in de v ice mode and w hen the usb is suspended, transient perturbation recei v ed on the usb lines generates a w ake up state. ho w e v er the idle state follo w ing the perturbation does not set the suspi bit anymore. the internal usb engine remains in suspend mode but the usb differential recei v er is still enabled and generates a typical 300a extra-po w er con- sumption. detection of the suspend state after the transient perturbation should be performed by soft w are (instead of reading the suspi bit). problem fix/workaround usb w ai v er allo w s bus po w ered de v ices to consume up to 2.5ma in suspend state. 3. spike on twi pins when twi is enabled 100ns negati v e spike occurs on sda and scl pins w hen twi is enabled. problem fix/workaround no kno w n w orkaround, enable atmel at90usb64/128 twi first v ersus the others nodes of the twi net w ork. 2. high current consumption in sleep mode if a pending interrupt cannot w ake the part up from the selected mode, the current consump- tion w ill increase during sleep w hen executing the sleep instruction directly after a sei instruction. problem fix/workaround before entering sleep, interrupts not used to w ake up the part from the sleep mode should be disabled. 1. asynchronous timer interrupt wake up from sleep generates multiple interrupts if the cpu core is in sleep and w akes-up from an asynchronous timer interrupt and then go back in sleep mode again it may w ake up se v eral times. problem fix/workaround a soft w are w orkaround is to w ait w ith performing the sleep instruction until tcnt2>ocr2+1. 445 7593l?avr?09/12 at90usb64/128 38. datasheet revision history for atmel at90usb64/128 please note that the referring page numbers in th is section are referred to this document. the referring re v ision in this section are re ferring to the document re v ision. 38.1 changes from 7593a to 7593b 1. changed default configuration for fuse bytes and security byte. 2. suppression of timer 4,5 registers w hich does not exist. 3. updated typical application schematics in usb section 38.2 changes from 7593b to 7593c 1. update to package dra w ings, mqfp64 and tqfp64. 38.3 changes from 7593c to 7593d 1. for further product compatibility, changed usb pll po ssible prescaler configurations. only 8mhz and 16mhz crystal frequencies allo w s usb operation (see table 7-11 on page 50 ). 38.4 changes from 7593d to 7593e 1. updated pll prescaler table: configuration w ords are different bet w een at90usb64x and at90usb128x to enable the pll w ith a 16mhz source. 2. cleaned up some bits from usb registers, and updated information about otg timers, remote w ake-up, reset and connection timings. 3. updated clock distribution tree diagram (usb prescaler source and configuration register). 4. cleaned up register summary. 5. suppressed pcint23:8 that do not exist from external interrupts. 6. updated electrical characteristics. 7. added typical characteristics. 8. update errata section. 38.5 changes from 7593e to 7593f 1. remo v ed ?preliminary? from document status. 2. clarification in stand by mode regarding usb. 38.6 changes from 7593f to 7593g 1. updated errata section. 38.7 changes from 7593g to 7593h 1. added signature information for 64k de v ices. 2. fixed figure for typical bus po w ered application 3. added min/max v alues for bod le v els 4. added atmega32u6 product 5. update errata section 6. modified descriptions for hwupe and wakeupe interrupts enable (these interrupts should be enabled only to w ake up the cpu core from po w er do w n mode). 446 7593l?avr?09/12 at90usb64/128 7. added description to access unique serial number located in signature ro w see ?reading the signature ro w from soft w are? on page 354 . 38.8 changes from 7593h to 7593i 1. updated table 9-2 in ?bro w n-out detection? on page 60 . unused bod le v els remo v ed. 38.9 changes from 7593i to 7593j 1. updated table 9-2 in ?bro w n-out detection? on page 60 . bod le v el 100 remo v ed. 2. updated ?ordering information? on page 426 . 3. remo v ed atmega32u6 errata section. 38.10 changes from 7593j to 7593k 1. corrected figure 6-7 on page 34 , figure 6-8 on page 34 and figure 6-9 on page 35 . 2. corrected ordering information for section 35.3 ?atmel at90usb1286? on page 428 , section 35.4 ?atmel at90usb1287? on page 429 and section 35.2 ?atmel at90usb647? on page 427 . 3. remo v ed the atmega32u6 de v ice and updated the datasheet accordingly. 4. updated assembly code example in ?watchdog reset? on page 61 . 38.11 changes from 7593k to 7593l 1. updated the ?ordering information? on page 426 . changed the speed from 20mhz to 16mhz. 2. replaced atmegaat90usbxxxx by at90usbxxxx through the datasheet. 3. updated the first paragraph of ?o v er v ie w ? on page 307 . port a replaced by port f. 4. updated adc equation in ?adc con v ersion result? on page 318 . the equation has 1024 instead of 1023. 5. created ?packaging information? chapter. 6. replaced the ?qfn64? packaging by an updated qfn64 packaging dra w ing. 7. updated ?errata? on page 434 . at90usb1286/7 has a fourth release, w hile at90usb646/7 updated w ith a second release. 8. in section ?o v er v ie w ? on page 307 , ?port a? has been replaced by ?port f? in the first section. 9. in section ?atmel at90usb647? on page 427 the usb interface has been changed to usb otg. 10. in section ?atmel at90usb1286? on page 428 the usb interface has been changed to de v ice. 11. in section ?atmel at90usb1287? on page 429 the usb interface has been changed to host otg. 12. general update according to ne w template. i 7593l?avr?09/12 at90usb64x/128x table of contents features ................ ................ .............. ............... .............. .............. ............ 1 1 pin configurations .............. .............. ............... .............. .............. ............ 3 2 overview ............ ................ ................ ............... .............. .............. ............ 5 2.1 block diagram ..........................................................................................................6 2.2 pin descriptions .......................................................................................................8 3 resources .............. .............. .............. ............... .............. .............. .......... 10 4 about code examples .............. ................ ................. ................ ............. 10 5 avr cpu core ................. ................ ................. .............. .............. .......... 11 5.1 introduction ............................................................................................................11 5.2 architectural o v er v ie w ...........................................................................................11 5.3 alu ? arithmetic logic unit ..................................................................................12 5.4 status register .......................................................................................................13 5.5 general purpose register file .................................................................................14 5.6 stack pointer .........................................................................................................15 5.7 instruction execution timing ...................................................................................16 5.8 reset and interrupt handling .................................................................................17 6 atmel avr at90usb64/128 memories ....... ................. .............. .......... 20 6.1 in-system re-programmable flash program memory .............................................20 6.2 sram data memory ..............................................................................................21 6.3 eeprom data memory .........................................................................................24 6.4 i/o memory ............................................................................................................30 6.5 external memory interface ....................................................................................31 7 system clock and clock options ............... ................ ................. .......... 40 7.1 clock systems and their distribution ......................................................................40 7.2 clock sources ........................................................................................................41 7.3 lo w po w er crystal oscillator ..................................................................................42 7.4 lo w frequency crystal oscillator ............................................................................44 7.5 calibrated internal rc o scillator ............................................................................45 7.6 external clock ........................................................................................................46 7.7 clock output buffer ................................................................................................47 7.8 timer/counter oscillator ......................... ................................................................47 7.9 system clock prescaler .........................................................................................47 ii 7593l?avr?09/12 at90usb64x/128x 7.10 pll ......................................................................................................................4 9 8 power management and sleep mo des ............... .............. ............ ........ 51 8.1 idle mode ...............................................................................................................52 8.2 adc noise reduction mode ...................................................................................52 8.3 po w er-do w n mode ................................................................................................52 8.4 po w er-sa v e mode .................................................................................................52 8.5 standby mode .......................................................................................................53 8.6 extended standby mode .......................................................................................53 8.7 po w er reduction register .....................................................................................54 8.8 minimizing po w er consumption .............................................................................55 9 system control and reset ........ ................ ................. ................ ............. 57 9.1 resetting the avr .................................................................................................57 9.2 reset sources .......................................................................................................57 9.3 po w er-on reset ......................................................................................................58 9.4 external reset ........................................................................................................59 9.5 bro w n-out detection ..............................................................................................60 9.6 watchdog reset .....................................................................................................61 9.7 internal v oltage reference ......................................................................................62 9.8 watchdog timer .....................................................................................................63 10 interrupts ............... .............. .............. ............... .............. .............. .......... 68 10.1 interrupt v ectors in at90usb64/128 ...................................................................68 11 i/o-ports ........ ................ ................. ................ ................. .............. .......... 71 11.1 introduction ..........................................................................................................71 11.2 ports as general digital i/o ..................................................................................72 11.3 alternate port functions .......................................................................................76 11.4 register description for i/o-ports ........................................................................89 12 external interrupts .......... ................ ................. .............. .............. .......... 92 13 timer/counter0, timer/counter1, and timer/counter3 prescalers ... 96 13.1 internal clock source ...........................................................................................96 13.2 prescaler reset ....................................................................................................96 13.3 external clock source ..........................................................................................96 13.4 gtccr ? general timer/counter control register ............................................97 14 8-bit timer/counter0 with pw m .............. ................. ................ ............. 98 14.1 o v er v ie w .............................................................................................................98 iii 7593l?avr?09/12 at90usb64x/128x 14.2 timer/counter clock sources ...............................................................................99 14.3 counter unit .........................................................................................................99 14.4 output compare unit ..........................................................................................100 14.5 compare match output unit ..............................................................................102 14.6 modes of operation ............................................................................................103 14.7 timer/counter timing diagrams .........................................................................107 14.8 8-bit timer/counter register description ............................................................108 15 16-bit timer/counter (timer/counte r1 and timer/counter3) ........... 115 15.1 o v er v ie w ...........................................................................................................115 15.2 accessing 16-bit registers .................................................................................117 15.3 timer/counter clock sources .............................................................................120 15.4 counter unit .......................................................................................................121 15.5 input capture unit ..............................................................................................122 15.6 output compare units .......................................................................................124 15.7 compare match output unit ..............................................................................126 15.8 modes of operation ............................................................................................127 15.9 timer/counter timing diagrams .........................................................................134 15.10 16-bit timer/counter register description ........................................................136 16 8-bit timer/counter2 with pw m and asynchronous operation ........ 145 16.1 o v er v ie w ...........................................................................................................145 16.2 timer/counter clock sources .............................................................................146 16.3 counter unit .......................................................................................................146 16.4 output compare unit .........................................................................................147 16.5 compare match output unit ..............................................................................149 16.6 modes of operation ............................................................................................150 16.7 timer/counter timing diagrams .........................................................................154 16.8 8-bit timer/counter register description ............................................................156 16.9 asynchronous operation of the timer/counter ..................................................161 16.10 timer/counter prescaler ..................................................................................164 17 output compare modulato r (ocm1c0a) ....... .............. .............. ........ 166 17.1 o v er v ie w ...........................................................................................................166 17.2 description ........................................................................................................166 18 spi ? serial peripheral interface ......... .............. .............. ............ ........ 168 18.1 ss pin functionality ..........................................................................................172 18.2 data modes .......................................................................................................175 iv 7593l?avr?09/12 at90usb64x/128x 19 usart ............. ................. ................ .............. .............. .............. ........... 177 19.1 o v er v ie w ...........................................................................................................177 19.2 clock generation ...............................................................................................178 19.3 frame formats ...................................................................................................180 19.4 usart initialization ...........................................................................................181 19.5 data transmission ? the usart transmitter ....................................................182 19.6 data reception ? the usart recei v er ..............................................................185 19.7 asynchronous data reception ............................................................................189 19.8 multi-processor communication mode ..............................................................192 19.9 usart register description ...............................................................................193 19.10 examples of baud rate setting .........................................................................198 20 usart in spi mode .......... .............. .............. .............. .............. ........... 202 20.1 o v er v ie w ...........................................................................................................202 20.2 clock generation ...............................................................................................202 20.3 spi data modes and timing ...............................................................................203 20.4 frame formats ...................................................................................................203 20.5 data transfer ......................................................................................................205 20.6 usart mspim register description ..................................................................207 20.7 avr usart mspim v s. avr spi ....................................................................209 21 2-wire serial interface ....... .............. .............. .............. .............. ........... 211 21.1 features ............................................................................................................211 21.2 2- w ire serial interface bus definition .................................................................211 21.3 data transfer and frame format .........................................................................212 21.4 multi-master bus systems, arbitration and synchronization ...............................215 21.5 o v er v ie w of the twi module .............................................................................216 21.6 twi register description ....................................................................................219 21.7 using the twi ....................................................................................................222 21.8 transmission modes .........................................................................................225 21.9 multi-master systems and arbitration .................................................................239 22 usb controller ................... .............. .............. .............. .............. ........... 241 22.1 features ............................................................................................................241 22.2 block diagram ....................................................................................................241 22.3 typical application implementation ...................................................................242 22.4 general operating modes ..................................................................................246 22.5 po w er modes ....................................................................................................250 v 7593l?avr?09/12 at90usb64x/128x 22.6 speed control ....................................................................................................251 22.7 memory management .......................................................................................252 22.8 pad suspend ....................................................................................................253 22.9 otg timers customizing ....................................................................................254 22.10 plug-in detection ..............................................................................................255 22.11 id detection .....................................................................................................256 22.12 registers description .......................................................................................256 22.13 usb soft w are operating modes .....................................................................261 23 usb device operating modes ................. ................. ................ ........... 262 23.1 introduction ........................................................................................................262 23.2 po w er-on and reset ...........................................................................................262 23.3 endpoint reset ...................................................................................................262 23.4 usb reset ..........................................................................................................263 23.5 endpoint selection .............................................................................................263 23.6 endpoint acti v ation ............................................................................................263 23.7 address setup ...................................................................................................264 23.8 suspend, w ake-up and resume .........................................................................265 23.9 detach ...............................................................................................................265 23.10 remote wake-up ............................................................................................266 23.11 stall request ................................................................................................266 23.12 control endpoint management ..................................................................267 23.13 out endpoint management ............................................................................268 23.14 in endpoint management ................................................................................269 23.15 isochronous mode ...........................................................................................271 23.16 o v erflo w ..........................................................................................................272 23.17 interrupts .........................................................................................................272 23.18 registers .........................................................................................................273 24 usb host operating mode s ................. .............. .............. ............ ........ 285 24.1 pipe description .................................................................................................285 24.2 detach ...............................................................................................................285 24.3 po w er-on and reset ...........................................................................................285 24.4 de v ice detection ................................................................................................286 24.5 pipe selection ....................................................................................................286 24.6 pipe configuration ..............................................................................................286 24.7 usb reset ..........................................................................................................288 vi 7593l?avr?09/12 at90usb64x/128x 24.8 address setup ...................................................................................................288 24.9 remote w ake-up detection ................................................................................288 24.10 usb pipe reset ................................................................................................288 24.11 pipe data access .............................................................................................288 24.12 control pipe management ...............................................................................289 24.13 out pipe management ...................................................................................289 24.14 in pipe management .......................................................................................290 24.15 interrupt system ...............................................................................................291 24.16 registers .........................................................................................................292 25 analog comparator .......... .............. .............. .............. .............. ........... 304 25.1 analog comparator multiplexed input ...............................................................306 26 adc ? analog to digital co nverter .............. .............. .............. ........... 307 26.1 features ............................................................................................................307 26.2 o v er v ie w ...........................................................................................................307 26.3 operation ...........................................................................................................309 26.4 starting a con v ersion .........................................................................................309 26.5 prescaling and con v ersion timing ......................................................................310 26.6 changing channel or reference selection ..........................................................313 26.7 adc noise canceler ...........................................................................................314 26.8 adc con v ersion result .......................................................................................318 26.9 adc register description ...................................................................................321 27 jtag interface and on-chi p debug system .............. .............. ........... 327 27.1 o v er v ie w ...........................................................................................................327 27.2 tap ? test access port ....................................................................................327 27.3 tap controller ...................................................................................................329 27.4 using the boundary-scan chain ........................................................................330 27.5 using the on-chip debug system .......................................................................330 27.6 on-chip debug specific jtag instructions .........................................................331 27.7 on-chip debug related register in i/o memory ................................................332 27.8 using the jtag programming capabilitie s ........................................................332 27.9 bibliography .......................................................................................................332 28 ieee 1149.1 (jtag) boundary-scan .......... ................ .............. ........... 333 28.1 features ............................................................................................................333 28.2 system o v er v ie w ...............................................................................................333 28.3 data registers ....................................................................................................333 vii 7593l?avr?09/12 at90usb64x/128x 28.4 boundary-scan specific jtag instructions ........................................................335 28.5 boundary-scan related register in i/o memory ...............................................336 28.6 boundary-scan chain .........................................................................................337 28.7 atmel at90usb64/128 boundary-scan order ...................................................340 28.8 boundary-scan description language files .........................................................342 29 boot loader support ? read-while-write self-programmi ng ............. 343 29.1 boot loader features .........................................................................................343 29.2 application and boot loader flash sections ......................................................343 29.3 read- w hile- w rite and no read- w hile- w rite flash sections ...................................343 29.4 boot loader lock bits .........................................................................................346 29.5 entering the boot loader program ....................................................................347 29.6 addressing the flash during self-programming ..................................................350 29.7 self-programming the flash ...............................................................................351 30 memory programming ........... ................ ................. ................ ............. 359 30.1 program and data memory lock bits ..................................................................359 30.2 fuse bits ............................................................................................................360 30.3 signature bytes .................................................................................................362 30.4 calibration byte .................................................................................................362 30.5 parallel programming parameters, pin mapping, and commands .....................362 30.6 parallel programming ........................................................................................365 30.7 serial do w nloading ............................................................................................373 30.8 serial programming pin mapping ......................................................................374 30.9 programming v ia the jtag interface ................................................................377 31 electrical characteristics for atmel at90usb64/128 ........ ............... 390 31.1 absolute maximum ratings* ...............................................................................390 31.2 dc characteristics .............................................................................................390 31.3 external clock dri v e w a v eforms .........................................................................392 31.4 external clock dri v e ...........................................................................................392 31.5 maximum speed v s. v cc ........................................................................................................................... 3 92 31.6 2- w ire serial interface characteristics ................................................................393 31.7 spi timing characteristics ..................................................................................395 31.8 hard w are boot entrance timing characteristics .................................................396 31.9 adc characteristics ...........................................................................................397 31.10 external data memory timing ...........................................................................399 32 atmel at90usb64/128 typi cal characteristics ........ .............. ........... 404 viii 7593l?avr?09/12 at90usb64x/128x 32.1 input v oltage le v els ............................................................................................405 32.2 output v oltage le v els .........................................................................................406 32.3 po w er-do w n supply current ...............................................................................408 32.4 po w er-sa v e supply current ................................................................................409 32.5 idle supply current .............................................................................................410 32.6 acti v e supply current .........................................................................................410 32.7 reset supply current .........................................................................................411 32.8 i/o pull-up current ..............................................................................................411 32.9 bandgap v oltage ...............................................................................................412 32.10 internal aref v oltage .......................................................................................413 32.11 usb regulator ..................................................................................................413 32.12 bod le v els ......................................................................................................414 32.13 watchdog timer frequency ..............................................................................416 32.14 internal rc oscillator frequency ........ ..............................................................416 32.15 po w er-on reset ................................................................................................418 33 register summary ............. .............. .............. .............. .............. ........... 419 34 instruction set summary .... .............. ............... .............. .............. ........ 423 35 ordering information .......... .............. ............... .............. .............. ........ 426 35.1 atmel at90usb646 ..........................................................................................426 35.2 atmel at90usb647 ..........................................................................................427 35.3 atmel at90usb1286 ........................................................................................428 35.4 atmel at90usb1287 ........................................................................................429 36 packaging information .......... ................ ................. ................ ............. 430 36.1 tqfp64 .............................................................................................................430 36.2 qfn64 ...............................................................................................................432 37 errata ........... ................ ................ ................. ................ .............. ........... 434 37.1 atmel at90usb1287/6 errata ...........................................................................434 37.2 atmel at90usb646/7 errata .............................................................................442 38 datasheet revision history for atme l at90usb64/128 ...... ............... 445 38.1 changes from 7593a to 7593b .........................................................................445 38.2 changes from 7593b to 7593c .........................................................................445 38.3 changes from 7593c to 7593d .........................................................................445 38.4 changes from 7593d to 7593e .........................................................................445 38.5 changes from 7593e to 7593f .........................................................................445 ix 7593l?avr?09/12 at90usb64x/128x 38.6 changes from 7593f to 7593g .........................................................................445 38.7 changes from 7593g to 7593h ........................................................................445 38.8 changes from 7593h to 7593i ..........................................................................446 38.9 changes from 7593i to 7593j ...........................................................................446 38.10 changes from 7593j to 7593k ........................................................................446 38.11 changes from 7593k to 7593l .......................................................................446 table of contents ............. ................ ................. ................ .............. ........... i 7593l?avr?09/12 atmel corporation 2325 orchard park w ay san jose, ca 95131 usa tel : (+1)(408) 441-0311 fax : (+1)(408) 487-2600 www .atmel.com atmel asia limited unit 1-5 & 16, 19/f bea to w er, millennium city 5 418 k w un tong road k w un tong, ko w loon hong kong tel : (+852) 2245-6100 fax : (+852) 2722-1369 atmel munich gmbh business campus parkring 4 d-85748 garching b. munich germany tel : (+49) 89-31970-0 fax : (+49) 89-3194621 atmel japan 16f, shin osaki kangyo bldg. 1-6-4 osaki shinaga w a-ku tokyo 104-0032 japan tel : (+81) 3-6417-0300 fax : (+81) 3-6417-0370 ? 2012 atmel corporation. all rights reserved. atmel ? , atmel logo and combinations thereof, avr ? , avr studio ? , and others are registered trademarks or trademarks of atmel cor- poration or its subsidiaries. windo w s ? is a registered trademark of microsoft corporat ion in u.s. and or other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is pro v ided in connection w ith atmel products. no license, expr ess or implied, by estoppel or other w ise, to any intellectual property right is granted by this document or in connection w ith the sale of atmel products. except as set forth in the atmel terms and conditions of sales located on the atmel website, atmel assumes no liability whatsoever and disclaims any express, implied or statutory warranty relating to its pro ducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purp ose, or non-infringement. in no even t shall atmel be liable for any direct, indirect, consequential, punitive, special or incidental damages (including, without limitati on, damages for loss and prof- its, business interruption, or loss of information) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no representations or w arranties w ith respect to the accuracy or com- pleteness of the contents of this document and reser v es the right to make changes to specificat ions and product descriptions at any time w ithout notice. atmel does not make any commitment to update the in formation contained herein. unless specifically pro v ided other w ise, atmel products are not suit- able for, and shall not be used in, automoti v e applications. atmel products are not intended, authorized, or w arranted for use as components in applica- tions intended to support or sustain life. |
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